SRV05-4A Datasheet

SRV05-4A
RailClamp®
Low Capacitance TVS Diode Array
PROTECTION PRODUCTS - RailClamp®
Description
Features
RailClamp® low capacitance TVS array is designed to
protect high speed data interfaces. This series has
been specifically designed to protect sensitive components which are connected to data and transmission
lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and
lightning.
The unique design incorporates eight surge rated, low
capacitance steering diodes and a TVS diode in a
single package. During transient conditions, the
steering diodes direct the transient to either the
positive side of the power supply line or to ground. The
internal TVS diode prevents over-voltage on the power
line, protecting any downstream components.
The SRV05-4A is in a 6-lead SOT-23 package. The
leads are finished with lead-free matte tin. Each
device will protect up to four high-speed lines. They
may be used to meet the ESD immunity requirements
of IEC 61000-4-2. The combination of small size, low
capacitance, and high surge capability makes them
ideal for use in applications such as 10/100 Ethernet,
USB 2.0, and video interfaces.
‹ Protection for high-speed data lines to
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IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20μs)
Array of surge rated diodes with internal TVS Diode
Small package saves board space
Protects four I/O lines
Low capacitance: 3pF typical
Low clamping voltage
Low operating voltage: 5.0V
Solid-state silicon-avalanche technology
Mechanical Characteristics
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JEDEC SOT-23 6L package
Pb-Free, Halogen Free, RoHS/WEEE Compliant
Molding compound flammability rating: UL 94V-0
Marking: V05 + Date Code
Packaging: Tape and Reel
Applications
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Circuit Diagram
USB 2.0 Power and Data Line Protection
Video Graphics Cards
Monitors and Flat Panel Displays
Digital Visual Interface (DVI)
10/100 Ethernet
Notebook Computers
SIM Ports
IEEE 1394 Firewire Ports
Schematic and PIN Configuration
5
1
3
4
6
2
SOT-23 6L (Top View)
Revision 04/19/2010
1
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SRV05-4A
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Symbol
Value
Units
Peak Pulse Power (tp = 8/20μs)
Pp k
300
Watts
Peak Pulse Current (tp = 8/20μs)
IP P
12
A
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
VESD
15
8
kV
Lead Soldering Temperature
TL
260 (10 sec.)
°C
Operating Temperature
TJ
-55 to +125
°C
TSTG
-55 to +150
°C
Storage Temperature
Electrical Characteristics (T=25oC)
Parameter
Symbol
Conditions
Reverse Stand-Off Voltage
VRWM
Pi n 5 to 2
Reverse Breakdown Voltage
V BR
It = 1mA
Pi n 5 to 2
Reverse Leakage Current
IR
VRWM = 5V, T=25°C
Pi n 5 to 2
5
μA
Forward Voltage
VF
If = 15mA
1.2
V
Clamping Voltage
VC
IPP = 1A, tp = 8/20μs
Any I/O pin to Ground
12.5
V
Clamping Voltage
VC
IPP = 5A, tp = 8/20μs
Any I/O pin to Ground
17.5
V
Junction Capacitance
Cj
VR = 0V, f = 1MHz
Any I/O pin to Ground
3
5
pF
VR = 0V, f = 1MHz
Between I/O pins
1.5
© 2010 Semtech Corp.
2
Minimum
Typical
Maximum
Units
5
V
6
V
pF
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SRV05-4A
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
100
90
% of Rated Power or PI P
Peak Pulse Power - PPk (kW)
110
1
0.1
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
0
1000
25
50
75
100
125
150
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
Pulse Waveform
Clamping Voltage vs. Peak Pulse Current
110
Waveform
Parameters:
tr = 8µs
td = 20µs
90
Percent of I
PP
80
70
30.00
Clamping Voltage -VC (V)
100
e-t
60
50
40
td = IPP/2
30
20
25.00
20.00
15.00
10.00
Waveform
Parameters:
tr = 8µs
td = 20µs
5.00
10
0
0.00
0
5
10
15
20
25
30
0.00
2.00
Time (µs)
4.00
6.00
8.00
10.00
12.00
Peak Pulse Current - IPP (A)
Normalized Capacitance vs. Reverse Voltage
Forward Voltage vs. Forward Current
1.4
7.00
CJ(V R) / C J(V R=0)
Forward Voltage -VF (V)
1.2
6.00
5.00
4.00
3.00
Waveform
Parameters:
tr = 8µs
td = 20µs
2.00
1.00
0.8
0.6
0.4
0.2
f = 1 MHz
0
0.00
0.00
1
0
2.00
4.00
6.00
8.00
10.00
1
2
3
4
5
Reverse Voltage - VR (V)
12.00
Forward Current - IF (A)
© 2010 Semtech Corp.
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SRV05-4A
PROTECTION PRODUCTS
Applications Information
Insertion Loss S21
CH1
S21
LOG
START
3 dB/
.030 000 MHz
© 2010 Semtech Corp.
Analog Cross Talk
CH1
REF 0 dB
S21
LOG
START
STOP 3 000. 000 000 MHz
4
20 dB/
.030 000 MHz
REF 0 dB
STOP 3 000. 000 000 MHz
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SRV05-4A
PROTECTION PRODUCTS
Applications Information
Data Line and Power Supply Protection Using Vcc as
reference
Device Connection Options for Protection of Four
High-Speed Data Lines
The SRV05-4A is designed to protect four data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 3, 4 and 6. The
negative reference (REF1) is connected at pin 2. This
pin should be connected directly to a ground plane on
the board for best results. The path length is kept as
short as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 5.
The options for connecting the positive reference are
as follows:
Data Line Protection with Bias and Power Supply
Isolation Resistor
1. To protect data lines and the power line, connect
pin 5 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SRV05-4A can be isolated from the power
supply by adding a series resistor between pin 5
and VCC. A value of 100kΩ is recommended. The
internal TVS and steering diodes remain biased,
providing the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 5 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
Data Line Protection Using Internal TVS Diode as
Reference
ESD Protection With RailClamps®
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where discrete diodes or diode arrays are configured for rail-torail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
© 2010 Semtech Corp.
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SRV05-4A
PROTECTION PRODUCTS
Applications Information (continued)
the reference voltage plus the VF drop of the diode.
For negative events, the bottom diode will be biased
when the voltage exceeds the VF of the diode. At first
approximation, the clamping voltage due to the characteristics of the protection diodes is given by:
PIN Descriptions
VC = VCC + VF
VC = -VF
(for positive duration pulses)
(for negative duration pulses)
However, for fast rise time transient events, the
effects of parasitic inductance must also be considered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
Figure 1 - “RailTo-Rail” Pr
o t ection TTopology
opology
“Rail-T
Pro
(First Approximation)
VC = VCC + VF + LP diESD/dt (for positive duration pulses)
VC = -VF - LG diESD/dt
(for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a VCC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
Figure 2 - The Effects of Parasitic Inductance
When Using Discrete Components to Implement
RailTo-Rail Pr
o t ection
Rail-T
Pro
VC = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
that it is not uncommon for the VF of discrete diodes to
exceed the damage threshold of the protected IC. This
is due to the relatively small junction area of typical
discrete components. It is also possible that the
power dissipation capability of the discrete diode will
be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
© 2010 Semtech Corp.
Figure 3 - RailTo-Rail Pr
o t ection Using
Rail-T
Pro
RailClam
p T V S Arra
ys
RailClamp
Arrays
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SRV05-4A
PROTECTION PRODUCTS
Applications Information (continued)
helps to mitigate the effects of parasitic inductance in
the power supply connection. During an ESD event,
the current will be directed through the integrated TVS
diode to ground. The maximum voltage seen by the
protected IC due to this path will be the clamping
voltage of the device.
Video Interface Protection
Video interfaces are susceptible to transient voltages
resulting from electrostatic discharge (ESD) and “hot
plugging” cables. If left unprotected, the video
interface IC may be damaged or even destroyed.
Protecting a high-speed video port presents some
unique challenges. First, any added protection device
must have extremely low capacitance and low leakage
current so that the integrity of the video signal is not
compromised. Second, the protection component
must be able to absorb high voltage transients without
damage or degradation. As a minimum, the device
should be rated to handle ESD voltages per IEC
61000-4-2, level 4 (±15kV air, ±8kV contact). The
clamping voltage of the device (when conducting high
current ESD pulses) must be sufficiently low enough to
protect the sensitive CMOS IC. If the clamping voltage
is too high, the “protected” device may latch-up or be
destroyed. Finally, the device must take up a relatively
small amount of board space, particularly in portable
applications such as notebooks and handhelds. The
SRV05-4A is designed to meet or exceed all of the
above criteria. A typical video interface protection
circuit is shown in Figure 4. All exposed lines are
protected including R, G, B, H-Sync, V-Sync , and the ID
lines for plug and play monitors.
Figure 4 - Video Interface Protection
SRV05-4A
Figure 5 - Dual USB Port Protection
Universal Serial Bus ESD Protection
The SRV05-4A may also be used to protect the USB
ports on monitors, computers, peripherals or portable
systems. Each device will protect up to two USB ports
(Figure 5). When the voltage on the data lines exceed
the bus voltage (plus one diode drop), the internal
rectifiers are forward biased conducting the transient
current away from the protected controller chip. The
TVS diode directs the surge to ground. The TVS diode
also acts to suppress ESD strikes directly on the
voltage bus. Thus, both power and data pins are
protected with a single device.
SRV05-4A
Figure 6 - SIM Port
© 2010 Semtech Corp.
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SRV05-4A
PROTECTION PRODUCTS
DVI Protection
10/100 ETHERNET PROTECTION
The small geometry of a typical digital-visual interface
(DVI) graphic chip will make it more susceptible to
electrostatic discharges (ESD) and cable discharge
events (CDE). Transient protection of a DVI port can
be challenging. Digital-visual interfaces can often
transmit and receive at a rate equal to or above
1Gbps. The high-speed data transmission requires the
protection device to have low capacitance to maintain
signal integrity and low clamping voltage to reduce
stress on the protected IC. The SRV05-4A has a low
typical insertion loss of <0.4dB at 1GHz (I/O to ground)
to ensure signal integrity and can protect the DVI
interface to the 8kV contact and 15kV air ESD per IEC
61000-4-2 and CDE.
Ethernet ICs are vulnerable to damage from electrostatic discharge (ESD). The internal protection in the
PHY chip, if any, often is not enough due to the high
energy of the discharges specified by IEC 61000-4-2.
If the discharge is catastrophic, it will destroy the
protected IC. If it is less severe, it will cause latent
failures that are very difficult to find.
In a typical 10/100 system, the twisted-pair interface
for each port consists of two differential signal pairs:
one for the transmitter and one for the receiver, with
the transmitter input being the most sensitive to
damage. The fatal discharge occurs differentially
across the transmit or receive line pair and is capacitively coupled through the transformer to the Ethernet
chip. Figure 8 shows how to design the SRV05-4A on
the line side of a 10/100 ethernet port to provide
differential mode protection. The common mode
isolation of the transformer will provide common mode
protection to the rating of the transformer isolation
which is usually >1.5kV. Figure 9 shows how to
implement the SRV05-4A on the IC side of the 10/
100 Ethernet circuit.
Figure 7 shows how to design the SRV05-4A into the
DVI circuit on a flat panel display and a PC graphic
card. The SRV05-4A is configured to provide common
mode and differential mode protection. The internal
TVS of the SRV05-4A acts as a 5 volt reference. The
power pin of the DVI circuit does not come out through
the connector and is not subjected to external ESD
pulse; therefore, pin 5 should be left unconnected.
Connecting pin 5 to Vcc of the DVI circuit may result in
damage to the chip from ESD current.
Figure 7 - Digital Visual Interface (DVI) Protection
© 2010 Semtech Corp.
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SRV05-4A
PROTECTION PRODUCTS
SRV05-4A
Figure 8 - 10/100 Ethernet Differential Protection
SRV05-4A
Figure 9 - 10/100 Ethernet Differential and Common Mode Protection
© 2010 Semtech Corp.
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SRV05-4A
PROTECTION PRODUCTS
Outline Drawing
Drawing -SOT23
- SO-8 6L
Outline
DIM
A
e1
2X E/2
A
A1
A2
b
c
D
E1
E
e
e1
L
L1
N
01
aaa
bbb
ccc
D
N
EI
1
E
2
ccc C
2X N/2 TIPS
e
B
D
aaa C
A2
SEATING
PLANE
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
.057
.035
.006
.000
.035 .045 .051
.020
.010
.009
.003
.110 .114 .122
.060 .063 .069
.110 BSC
.037 BSC
.075 BSC
.012 .018 .024
(.024)
6
10°
0°
.004
.008
.008
1.45
0.90
0.00
0.15
.90 1.15 1.30
0.25
0.50
0.08
0.22
2.80 2.90 3.10
1.50 1.60 1.75
2.80 BSC
0.95 BSC
1.90 BSC
0.30 0.45 0.60
(0.60)
6
0°
10°
0.10
0.20
0.20
A
H
A1
C
bxN
bbb
c
GAGE
PLANE
C A-B D
0.25
L
01
(L1)
DETAIL
A
SEE DETAIL
A
SIDE VIEW
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
Land Pattern -SOT23 6L
X
DIM
(C)
G
Z
Y
P
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.098)
.055
.037
.024
.043
.141
(2.50)
1.40
0.95
0.60
1.10
3.60
NOTES:
1.
© 2010 Semtech Corp.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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SRV05-4A
PROTECTION PRODUCTS
Marking Codes
YW
V05
Ordering Information
Part Number
Lead Finish
Qty per
Reel
R eel Size
SRV05-4ATCT
Matte Tin
3,000
7 Inch
YW = 2 - Alphanumeric characters for Date Code
Tape and Reel Specification
Pin 1 Location
User Direction of feed
A0
3.23 +/-0.05 mm
B0
K0
3.17 +/-0.05 mm
Tape
Width
B, (Max)
D
8 mm
4.2 mm
(.165)
1.5 + 0.1 mm
- 0.0 mm
1.37 +/-0.05 mm
D1
E
1.0 mm
±0.05
1.750±.10
mm
F
K
(MAX)
P
P0
P2
T(MAX)
3.5±0.05
mm
2.4 mm
4.0±0.1
mm
4.0±0.1
mm
2.0±0.05
mm
0.4 mm
W
8.0 mm
+ 0.3 mm
- 0.1 mm
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2010 Semtech Corp.
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