SEMTECH SR05.TCT

SR05
RailClamp
Low Capacitance TVS Diode Array
PROTECTION PRODUCTS
Description
Features
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive components which are connected to data and transmission
lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (EFT), and
lightning.
The unique design of the SR series devices incorporates four surge rated, low capacitance steering diodes
and a TVS diode in a single package. During transient
conditions, the steering diodes direct the transient to
either the positive side of the power supply line or to
ground. The internal TVS diode prevents over-voltage
on the power line, protecting any downstream components.
The low capacitance array configuration allows the user
to protect two high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges.
‹ ESD protection to
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IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20µs)
Array of surge rated diodes with internal TVS Diode
Protects two I/O lines
Low capacitance (<10pF) for high-speed interfaces
Low clamping voltage
Low operating voltage: 5.0V
Solid-state silicon-avalanche technology
Mechanical Characteristics
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JEDEC SOT-143 package
UL 497B listed
Molding compound flammability rating: UL 94V-0
Marking : R05
Packaging : Tape and Reel per EIA 481
Applications
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Circuit Diagram
USB Power & Data Line Protection
Ethernet 10BaseT
I2C Bus Protection
Video Line Protection
T1/E1 secondary IC Side Protection
Portable Electronics
Microcontroller Input Protection
WAN/LAN Equipment
ISDN S/T Interface
Schematic & PIN Configuration
Pin 4
1
Pin 2
4
Pin 3
2
3
Pin 1
SOT-143 (Top View)
Revision 02/18/05
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SR05
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Symbol
Value
Units
Peak Pulse Power (tp = 8/20µs)
Pp k
500
Watts
Peak Pulse Current (tp = 8/20µs)
IP P
25
A
Peak Forward Voltage (IF = 1A, tp=8/20µs)
VFP
1.5
V
Lead Soldering Temperature
TL
260 (10 sec.)
°C
Operating Temperature
TJ
-55 to +125
°C
TSTG
-55 to +150
°C
Storage Temperature
Electrical Characteristics
SR 05
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Units
5
V
Reverse Stand-Off Voltage
VRWM
Reverse Breakdown Voltage
V BR
It = 1mA
Reverse Leakage Current
IR
VRWM = 5V, T=25°C
5
µA
Clamping Voltage
VC
IPP = 1A, tp = 8/20µs
9.8
V
Clamping Voltage
VC
IPP = 10A, tp = 8/20µs
12
V
Clamping Voltage
VC
IPP = 25A, tp = 8/20µs
20
V
Junction Capacitance
Cj
Between I/O pins and
Ground
VR = 0V, f = 1MHz
6
10
pF
Between I/O pins
VR = 0V, f = 1MHz
3
 2005 Semtech Corp.
2
6
V
pF
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SR05
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Power Derating Curve
10
110
% of Rated Power or PI P
Peak Pulse Power - PPk (kW)
100
1
0.1
90
80
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
0
1000
25
Pulse Waveform
75
100
125
150
Clamping Voltage vs. Peak Pulse Current
18
110
Waveform
Parameters:
tr = 8µs
td = 20µs
90
80
70
16
Clamping Voltage - V C (V)
100
Percent of IPP
50
Ambient Temperature - TA (oC)
Pulse Duration - tp (µs)
-t
e
60
50
40
td = IPP/2
30
20
10
14
12
10
8
Waveform
Parameters:
tr = 8µs
td = 20µs
6
4
2
0
0
5
10
15
20
25
30
0
Time (µs)
0
5
10
15
20
25
Peak Pulse Current - IPP (A)
Forward Voltage vs. Forward Current
Capacitance vs. Reverse Voltage
10
0
-2
8
% Change in Capacitance
Forward Voltage - V F (V)
9
7
6
5
4
3
Waveform
Parameters:
tr = 8µs
td = 20µs
2
1
-4
-6
-8
-10
-12
-14
-16
0
0
5
10
15
20
25
30
35
40
45
0
50
 2005 Semtech Corp.
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2
3
4
5
6
Reverse Voltage - VR (V)
Forward Current - IF (A)
3
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SR05
PROTECTION PRODUCTS
Applications Information
Data Line and Power Supply Protection Using Vcc as
reference
Device Connection Options for Protection of Two
High-Speed Data Lines
The SR05 TVS is designed to protect two data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode VF) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 2 and 3. The negative reference (REF1) is connected at pin 1. This pin
should be connected directly to a ground plane on the
board for best results. The path length is kept as short
as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 4.
The options for connecting the positive reference are
as follows:
Data Line Protection with Bias and Power Supply
Isolation Resistor
1. To protect data lines and the power line, connect
pin 4 directly to the positive supply rail (VCC). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SR05 can be isolated from the power supply by
adding a series resistor between pin 4 and VCC. A
value of 10kΩ is recommended. The internal TVS
and steering diodes remain biased, providing the
advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 4 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
Data Line Protection Using Internal TVS Diode as
Reference
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where discrete diodes or diode arrays are configured for rail-torail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the VF drop of the diode.
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SR05
PROTECTION PRODUCTS
Applications Information (continued)
For negative events, the bottom diode will be biased
when the voltage exceeds the VF of the diode. At first
approximation, the clamping voltage due to the characteristics of the protection diodes is given by:
V
= VDescriptions
+ VF (for positive duration pulses)
PIN
C
CC
(for negative duration pulses)
VC = -VF
However, for fast rise time transient events, the
effects of parasitic inductance must also be considered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
Figure 1 - “RailTo-Rail” Pr
o t ection TTopology
opology
“Rail-T
Pro
(First Approximation)
VC = VCC + VF + LP diESD/dt (for positive duration pulses)
VC = -VF - LG diESD/dt
(for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = LP diESD/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a VCC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
Figure 2 - The Effects of Parasitic Inductance
When Using Discrete Components to Implement
RailTo-Rail Pr
o t ection
Pro
Rail-T
VC = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
that it is not uncommon for the VF of discrete diodes to
exceed the damage threshold of the protected IC. This
is due to the relatively small junction area of typical
discrete components. It is also possible that the
power dissipation capability of the discrete diode will
be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
 2005 Semtech Corp.
Figure 3 - RailTo-Rail Pr
o t ection Using
Rail-T
Pro
RailClam
p T V S Arra
ys
RailClamp
Arrays
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SR05
PROTECTION PRODUCTS
Applications Information (continued)
the power supply connection. During an ESD event,
the current will be directed through the integrated TVS
diode to ground. The total clamping voltage seen by
the protected IC due to this path will be:
VC = VF(RailClamp) + VTVS
This is given in the data sheet as the rated clamping
voltage of the device. For a SR05 the typical clamping
voltage is <16V at IPP=30A. The diodes internal to the
RailClamp are low capacitance, fast switching devices
that are rated to handle transient currents and maintain excellent forward voltage characteristics.
Universal Serial Bus ESD Protection
The figure below illustrates how to use the SR05 to
protect one upstream USB port and the SRDA05-4 to
protect two downstream USB ports. When the voltage
on the data lines exceed the bus voltage (plus one
diode drop), the internal rectifiers are forward biased
conducting the transient current away from the protected controller chip. The TVS diode directs the surge
to ground. The TVS diode also acts to suppress ESD
strikes directly on the voltage bus. Thus, both power
and data pins are protected with a single device.
Reference Semtech application note SI96-18 for
further information.
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small compared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
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SR05
PROTECTION PRODUCTS
Typical Applications
Universal Serial Bus ESD Protection
ISDN S/T Interface Protection
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SR05
PROTECTION PRODUCTS
Outline Drawing - SOT-143
D
A
e
H
e/2
DIM
4
3
GAUGE
PLANE
SEATING
PLANE
B
C
1
c
0.25
L
L1
E
E1
0
DETAIL A
2
bxN
e1
bbb
A2
C A B
SEE DETAIL A
SIDE VIEW
A
A
A1
A2
b
b1
c
D
E
E1
e
e1
L
L1
N
0
aaa
bbb
ccc
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.035
-
.048 0.80
1.22
.006 0.013
0.15
.042 0.75 0.90 1.07
.020 0.30
0.51
.037 0.76
0.94
.008 0.08
0.20
.114 .120 2.80 2.90 3.04
.093 .104 2.10 2.37 2.64
.051 .055 1.20 1.30 1.40
.075
1.92 BSC
.008
0.20 BSC
.015 .020 .024 0.40 0.50 0.60
(.021)
(0.54)
4
4
0°
8°
0°
8°
.006
0.15
.008
0.20
.004
0.10
.031
.000
.029
.011
.029
.003
.110
.082
.047
ccc C
4X
SEATING PLANE
A1
b1
aaa
C
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B-
TO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD TO-253, VARIATION D.
Land Pattern - SOT-143
X1
X1
Y
DIM
Z
C
E1
G
E2
Y
X2
C
E1
E2
G
X1
X2
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.087)
.076
.068
.031
.039
.047
.055
.141
(2.20)
1.92
1.72
0.80
1.00
1.20
1.40
3.60
X1
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A.
 2005 Semtech Corp.
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SR05
PROTECTION PRODUCTS
Marking Codes
Part Number
Marking
Code
SR05
R05
Ordering Information
Par t
Number
Lead Finish
Qty per
Reel
R eel Size
SR05.TC
SnPb
3,000
7 Inch
SR05.TCT
Pb free
3,000
7 Inch
Contact Information
Semtech Corporation
Protection Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2005 Semtech Corp.
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