Data Sheet

PH1875L
N-channel TrenchMOS logic level FET
Rev. 01 — 29 November 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
■ Logic level threshold
■ Low thermal resistance
■ Very low on-state resistance
■ Surface-mounted package
1.3 Applications
■ DC motor control
■ DC-to-DC converters
■ General purpose power switching
1.4 Quick reference data
■ VDS ≤ 75 V
■ RDSon ≤ 16.5 mΩ
■ ID ≤ 45.8 A
■ QGD = 15.3 nC (typ)
2. Pinning information
Table 1:
Pinning
Pin
Description
1, 2, 3
source (S)
4
gate (G)
mb
mounting base; connected to drain (D)
Simplified outline
Symbol
D
mb
G
mbb076
1 2 3 4
SOT669 (LFPAK)
S
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
PH1875L
Package
Name
Description
Version
LFPAK
plastic single-ended surface mounted package; 4 leads
SOT669
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage
25 °C ≤ Tj ≤ 150 °C
-
75
V
VDGR
drain-gate voltage (DC)
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
75
V
VGS
gate-source voltage
-
±15
V
ID
drain current
Tmb = 25 °C; VGS = 10 V; see Figure 2 and 3
-
45.8
A
Tmb = 100 °C; VGS = 10 V; see Figure 2
-
29
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3
-
183
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 1
-
62.5
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−55
+150
°C
Source-drain diode
IS
source current
Tmb = 25 °C
-
45.8
A
ISM
peak source current
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
183
A
unclamped inductive load; ID = 26 A;
tp = 0.11 ms; VDS ≤ 75 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
-
165
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
PH1875L_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
2 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
03aa16
120
03aa23
120
Ider
Pder
(%)
(%)
80
80
40
40
0
0
0
50
100
150
Tmb (°C)
200
0
P tot
P der = ------------------------ × 100 %
P
°
50
100
150
200
Tmb (°C)
ID
I der = --------------------- × 100 %
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aab052
103
ID
(A)
Limit RDSon = VDS / ID
tp =
10 µs
2
10
100 µs
10
1 ms
10 ms
DC
0.1 s
1
10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH1875L_1
Product data sheet
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Rev. 01 — 29 November 2005
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PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
thermal resistance from junction to mounting base see Figure 4
Rth(j-mb)
Min
Typ
Max
Unit
-
-
2
K/W
003aab053
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
10-1
δ=
P
0.02
tp
T
single pulse
t
tp
T
10-2
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH1875L_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
4 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
75
-
-
V
Tj = −55 °C
68
-
-
V
Static characteristics
V(BR)DSS drain-source breakdown
voltage
VGS(th)
IDSS
gate-source threshold voltage
drain leakage current
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
1
1.5
2
V
Tj = 150 °C
0.5
-
-
V
Tj = −55 °C
-
-
2.2
V
VDS = 75 V; VGS = 0 V
Tj = 25 °C
-
-
1
µA
Tj = 150 °C
-
-
500
µA
IGSS
gate leakage current
VGS = ±15 V; VDS = 0 V
-
10
100
nA
RG
gate resistance
f = 1 MHz
-
1
-
Ω
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 20 A; see Figure 6 and 8
Tj = 25 °C
-
13.3
16.5
mΩ
Tj = 150 °C
-
24.2
30
mΩ
VGS = 4.5 V; ID = 20 A; see Figure 6 and 8
-
14.6
20
mΩ
VGS = 5 V; ID = 20 A; see Figure 6 and 8
-
14.2
18
mΩ
ID = 25 A; VDS = 60 V; VGS = 5 V; see
Figure 11 and 12
-
33.4
-
nC
-
6.7
-
nC
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGS1
pre-VGS(th) gate-source charge
-
3.3
-
nC
QGS2
post-VGS(th) gate-source charge
-
3.4
-
nC
QGD
gate-drain charge
-
15.3
-
nC
VGS(pl)
gate-source plateau voltage
-
3
-
V
QG(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
23
-
nC
Ciss
input capacitance
-
2 600
-
pF
Coss
output capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz; see
Figure 14
-
285
-
pF
Crss
reverse transfer capacitance
-
150
-
pF
Ciss
input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
-
4000
-
pF
td(on)
turn-on delay time
VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω
-
23
-
ns
tr
rise time
-
80
-
ns
td(off)
turn-off delay time
-
92
-
ns
tf
fall time
-
60
-
ns
Source-drain diode
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; see Figure 13
-
0.85
1.2
V
trr
reverse recovery time
-
107
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V;
VR = 30 V
-
124
-
nC
PH1875L_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
5 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
003aab054
40
10
ID
(A)
3
2.8
5
4.5
30
003aab055
50
RDSon
(mΩ)
2.2
2.6
2.4
2.8
40
30
2.6
20
3
20
5
4.5
2.4
10
10
VGS (V) = 10
VGS (V) = 2.2
0
0
0
0.5
1
1.5
VDS (V)
0
2
Tj = 25 °C
10
20
30
ID (A)
40
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
003aab056
40
ID
(A)
003aaa918
2.4
a
30
1.6
20
Tj = 150 °C
0.8
25 °C
10
0
0
1
2
VGS (V)
3
Tj = 25 °C and 150 °C; VDS > ID × RDSon
0
-60
60
120
Tj (°C)
180
R DSon
a = ----------------------------R DSon ( 25 °C )
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
PH1875L_1
Product data sheet
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
6 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
03aa33
2.5
VGS(th)
(V)
2
1.5
03aa36
10-1
ID
(A)
max
10-2
typ
10-3
min
max
10-4
min
1
typ
10-5
0.5
0
-60
10-6
0
60
120
Tj (°C)
180
0
1
2
VGS (V)
3
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
003aab057
5
VGS
(V)
4
VDS
ID
3
VGS(pl)
2
VGS(th)
VGS
1
QGS1
QGS2
QGS
0
0
10
20
30
QG (nC)
40
QGD
QG(tot)
003aaa508
ID = 25 A; VDS = 60 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
PH1875L_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
7 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
003aab058
40
IS
(A)
003aab059
104
C
(pF)
30
Ciss
103
20
150 °C
10
Coss
Tj = 25 °C
Crss
0
0.2
0.4
0.6
0.8
VSD (V)
1
Tj = 25 °C and 150 °C; VGS = 0 V
102
10-1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PH1875L_1
Product data sheet
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
8 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface mounted package (LFPAK); 4 leads
A2
A
E
SOT669
C
c2
b2
E1
b3
L1
mounting
base
b4
D1
D
H
L2
1
2
3
e
4
w M A
b
X
c
1/2 e
A
(A 3)
A1
C
θ
L
detail X
y C
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
A1
A2
A3
b
b2
1.20 0.15 1.10
0.50 4.41
0.25
1.01 0.00 0.95
0.35 3.62
b3
b4
2.2
2.0
0.9
0.7
c
D (1)
c2
D1(1)
E(1) E1(1)
max
0.25 0.30 4.10
4.20
0.19 0.24 3.80
5.0
4.8
3.3
3.1
e
H
L
L1
L2
w
y
θ
1.27
6.2
5.8
0.85
0.40
1.3
0.8
1.3
0.8
0.25
0.1
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT669
REFERENCES
IEC
JEDEC
JEITA
MO-235
EUROPEAN
PROJECTION
ISSUE DATE
03-09-15
04-10-13
Fig 15. Package outline SOT669 (LFPAK)
PH1875L_1
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
9 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 6:
Revision history
Document ID
Release date
Data sheet status
Change notice Doc. number
Supersedes
PH1875L_1
20051129
Product data sheet
-
-
PH1875L_1
Product data sheet
-
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 01 — 29 November 2005
10 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
9. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
PH1875L_1
Product data sheet
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Rev. 01 — 29 November 2005
11 of 12
PH1875L
Philips Semiconductors
N-channel TrenchMOS logic level FET
14. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
11
12
13
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information . . . . . . . . . . . . . . . . . . . . 11
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 29 November 2005
Document number: PH1875L_1
Published in The Netherlands