DP AK BUK9215-55A N-channel TrenchMOS logic level FET 7 April 2014 Product data sheet 1. General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 2. Features and benefits • • • • AEC Q101 compliant Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources Suitable for thermally demanding environments due to 175 °C rating 3. Applications • • • 12 V and 24 V loads Automotive and general purpose power switching Motors, lamps and solenoids 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 55 V ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2; Fig. 3 - - 62 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 115 W VGS = 10 V; ID = 25 A; Tj = 25 °C - 11 13.6 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C - - 16.6 mΩ VGS = 5 V; ID = 25 A; Tj = 25 °C; - 13 15 mΩ - 20 - nC [1] Static characteristics RDSon drain-source on-state resistance Fig. 11; Fig. 12 Dynamic characteristics QGD gate-drain charge VGS = 5 V; ID = 25 A; VDS = 44 V; Tj = 25 °C; Fig. 9 Scan or click this QR code to view the latest information for this product BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit ID = 62 A; Vsup ≤ 55 V; RGS = 50 Ω; - - 211 mJ Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy [1] VGS = 5 V; Tj(init) = 25 °C; unclamped Current is limited by power dissipation chip rating. 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb G mbb076 2 1 S 3 DPAK (SOT428) 6. Ordering information Table 3. Ordering information Type number BUK9215-55A BUK9215-55A Product data sheet Package Name Description Version DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 2 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ - 55 V VGS gate-source voltage -15 15 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 115 W ID drain current Tmb = 25 °C; VGS = 5 V; Fig. 2; Fig. 3 [1] - 62 A [2] - 55 A [1] - 44 A - 248 A Tmb = 100 °C; VGS = 5 V; Fig. 2 IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C [2] - 55 A [1] - 62 A pulsed; tp ≤ 10 µs; Tmb = 25 °C - 248 A ID = 62 A; Vsup ≤ 55 V; RGS = 50 Ω; - 211 mJ Source-drain diode IS ISM source current Tmb = 25 °C peak source current Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] BUK9215-55A Product data sheet VGS = 5 V; Tj(init) = 25 °C; unclamped Current is limited by power dissipation chip rating. Continious current is limited by bond wires. All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 3 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03aa16 120 03nf79 80 ID (A) Pder (%) Capped at 55 A due to limitation of bondwires 60 80 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 Fig. 2. Normalized total power dissipation as a function of mounting base temperature 25 50 75 100 125 150 175 200 Tmb (°C) Continuous drain current as a function of mounting base temperature 03nf78 103 ID (A) tp = 10 µs RDSon = VDS / ID 102 100 µs P 10 δ= tp T 1 ms DC 10 ms tp 1 Fig. 3. 1 100 ms t T 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 4 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 8. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 4 - - 1.3 K/W Rth(j-a) thermal resistance from junction to ambient - 71.4 - K/W 03nf77 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10- 1 0.05 0.02 10- 2 P δ= Single Shot tp 10- 3 Fig. 4. tp T 10- 6 10- 5 10- 4 10- 3 10- 2 t T 10- 1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 5 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 9. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 50 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.3 V 0.5 - - V 1 1.5 2 V VDS = 55 V; VGS = 0 V; Tj = 25 °C - 0.05 10 µA VDS = 55 V; VGS = 0 V; Tj = 175 °C - - 500 µA VGS = 10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C - 11 13.6 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C - - 16.6 mΩ VGS = 5 V; ID = 25 A; Tj = 175 °C; - - 30 mΩ - 13 15 mΩ Static characteristics V(BR)DSS VGS(th) Fig. 10 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 10 ID = 1 mA; VDS = VGS; Tj = 25 °C; Fig. 10 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 11; Fig. 12 VGS = 5 V; ID = 25 A; Tj = 25 °C; Fig. 11; Fig. 12 Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS = 44 V; VGS = 5 V; - 48 - nC QGS gate-source charge Tj = 25 °C; Fig. 9 - 6 - nC QGD gate-drain charge - 20 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 2190 2916 pF Coss output capacitance Tj = 25 °C; Fig. 13 - 380 450 pF Crss reverse transfer capacitance - 250 344 pF td(on) turn-on delay time VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; - 19 - ns tr rise time RG(ext) = 10 Ω; Tj = 25 °C - 161 - ns td(off) turn-off delay time - 138 - ns tf fall time - 165 - ns LD internal drain inductance - 2.5 - nH BUK9215-55A Product data sheet measured from drain to centre of die All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 6 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET Symbol Parameter Conditions Min Typ Max Unit LS internal source inductance measured from source lead to source bond pad - 7.5 - nH Source-drain diode VSD source-drain voltage IS = 20 A; VGS = 0 V; Tj = 25 °C; Fig. 14 - 0.85 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; - 51 - ns recovered charge VGS = -10 V; VDS = 30 V; Tj = 25 °C - 102 - nC Qr ID (A) 03nb61 300 VGS (V) = 10 9 250 8 17 7 200 16 6 5 150 15 14 13 100 3 12 50 11 2.2 0 Fig. 5. 03nf85 19 RDSon (mΩ) 18 0 2 4 6 8 VDS (V) 10 10 Output characteristics: drain current as a Fig. 6. function of drain-source voltage; typical values 03aa35 10- 1 ID (A) min 10- 2 typ 3 6 9 12 VGS (V) 15 Drain-source on-state resistance as a function of gate-source voltage; typical values 03nb58 60 gfs (S) max 40 10- 3 10- 4 20 10- 5 10- 6 Fig. 7. 0 2 4 VGS (V) 0 6 Sub-threshold drain current as a function of gate-source voltage BUK9215-55A Product data sheet Fig. 8. 0 20 60 80 ID (A) 100 Forward transconductance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 7 April 2014 40 © NXP Semiconductors N.V. 2014. All rights reserved 7 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nb57 5 VGS (V) VDD = 14 V VGS(th) (V) VDD = 44 V 4 03aa33 2.5 2 max 3 1.5 typ 2 1 min 1 0.5 0 Fig. 9. 0 20 40 0 -60 60 QG (nC) Gate-source voltage as a function of turn-on gate charge; typical values Tj (° C) 180 03ne89 a 3.6 1.5 4.0 18 120 2 VGS (V) = 3.4 20 60 Fig. 10. Gate-source threshold voltage as a function of junction temperature 03nb62 22 RDSon (mΩ) 0 4.2 16 1 4.6 5.0 14 0.5 12 10 20 40 60 80 ID (A) 0 -60 100 Fig. 11. Drain-source on-state resistance as a function of drain current; typical values BUK9215-55A Product data sheet 0 60 120 Tj (°C) 180 Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 8 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 03nb63 6000 C Ciss (pF) 5000 4000 03nb56 100 IS (A) 80 Coss Tj = 175 °C 60 Tj = 25 °C 3000 Crss 40 2000 20 1000 0 10- 2 10- 1 1 10 VDS (V) 0 102 0.0 0.5 1.0 VSD (V) 1.5 Fig. 13. Input, output and reverse transfer capacitances Fig. 14. Reverse diode current; typical value as a function of drain-source voltage; typical values BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 9 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 10. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 E1 mounting base D2 D1 HD 2 L2 L 1 L1 3 b1 b w M c A e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D1 D2 min E E1 min e e1 HD L L1 min L2 w y max mm 2.38 2.22 0.93 0.46 0.89 0.71 1.1 0.9 5.46 5.00 0.56 0.20 6.22 5.98 4.0 6.73 6.47 4.45 2.285 4.57 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig. 15. Package outline DPAK (SOT428) BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 10 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 11. Legal information 11.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Document status [1][2] Product status [3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Definition Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 11.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. BUK9215-55A Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 11 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, ICODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 12 / 13 BUK9215-55A NXP Semiconductors N-channel TrenchMOS logic level FET 12. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Limiting values .......................................................3 8 Thermal characteristics .........................................5 9 Characteristics ....................................................... 6 10 Package outline ................................................... 10 11 11.1 11.2 11.3 11.4 Legal information .................................................11 Data sheet status ............................................... 11 Definitions ...........................................................11 Disclaimers .........................................................11 Trademarks ........................................................ 12 © NXP Semiconductors N.V. 2014. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 April 2014 BUK9215-55A Product data sheet All information provided in this document is subject to legal disclaimers. 7 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved 13 / 13