dm00069958

AN4200
Application note
Four-layer demonstration board based on the STA333IS
Introduction
The STEVAL-CCA053V1 is a four-layer demonstration board designed for the evaluation of
the STA333IS two-channel, high-efficiency Sound Terminal® device.
The purpose of this application note is to show:
 how to connect the STA333IS demonstration board
 the performance of the STA333IS device
 how to avoid critical board and layout issues
All the results and characterization data included in this application note have been
measured using Audio Precision equipment. Reference documents consist of the STA333IS
datasheet, schematic diagrams and PCB layout.
Figure 1. STEVAL-CCA053V1
July 2013
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www.st.com
Contents
AN4200
Contents
1
2
Test conditions and connections of demonstration board . . . . . . . . . . 4
1.1
Power supply signal and interface connection . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
Required equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4
Board connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Schematic diagram and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
APWorkbench settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Thermal test - VCC = 12.5 V, 1 kHz, load= 8 W (stereo) . . . . . . . . . . . . . 14
6
7
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5.1
Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2
Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Design guidelines for schematic and PCB layout . . . . . . . . . . . . . . . . 15
6.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.3
Snubber network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.4
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4.1
Snubber layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4.2
VCC traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4.3
Ground plane and heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4.4
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4.5
VCC filter for high frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
STEVAL-CCA053V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Demonstration board (four-layer) - connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Schematic diagram - part 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Schematic diagram - part 2 (connectors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
STA333IS demonstration board - four-layer PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
APWorkbench - device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
APWorkbench - control panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
THD+N vs. power - VCC = 12.5 V, load = 8 W, 1 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
THD+N vs. frequency - VCC = 12.5 V, load = 8 W, Pout = 1 W at 1 kHz . . . . . . . . . . . . . . 10
Frequency response - VCC = 12.5 V, load = 8 W, Pout = 1 W at 1 kHz . . . . . . . . . . . . . . . 11
Crosstalk - VCC = 12.5 V, load = 8 W, Pout = 1 W at 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . 11
FFT - VCC = 12.5 V, load = 8 W, Pout = 1 W at 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output power vs. supply voltage - load = 8 W, 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Efficiency - VCC = 12.5 V, 1 kHz, load = 8 W (stereo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal analysis - VCC = 12.5 V - 2 x 10 W at 1 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Snubber network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCB layout recommendations - star routing VCC traces. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCB layout recommendation - large ground plane on the top side . . . . . . . . . . . . . . . . . . 17
PCB layout recommendation - large ground plane on the inner layer 2 . . . . . . . . . . . . . . . 17
PCB layout recommendation - large ground plane on the inner layer 3 . . . . . . . . . . . . . . . 17
PCB layout recommendation - large ground plane on the bottom side . . . . . . . . . . . . . . . 17
Output filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VCC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Test conditions and connections of demonstration board
AN4200
1
Test conditions and connections of demonstration
board
1.1
Power supply signal and interface connection
1.2
1.
Connect the power supply to the +VCC and GND terminal blocks (J2)
2.
Connect the STEVAL-CCA053V1 interface board to the J4 connector
3.
Connect the S/PDIF signal cable to the RCA jack on the STEVAL-CCA035V1 board.
The signal source should be the Audio Precision equipment or a DVD player.
4.
Adjust the voltage level of the power supply. The voltage range of the DC power supply
is 4.5 V to 18 V.
5.
Connect the load to the connectors J1 and J3
Output configuration
The STA333IS demonstration board can be only configured for 2.0 channels and BTL
outputs.
1.3
Required equipment


4/20
Audio Precision (System 2700)
–
Audio Analyzer: Mod. SYS2722 -192K
–
Class-D filter: AUX-0025 filter
–
Multifunction module: DCX-127
DC power supply (4.5 V to 18 V)
–
Lambda Genesys Gen 80-19
–
HP 6038A

Digital oscilloscope: Tektronix TDS5054B

Digital multimeter: AGILENT Mod. 34410A

PC with APWorkbench control software installed
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1.4
Test conditions and connections of demonstration board
Board connections
Figure 2. Demonstration board (four-layer) - connectors
J2
DC supply
J1
OUT1
J3
OUT2
J4
Connect to STEVAL-CCA035V board
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Schematic diagram and PCB layout
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2
Schematic diagram and PCB layout
2.1
Schematic
Figure 3. Schematic diagram - part 1
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Schematic diagram and PCB layout
Figure 4. Schematic diagram - part 2 (connectors)
2.2
PCB layout
Figure 5. STEVAL-CCA053V1 board - four-layer PCB
Note:
Please refer to Figure 18 through Figure 21 on page 17 for the top, inner layer 2, inner layer
3, and bottom views, respectively.
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Schematic diagram and PCB layout
2.3
AN4200
Bill of material
Table 1. Bill of material
No.
Type
Footprint
1
Connector
Through-hole
2P pitch: 5 mm connector
terminal
3
J1, J2, J3
Any source
2
Header
Through-hole
16P (8 x 2 row) 2.5 mm
header
1
J4
Any source
3
CCAP
CAP0603
50 Volt NPO 330 pF 10%
2
C12, C13
Murata
4
CCAP
CAP0603
50 Volt 1nF 10%
6
C1, C2, C3, C4, C5, C6
Murata
5
CCAP
CAP0603
50 Volt 100 nF 10%
6
C20, C21, C22, C23,
C24, C27
Murata
6
CCAP
CAP1206
50 Volt 1U 10%
2
C16, C17
Murata
7
ECAP
CAP1206
10 µF / 16 V
5
C7, C8, C10, C11, C30
8
RES
R1206
6R2, 5% 1/8W
4
R1, R2, R5, R6
Murata
9
RES
R1206
20 5% 1/8W
2
R3, R4
Murata
10
RES
R0603
2R2 5% 1/16W
1
R7
Murata
11
RES
R0603
NS
2
R8, R12
12 Plastic rod
Hexagonal rod 15 mm length,
male type
4
Four corners
Any source
13 Plastic rod
Hexagonal rod 8 mm length,
female type
4
Four corners
Any source
1
IC1
DPM02, MARUWA
2
L5, L6
STA333IS 4-layer 1V0
1
14
IC
15
Coil
16
PCB
8/20
Description
CSP 5x6 array STA333IS
SMD
Qty
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Reference
Manufacturer
Samsung
STMicroelectronics
Maruwa
Fastprint
AN4200
3
APWorkbench settings
APWorkbench settings
Figure 6. APWorkbench - device selection
Device selection
Sound
Terminal
Amplifiers
Interface selection
Figure 7. APWorkbench - control panel
Gain Control
Volume Control
Bridge enable button
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Test results
4
AN4200
Test results
Figure 8. THD+N vs. power - VCC = 12.5 V, load = 8 , 1 kHz
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m
2m
5m
10m
20m
50m
100m
200m
500m
1
2
5
10
20
W
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
3
Red
Blue
Solid
Solid
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Ch1; Vcc= 12.5V, 1kHz, 8ohm
Ch2; Vcc= 12.5V, 1kHz, 8ohm
Figure 9. THD+N vs. frequency - VCC = 12.5 V, load = 8 , Pout = 1 W at 1 kHz
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
10/20
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Anlr.THD+N Ratio
Anlr.THD+N Ratio
Left
Left
Ch1; Vcc= 12.5V, 1W@1kHz, 8ohm
Ch2; Vcc= 12.5V, 1W@1kHz, 8ohm
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Test results
Figure 10. Frequency response - VCC = 12.5 V, load = 8 , Pout = 1 W at 1 kHz
+3
+3
+2.5
+2.5
+2
+2
+1.5
+1.5
+1
+1
d
B
r
+0.5
+0
+0.5
+0
d
B
r
A
-0.5
-0.5
B
-1
-1
-1.5
-1.5
-2
-2
-2.5
-2.5
-3
20
50
100
200
500
1k
2k
5k
10k
20k
-3
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Anlr.Level A
Anlr.Level B
Left
Right
Ch1; Vcc= 12.5V, 1kHz, 8ohm
Ch1; Vcc= 12.5V, 1kHz, 8ohm
Figure 11. Crosstalk - VCC = 12.5 V, load = 8 , Pout = 1 W at 1 kHz
+0
T T T
T
T
TT
TT
TT T
-20
-40
-60
-80
d
B
-100
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Anlr.Crosstalk
Anlr.Crosstalk
Left
Left
Ch2 =off; Vcc=12.5V, Ref:0dB@1W@1kHz, 8ohm
Ch1 =off; Vcc=12.5V, Ref:0dB@1W@1kHz, 8ohm
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Test results
AN4200
Figure 12. FFT - VCC = 12.5 V, load = 8 , Pout = 1 W at 1 kHz
+0
-20
-40
-60
d
B
r
A
-80
-100
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
2
Red
Blue
Solid
Solid
2
2
Fft.Ch.1 Ampl
Fft.Ch.2 Ampl
Left
Left
Ch1; Vcc=12.5V; 1W@1kHz;
Ch2; Vcc=12.5V; 1W@1kHz;
Figure 13. Output power vs. supply voltage - load = 8 , 1 kHz
30
28
26
24
22
20
18
16
W
14
12
10
8
6
4
2
0
+4
+6
+8
+10
+12
+14
+16
+18
+20
Vdc
12/20
Sweep
Trace
Color
Line Style
Thick
Data
Axis
Comment
1
1
1
3
Red
Blue
Solid
Solid
2
2
Anlr.Level A
Anlr.Level B
Left
Left
Ch1; Undistorted Output; (1kHz - Gain=0dB)
Ch2; THD˜10%; (1kHz - Gain=+3dB)
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Test results
Figure 14. Efficiency - VCC = 12.5 V, 1 kHz, load = 8  (stereo)
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Thermal test - VCC = 12.5 V, 1 kHz, load= 8 W (stereo)
AN4200
5
Thermal test - VCC = 12.5 V, 1 kHz, load= 8  (stereo)
5.1
Test conditions
VCC =12.5 VDC
Load= 8  (resistive dummy load)
Gain= +3 dB (both L&R channels)
All channels ON
AP filter= 22 Hz ÷ 22 kHz
Output power: 2 x 10 W (adj. using post-scale)
Tamb = 31 °C
5.2
Test results
Tmax = 88.6 °C
Tamb = 31 °C
T = 57.6 °C
Figure 15. Thermal analysis - VCC = 12.5 V - 2 x 10 W at 1 kHz
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Design guidelines for schematic and PCB layout
6
Design guidelines for schematic and PCB layout
6.1
General
6.2

Absolute maximum rating: 20 V

Bypass capacitor 100 nF in parallel to 1 µF and 10 µF for each power VCC branch.
Preferable dielectric is X7R.

Vdd and ground for the digital section should be separated from the other power
supply.

Coil saturation current compatible with the peak current of the application
Decoupling capacitors
The decoupling capacitors can be shared for each VCC branch. The decoupling capacitors
must be placed as close as possible to the IC pins.
The capacitor and the decoupling capacitor must be on the same layer as well as the track
used to connect the capacitors and the positive VCC device pins.
6.3
Snubber network
The snubber circuit must be optimized for the specific application. Starting values are
330 pF in series to 22 .
The power dissipation in this network can be defined by the following formula which
considers the power supply, frequency and capacitor value:
P = C · FreqPWM · (2 · VOUT)2
This power is dissipated on the series resistance.
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Design guidelines for schematic and PCB layout
6.4
PCB layout
6.4.1
Snubber layout
AN4200
Solder the snubber network as close as possible to the related IC pin.
Figure 16. Snubber network
Snubber network
6.4.2
VCC traces
Design the PCB tracks to implement a star routing for the VCC traces.
Figure 17. PCB layout recommendations - star routing VCC traces
Star Routing for VCC traces
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6.4.3
Design guidelines for schematic and PCB layout
Ground plane and heatsink
To dissipate the power not delivered to the loads, a large ground plane should be
implemented. This solution allows removing the heat from the device without adding an
external heatsink.
Note:
It is mandatory to have a large ground plane on the top layer, inner layer 2, inner layer 3,
and the bottom layer and solder the slug on the PCB.
Figure 18. PCB layout recommendation - large
ground plane on the top side
Figure 19. PCB layout recommendation - large
ground plane on the inner layer 2
Figure 20. PCB layout recommendation - large
ground plane on the inner layer 3
Figure 21. PCB layout recommendation - large
ground plane on the bottom side
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Design guidelines for schematic and PCB layout
6.4.4
AN4200
Output filter
It is recommended to design the PCB using symmetrical paths and tracks.
Figure 22. Output filter
Output of symmetrical paths
6.4.5
VCC filter for high frequency
The VCC filter capacitors must be placed as close as possible to the supply pins. The
ceramic capacitors must be positioned on the same layer of the device (in this
demonstration board, on the top layer of the PCB) and the distance from the IC must be
short and compatible with the minimum SMB mounting limitation.
Figure 23. VCC filter
The PWM frequency is 384 kHz (with Fs = 48 kHz) with very fast transition time. In order to
compensate the inductive effect of the copper track, the ceramic capacitors must be placed
as close as possible to the supply pins. The recommended distance between the capacitors
and the supply pins is less than 5 mm.
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Revision history
Revision history
Table 2. Document revision history
Date
Revision
01-Jul-2013
1
Changes
Initial release.
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