PSMN165-200K N-channel TrenchMOS SiliconMAX standard level FET Rev. 02 — 3 December 2009 Product data sheet 1. Product profile 1.1 General description SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 1.3 Applications Computer motherboards Switched-mode power supplies DC-to-DC convertors 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 200 V ID drain current Tsp = 80 °C; see Figure 1 and 3 - - 2.9 A Ptot total power dissipation Tsp = 80 °C; see Figure 2 - - 3.5 W VGS = 10 V; ID = 3 A; VDS = 100 V; Tj = 25 °C; see Figure 11 - 12 16.5 nC VGS = 10 V; ID = 2.5 A; Tj = 25 °C; see Figure 9 and 10 - 130 165 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 2 S source 3 S source 4 G gate 5 D drain 6 D drain 7 D drain 8 D drain Simplified outline 8 Graphic symbol D 5 G 1 mbb076 4 S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Type number PSMN165-200K Package Name Description Version SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 200 V VGS gate-source voltage -20 20 V ID drain current Tsp = 80 °C; see Figure 1 and 3 - 2.9 A IDM peak drain current Tsp = 25 °C; tp ≤ 10 µs; pulsed - 20 A Ptot total power dissipation Tsp = 80 °C; see Figure 2 - 3.5 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp = 80 °C - 3.1 A ISM peak source current Tsp = 25 °C; tp ≤ 10 µs; pulsed - 20 A PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 2 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 03aa25 120 03aa17 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 0 50 100 150 Tsp (°C) Fig 1. 200 Tsp (°C) Normalized continuous drain current as a function of solder point temperature Fig 2. Normalized total power dissipation as a function of solder point temperature 03ae06 102 RDSon = VDS/ID ID (A) 10 tp = 10 µs 100 µs 1 ms 1 10 ms δ= P tp D.C. T 100 ms 10−1 t tp T 10−2 1 10 102 103 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 3 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from mounted on a metal clad substrate; junction to solder point see Figure 4 Min Typ Max Unit - - 20 K/W 03ae05 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 1 0.1 0.05 0.02 δ= P 10−1 tp T single pulse t tp 10−2 10−4 T 10−3 10−2 10−1 1 102 10 tp (s) Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 4 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 200 240 - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS= VGS; Tj = 150 °C; see Figure 8 1.2 - - V ID = 1 mA; VDS= VGS; Tj = -55 °C; see Figure 8 - - 6 V ID = 1 mA; VDS= VGS; Tj = 25 °C; see Figure 8 2 - 4 V IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 160 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 200 V; VGS = 0 V; Tj = 150 °C - - 0.5 mA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 2.5 A; Tj = 150 °C; see Figure 9 and 10 - 325 413 mΩ VGS = 10 V; ID = 2.5 A; Tj = 25 °C; see Figure 9 and 10 - 130 165 mΩ ID = 3 A; VDS = 100 V; VGS = 10 V; Tj = 25 °C; see Figure 11 - 40 - nC - 4.5 - nC - 12 16.5 nC Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 12 - 1330 - pF - 140 - pF - 70 - pF - 12 25 ns - 11 25 ns turn-off delay time - 50 80 ns tf fall time - 25 40 ns gfs transfer conductance VDS = 15 V; ID = 2.9 A; Tj = 25 °C; see Figure 13 - 10 - S VDS = 100 V; RL = 100 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 2.3 A; VGS = 0 V; Tj = 25 °C; see Figure 14 - 0.7 1.1 V trr reverse recovery time - 105 - ns Qr recovered charge IS = 2.9 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 0.45 - µC PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 5 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 03ae07 20 VGS = 10 V ID 03ae09 20 5V VDS > I D X R DSon ID (A) (A) 15 15 4.5 V 10 10 5 5 Tj = 150 °C 4V 3.5 V 0 0 1 2 3 4 0 5 0 1 2 25 °C 3 4 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. 03aa35 10−1 ID (A) Transfer characteristics: drain current as a function of gate-source voltage; typical values 03aa32 5 VGS(th) (V) min 10−2 typ max 4 10−3 3 10−4 2 10−5 1 10−6 0 2 4 0 −60 6 VGS (V) Fig 7. 5 VGS(V) VDS (V) Sub-threshold drain current as a function of gate-source voltage Fig 8. typ min 0 60 120 180 Tj (°C) Gate-source threshold voltage as a function of junction temperature PSMN165-200K_2 Product data sheet max © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 6 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 03ae08 0.3 VGS = 4 V R DSon 03aa31 3 Tj = 25 °C 4.5 V a (Ω) 0.25 2 0.2 5V 10 V 1 0.15 0.1 0 Fig 9. 5 10 15 ID (A) 20 Drain-source on-state resistance as a function of drain current; typical values 03ae13 10 ID = 3 A VGS (V) 0 -60 0 60 120 Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 03ae12 104 Ciss , Coss , Crss (pF) Tj = 25 °C 8 VDD = 40 V 100 V 160 V Ciss 103 6 4 Coss 102 Crss 2 0 0 15 30 QG (nC) 45 Fig 11. Gate-source voltage as a function of gate charge; typical values 10 10−1 10 VDS (V) 102 Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN165-200K_2 Product data sheet 1 © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 7 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 03ae10 30 gfs (S) 25 VDS > I D X R DSon 03ae11 20 VGS = 0 V IS (A) Tj = 25 °C 15 20 150 °C 10 15 10 5 Tj = 150 °C 25 °C 5 0 0 5 10 15 20 0 0 Fig 13. Forward transconductance as a function of drain current; typical values 0.4 0.6 0.8 1 Fig 14. Source current as a function of source-drain voltage; typical values PSMN165-200K_2 Product data sheet 0.2 VSD (V) ID (A) © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 8 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 inches 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 15. Package outline SOT96-1 (SO8) PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 9 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN165-200K_2 20091203 Product data sheet - PSMN165-200K-01 Modifications: PSMN165-200K-01 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20010116 Product specification - PSMN165-200K_2 Product data sheet - © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 10 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Draft— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS— is a trademark of NXP B.V. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PSMN165-200K_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 December 2009 11 of 12 PSMN165-200K NXP Semiconductors N-channel TrenchMOS SiliconMAX standard level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 December 2009 Document identifier: PSMN165-200K_2