LAMINATE Data Sheet FCBGA Technology Options Flip Chip BGA Packages (FCBGA) J-Devices FCBGA package offers a better solution for high performance applications. “Flip Chip” describes a method of electrically connecting the die to the package carrier through a conductive bump. Benefits for this technology include: reduced signal inductance due to the shorter die to package connection; reduced power/ground inductance as power can routed directly into die core; higher signal density by utilizing the total die surface vs. only edge pads on wire bonded design. For higher I/O products limited by bond pad design, this packaging technology can enable smaller die design. Package X & Y footprint is reduced since there is no need for bond wire routing; and a thinner package is possible since the mold is not needed to protect the wires. High thermal conductive material is used for the thermal interface material between die back side and lid, resulting in excellent thermal performance. Applications • Games, networking, PC and TV applications • High speed, high pin count, high density applications with better heat dissipation • Substrates – 4-19 layer laminate build up substrates – High CTE ceramic – Coreless • Bump types – Eutectic Sn/Pb – High Pb – Pb free – Cu pillar (array and fine pitch peripheral) • Package formats – Bare die – Lidded Thermal Solutions The various FCBGA package options enable a package selection that fits the final product specific needs. High performance products can utilize a lidded package configuration that can be directly attached to a heat spreader. This feature produces the lowest possible thermal resistance (Theta JC) between the package and any externally applied thermal solution. Reliability Qualification • Moisture Sensitivity: Pre-condition of 30°C/60% RH, 192 hours, IR reflow 260°C 3X • THB: 85°C/85% RH, 100 hours • uHAST: 130°C/85% RH, 100 hours • Temp Cycle: -55°C/+125°C, 1000 cycles • High Temp Storage: 150°C, 1000 hours Features • • • • • • Up to 26 mm die sizes 12-47.5 mm body size 1.0-0.4 mm ball pitch 150 µm minimum array bump pitch < 100 µm minimum peripheral bump pitch Wafer node ≥ 28 nm qualified, 20 nm in development DSJD406A Rev Date: 5/15 www.j-devices.co.jp LAMINATE Data Sheet FCBGA Additional Package Options • • • • • • Cross-sectiom SMT components on top or bottom side Multi-die capability Memory components on top side Variety of lid material options Grounded lid Custom BGA footprints Bare Die Hat Type Lid Test Services • Program conversion • Product engineering • Burn-in capabilities Grounded Lid Shipping • JEDEC outline trays Package Line Up FC-PBGA Body Size (mm) 12 x 12 14 x 14 15 x 15 17 x 17 19 x 19 21 x 21 23 x 23 25 x 25 27 x 27 29 x 29 31 x 31 33 x 33 35 x 35 37.5 x 37.5 40 x 40 42.5 x 42.5 45 x 45 47.5 x 47.5 0.4 455 681 0.5 0.65 Lead Pitch & Count (mm) 0.8 1.0 1.27 460 605, 647 625 436 472, 592 484, 524, 672 560, 593, 653 815, 832, 873, 1089 830, 1225 1936 320 576, 625, 676 554, 561, 640, 729, 783 772, 896, 900 961,1020 914, 924, 1089, 1152, 1156 1296, 1369 1182, 1414, 1444 1681 1848 2116 360 360 304 784 With respect to the information in this document, J-Devices makes no guarantee or warranty of its accuracy or that the use of such information will not infringe upon the intellectual rights of third parties. J-Devices shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it and no patent or other license is implied hereby. This document does not in any way extend or modify J-Devices’ warranty on any product beyond that set forth in its standard terms and conditions of sale. J-Devices reserves the right to make changes in its product and specifications at any time and without notice. © 2015, J-Devices Corporation. All Rights Reserved. DSJD406A Rev Date: 5/15 www.j-devices.co.jp