RENESAS M5M29KE131BVP

Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
DESCRIPTION
The M5M29KE131BVP is a Stacked micro Multi Chip
Package that contents 2 Dies of 64M-bit Flash memory in a
48-pin TSOP(I) for lead free use.
128M-bit Flash memory is a 16,777,216 bytes / 8,388,608
words, single power supply and high performance nonvolatile memory fabricated by CMOS technology for the
peripheral circuit and DINOR IV (Divided bit-line NOR IV)
architecture for the memory cell. All memory blocks are
locked and can not be programmed or erased, when WP# is
Low. Using Software Lock Release function, program or
erase operation can be executed.
The M5M29KE131BVP is suitable for a high performance cellular
phone and a mobile PC that are required to be small mounting
area, weight and small power dissipation.
FEATURES
Access time
Random
Page
Supply voltage
Ta=-40 ~ 85 °C
Ambient temperature
Package
70ns (Max.)
25ns(Max.)
VCC= 3.0 ~ 3.6V
48pin TSOP(Type-I), Lead pitch 0.5mm
Outer-lead finishing : Sn-Cu
APPLICATION
Digital Cellar Phone, Telecommunication,
PDA, Car Navigation System, Video Game Machine
12.0 mm
PIN CONFIGURATION (TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RP#
A21
WP#
A22#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
M5M29KE131BVP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
Outline
48P3R-C
20.0 mm
VCC
GND
A0-A22
DQ0-DQ15
CE#
OE#
1
: VCC
: GND
: Address
: Data I/O
: Chip enable
: Output enable
WE#
WP#
RP#
BYTE#
: Write enable
: Write protect
: Reset power down
: Byte enable
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
MCP Block Diagram
Vcc
GND
A0 to A22
CE#
WP#
RP#
WE#
OE#
BYTE#
64Mbit DINOR IV
Flash Memory
DQ0 to DQ15
64Mbit DINOR IV
Flash Memory
Capacitance
Symbol
Parameter
Input
A22-A0, OE#, WE#, CE#, WP#,
capacitance RP#,BYTE#
Output
COUT
DQ15-DQ0
Capacitance
CIN
2
Conditions
Ta=25°C, f=1MHz,
Vin=Vout=0V
Min.
Limits
Typ.
Max.
Unit
24
pF
24
pF
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Flash Memory Part
Description
- Auto Erase
The 128M-bit DINOR IV(Divided bit line NOR IV) Flash
Memory is 3.3V-only high speed 134,217,728-bit CMOS
boot block Flash Memory. Alternating BGO(Back Ground
Operation) feature of the device allows Program or Erase
operations to be performed in one bank while the device
simultaneously allows Read operations to be performed
on the other bank in each 64M-bit area which is selected
by A22=L or H. This BGO feature is suitable for
communication products and cellular phone.The Flash
Memory is fabricated by CMOS technology for the
peripheral circuits and DINOR IV architecture for the
memory cells.
Erase time
150ms(typ.)
Erase unit
Bank(I) ,Bank(VIII)
Boot Block
4K-word /8K-byte x 2
Parameter Block 4K-word /8K-byte x 6
Main Block
32K-word /64K-byte x 7
Bank(II) ,Bank(VII)
Main Block
32K-word /64K-byte 8
Bank(III) ,Bank(VI)
Main Block
32K-word /64K-byte x 56
Bank(IV) ,Bank(V)
Main Block
- Program/Erase cycles
Features
- Organization
8,388,608-word x 16-bit
16,777,216-word x 8-bit
- Supply Voltage
VCC = 3.0 ~ 3.6V
- Access time
Random Access
70ns(Max.)
Random Page Read
25ns(Max.)
- Read
108mW (Max. at 5MHz)
- Page Read
36mW (Max.)
(After Automatic Power Down)
- Program/Erase
0.66µW(typ.)
126mW(Max.)
Standby
0.66µW(typ.)
Deep Power Down mode
0.66µW(typ.)
- Auto Program for Bank(I) – Bank(IV)
Program Time
Word Program
30µs/1word(typ.)
Byte Program
30µs/1byte(typ.)
Page Program
4ms(typ.)
32K-word /64K-byte x 56
100Kcycles
- Dual Boot Block Architecture
There are Bottom and Top boot blocks in both sides.
Bottom Boot
(A22=VIL )
Top Boot
(A22=VIH)
- The Other Functions
Software Command Control
Quick Data Reclaim
Software Lock Release(while WP# is low)
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Among Bank (I)-Bank(IV)
in Bottom 64Mbit area (A22=VIL),
Among Bank (V)-Bank(VIII)
in Top 64Mbit area (A22=VIH)
Random Page Read
Program Unit
3
Word Program
1 word
Byte Program
1 byte
Page Program
128 words/256 bytes
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
A21
A20
A19
A18
A17
A16
A15
X-Decoder
A14
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Bank(VIII)
15blocks
Bank(VII)
8blocks
Bank(VI)
56blocks
Bank(V)
56blocks
A13
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
A12
A11
Address
A10
Input
A9
A8
A7
A6
A5
A4
A3
Bank(IV)
56blocks
Bank(III)
56blocks
Bank(II)
8blocks
Bank(I)
15blocks
Y-Decoder
.
.
.
.
.
A2
A1
A0
VCC
GND
A22="H"
A22
128word Page Buffer
Boot Block T134 4Kword
Boot Block T133 4Kword
Parameter Block T132 4Kword
.
Parameter Block T127 4Kword
Main Block T126 32Kword
.
Main Block T120 32Kword
Main Block T119 32Kword
.
.
Main Block T112 32Kword
Main Block T111 32Kword
.
.
Main Block T56 32Kword
Main Block T55 32Kword
.
.
Main Block T0 32Kword
Main Block B134 32Kword
.
.
Main Block B79 32Kword
Main Block B78 32Kword
.
.
Main Block B23 32Kword
Main Block B22 32Kword
.
.
Main Block B15 32Kword
Main Block B14 32Kword
.
Main Block B8 32Kword
Parameter Block B7 4Kword
.
Parameter Block B2 4Kword
Boot Block B1 4Kword
Boot Block B0 4Kword
A22="L"
Block Diagram
(128Mbit Flash Memory)
Y-Gate / Sense Amp.
………………………………….
Status / ID Register
Chip
Enable
Multiplexer
F-CE#
Output Enable OE#
Write Enable
WE#
Write
Protect
F-WP#
Reset
/Pow erDow n
F-RP#
BYTE
Enable
………………………………….
Command
User
Interface
Write
State
Machine
I/O Buffer
……………………
BYTE#
Data I/O
DQ15
/A-1
4
DQ14
……………………
DQ1 DQ0
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Function of Flash Memory
Output Disable
The 128M-bit DINOR IV Flash Memory includes on-chip
program/erase control circuitry. The Write State Machine
(WSM) controls block erase and word/page program
operations. Operational modes are selected by the
commands written to the Command User Interface (CUI).
The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired
program or block erase operation.
When OE# is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance (High-Z) state.
A Deep Power Down mode is enabled when the RP# pin
is at GND, minimizing power consumption.
Standby
When CE# is at VIH, the device is in the standby mode
and its power consumption is reduced. Data input/output
are in a high-impedance (High-Z) state. If the memory is
deselected during block erase or program, the internal
control circuits remain active and the device consumes
normal active power until the operation completes.
Read
The 128M-bit DINOR IV Flash Memory has four read
modes, which accesses to the memory array ,the Page read,
the Device Identifier and
the Status Register.
The
appropriate read commands are required to be written to the
CUI. Upon initial device power up or after exit from deep
power down, the 128M-bit DINOR IV Flash Memory
automatically resets to read array mode. In the read array
mode and in the conditions are low level input to OE#, high
level input to WE# and RP#, low level input to CE# and
address signals to the address inputs (A22 - A0:Word Mode,
A22-A-1:Byte Mode) the data of the addressed location to
the data input/output (DQ15-DQ0:Word Mode, DQ7DQ0:Byte Mode) is output.
Write
Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register. They also enable block erase and program. The
CUI is written by bringing WE# to low level and OE# is at
high level, while CE# is at low level. Address and data are
latched on the earlier rising edge of WE# and CE#.
Standard micro processor write timings are used.
Alternating Background Operation (BGO)
Deep Power Down
When RP# is at VIL, the device is in the deep power down
mode and its power consumption is substantially low.
During read modes, the memory is deselected and the data
input/output are in a high-impedance (High-Z) state. After
return from power down, the CUI is reset to Read Array,
and the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being
altered become invalid.
Automatic Power Down (Auto-PD)
The Automatic Power Down minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or CE# isn't
changed more than 200ns after the last alternation. The
power consumption becomes the same as the stand-by
mode. During this mode, the output data is latched and can
be read out. New data is read out correctly when
addresses are changed.
BBR(Back Bank array Read)
In the 128M-bit DINOR IV Flash Memory , when one
memory address is read according to a Read Mode in the
case of the same as an access when a Read Mode
command is input, an another Bank memory data can be
read out (Read Array or Page Read) by changing an
another Bank address.
The 128M-bit DINOR IV Flash Memory allows to read array
from one bank while the other bank operates in software
command write cycling or the erasing / programming
operation in the background. Array Read operation with the
other bank in BGO is performed by changing the bank
address without any additional command. When the bank
address points the bank in software command write cycling
or the erasing / programming operation, the data is read out
from the status register. The access time with BGO is the
same as the normal read operation.
5
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Software Command Definitions
Clear Status Register Command (50H)
The device operations are selected by writing specific
software command into the Command User Interface.
The Erase Status, Program Status and Block Status bits
are set to "1"s by the Write State Machine and can only
be reset by the Clear Status Register command of 50H.
These bits indicate various failure conditions.
Read Array Command (FFH)
The device is in Read Array mode on initial device power
up and after exit from deep power down, or by writing FFH
to the Command User Interface. After starting the internal
operation the device is set to the read status register mode
automatically.
Read Device Identifier Command (90H)
We can normally read device identifier codes when Read
Device Identifier Code Command (90H) is written to the
command latch. Following the command write, the
manufacturer code and the device code can be read from
A0 address 0H and 1H in a bank address, respectively.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm
command of D0H. An address within the block to be
erased is required. The WSM executes iterative erase
pulse application and erase verify operation.
Read Status Register Command (70H)
Program Commands
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Interface.
Also, after starting the internal operation the device is set to
the Read Status Register mode automatically.
A) Word / Byte Program (40H)
The contents of Status Register are latched on the later
falling edge of OE# must be toggled every status read.
Word/Byte program is executed by a two-command
sequence. The Word/Byte program Setup command of
40H is written to the Command Interface, followed by a
second write specifying the address and data to be written.
The WSM controls the program pulse application and
verify operation.
B) Page Program for Data Blocks (41H)
Page Read Command (F3H)
The Page Read command (F3H) timing can be used by
writing the first command to CUI and F-CE# falls VIL or
changing the address(A22-A2) is necessary to start
activating page read mode. This command is fast random
4 words read. During the read it is necessary to fix F-CE#
low and change addresses that are defined by A0 and
A1(0h - 3h) at random continuously. The mode is kept until
F-RP# is set to L or this chip is powered down.
The first read of Page Read timing is the same as normal
read (ta(CE)). F-CE# should be fallen “L”. The read timing
after the first is the same as ta(PAD).
In the page read mode the upper address(A22-A2) or FCE# are supposed not to be clocked during read operation.
Otherwise the access time is as same as normal read.
6
Page Program allows fast programming of 128words
/256bytes of data. Writing of 41H initiates the page
program operation for the Data area. From 2nd cycle to
129th cycle :Word Mode, 257th cycle :Byte Mode, write
data must be serially inputted. Address A6-A0:Word
Mode, A6-A-1:Byte Mode have to be incremented from
00H to 7FH. After completion of data loading, the WSM
controls the program pulse application and verify
operation.
C) Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by
writing 74H followed by a second write specifying the
column address(A6-A0:Word Mode, A6-A-1:Byte Mode)
and data. Distinct data up to 128word/256bytes can be
loaded to the page buffer by this two-command sequence.
On the other hand, all of the loaded data to the page buffer
is programmed simultaneously by writing Page Buffer to
Flash command of 0EH followed by the confirm command
of D0H. After completion of programming the data on the
page buffer is cleared automatically.
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Flash to Page Buffer Command (F1H/D0H)
Power Supply Voltage
Array data load to the page buffer is performed by
writing the Flash to Page Buffer command of F1H
followed by the Confirm command of D0H. An address
within the page to be loaded is required. Then the array
data can be copied into the other pages within the same
bank by using the Page Buffer to Flash command.
When the power supply voltage is less than VLKO, Low
VCC Lock-Out voltage, the device is set to the Read-only
mode.
A delay time of 60µs is required before any device
operation is initiated. The delay time is measured from the
time Flash VCC reaches Flash VCCmin (3.0V).
During power up, RP# = GND is recommended. Falling in
Busy status is not recommended for possibility of
damaging the device.
Clear Page Buffer Command (55H/D0H)
Loaded data to the page buffer is cleared by writing the
Clear Page Buffer command of 55H followed by the
Confirm command of D0H. This command is valid for
clearing data loaded by Single Data Load to Page Buffer
command.
Memory Organization
Data Protection
A block is erased independently of other blocks in the
array.
The 128M-bit DINOR IV Flash Memory has a master
Write Protect pin (WP#). When WP# is at VIH, all blocks
can be programmed or erased. When WP# is low, all
blocks are in locked mode which prevents any
modifications to memory blocks. Software Lock Release
function is only command which allows to program or erase.
The 128M-bit DINOR IV Flash Memory is constructed by
2 boot blocks of 4K words, 6 parameter blocks of 4K words
and 7 main blocks of 32K words in Bank(I) and Bank(VIII),
by 8 main blocks of 32K words in Bank(II) and Bank(VII),
and by 56 main blocks of 32K words in Bank(III),
BANK(IV) , BANK(V) and Bank(VI).
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows
read out from another block of memory. Writing the
Suspend command of B0H during program operation
interrupts the program operation and allows read out from
another block of memory. The Bank address is required
when writing the Suspend/Resume Command. The device
continues to output Status Register data when read, after
the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the
erase operation or program operation has been suspended.
At this point, writing of the Read Array command to the CUI
enables reading data from blocks other than that which is
suspended. When the Resume command of D0H is written
to the CUI, the WSM will continue with the erase or
program processes.
Erase All Unlocked Blocks Command (A7H/D0H)
The command sequence enable us to erase all blocks.
The command can be used by writing Setup command
A7H(1st cycle) and confirm command D0H(2nd cycle). The
sequence is not valid in case of WP#=VIL.
7
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Block Organization
70000H77FFFH
68000H6FFFFH
60000H67FFFH
58000H5FFFFH
50000H57FFFH
48000H4FFFFH
40000H47FFFH
38000H3FFFFH
30000H37FFFH
50000H5FFFFH
40000H4FFFFH
30000H3FFFFH
20000H2FFFFH
28000H2FFFFH
20000H27FFFH
18000H1FFFFH
10000H17FFFH
10000H1FFFFH
0E000H0FFFFH
0C000H0DFFFH
0A000H0BFFFH
08000H09FFFH
08000H0FFFFH
07000H07FFFH
06000H06FFFH
05000H05FFFH
04000H04FFFH
06000H07FFFH
04000H05FFFH
02000H03FFFH
00000H01FFFH
03000H03FFFH
02000H02FFFH
01000H01FFFH
00000H00FFFH
A21-A-1
(Byte
Mode)
8
A21-A0
(Word
Mode)
32Kw ord 26
32Kw ord 25
32Kw ord 24
32Kw ord 23
32Kw ord 22
32Kw ord 21
32Kw ord 20
32Kw ord 19
32Kw ord 18
32Kw ord 17
32Kw ord 16
32Kw ord 15
32Kw ord 14
32Kw ord 13
32Kw ord 12
32Kw ord 11
32Kw ord 10
32Kw ord 9
32Kw ord 8
4Kw ord 7
4Kw ord 6
4Kw ord 5
4Kw ord 4
4Kw ord 3
4Kw ord 2
4Kw ord 1
4Kw ord 0
1C8000H1CFFFFH
1C0000H1C7FFFH
1B8000H1BFFFFH
1B0000H1B7FFFH
1A8000H1AFFFFH
340000H34FFFFH
330000H33FFFFH
320000H32FFFFH
310000H31FFFFH
1A0000H1A7FFFH
198000H19FFFFH
190000H197FFFH
188000H18FFFFH
300000H30FFFFH
2F0000H2FFFFFH
2E0000H2EFFFFH
2D0000H2DFFFFH
2C0000H2CFFFFH
2B0000H2BFFFFH
2A0000H2AFFFFH
290000H29FFFFH
280000H28FFFFH
180000H187FFFH
178000H17FFFFH
170000H177FFFH
168000H16FFFFH
160000H167FFFH
158000H15FFFFH
150000H157FFFH
148000H14FFFFH
140000H147FFFH
270000H27FFFFH
260000H26FFFFH
250000H25FFFFH
240000H24FFFFH
138000H13FFFFH
130000H137FFFH
128000H12FFFFH
120000H127FFFH
230000H23FFFFH
220000H22FFFFH
210000H21FFFFH
200000H20FFFFH
1F0000H1FFFFFH
118000H11FFFFH
110000H117FFFH
108000H10FFFFH
100000H107FFFH
F8000HFFFFFH
1E0000H1EFFFFH
1D0000H1DFFFFH
1C0000H1CFFFFH
1B0000H1BFFFFH
F0000HF7FFFH
E8000HEFFFFH
E0000HE7FFFH
D8000HDFFFFH
A21-A-1
(Byte
Mode)
A21-A0
(Word
Mode)
32Kw ord 66
32Kw ord 65
32Kw ord 64
32Kw ord 63
32Kw ord 62
32Kw ord 61
32Kw ord 60
32Kw ord 59
32Kw ord 58
32Kw ord 57
32Kw ord 56
32Kw ord 55
32Kw ord 54
32Kw ord 53
32Kw ord 52
32Kw ord 51
32Kw ord 50
32Kw ord 49
32Kw ord 48
32Kw ord 47
32Kw ord 46
32Kw ord 45
32Kw ord 44
32Kw ord 43
32Kw ord 42
32Kw ord 41
32Kw ord 40
32Kw ord 39
32Kw ord 38
32Kw ord 37
32Kw ord 36
32Kw ord 35
32Kw ord 34
x16 (Word
Mode)
2F0000H2F7FFFH
2E8000H2EFFFFH
2E0000H2E7FFFH
5B0000H5BFFFFH
5A0000H5AFFFFH
590000H59FFFFH
580000H58FFFFH
570000H57FFFFH
2D8000H2DFFFFH
2D0000H2D7FFFH
2C8000H2CFFFFH
2C0000H2C7FFFH
2B8000H2BFFFFH
560000H56FFFFH
550000H55FFFFH
540000H54FFFFH
530000H53FFFFH
2B0000H2B7FFFH
2A8000H2AFFFFH
2A0000H2A7FFFH
298000H29FFFFH
520000H52FFFFH
510000H51FFFFH
500000H50FFFFH
4F0000H4FFFFFH
4E0000H4EFFFFH
4D0000H4DFFFFH
4C0000H4CFFFFH
4B0000H4BFFFFH
4A0000H4AFFFFH
290000H297FFFH
288000H28FFFFH
280000H287FFFH
278000H27FFFFH
270000H277FFFH
268000H26FFFFH
260000H267FFFH
258000H25FFFFH
250000H257FFFH
490000H49FFFFH
480000H48FFFFH
470000H47FFFFH
460000H46FFFFH
248000H24FFFFH
240000H247FFFH
238000H23FFFFH
230000H237FFFH
450000H45FFFFH
440000H44FFFFH
430000H43FFFFH
420000H42FFFFH
410000H41FFFFH
228000H22FFFFH
220000H227FFFH
218000H21FFFFH
210000H217FFFH
208000H20FFFFH
400000H40FFFFH
3F0000H3FFFFFH
3E0000H3EFFFFH
3D0000H3DFFFFH
200000H207FFFH
1F8000H1FFFFFH
1F0000H1F7FFFH
1E8000H1EFFFFH
A21-A-1
(Byte
Mode)
A21-A0
(Word
Mode)
32Kw ord 101
32Kw ord 100
32Kw ord 99
32Kw ord 98
32Kw ord 97
32Kw ord 96
32Kw ord 95
32Kw ord 94
32Kw ord 93
32Kw ord 92
32Kw ord 91
32Kw ord 90
32Kw ord 89
32Kw ord 88
32Kw ord 87
32Kw ord 86
32Kw ord 85
32Kw ord 84
32Kw ord 83
32Kw ord 82
32Kw ord 81
32Kw ord 80
32Kw ord 79
32Kw ord 78
32Kw ord 77
32Kw ord 76
32Kw ord 75
32Kw ord 74
32Kw ord 73
32Kw ord 72
32Kw ord 71
32Kw ord 70
32Kw ord 69
x8 (Byte
Mode)
7F0000H7FFFFFH
7E0000H7EFFFFH
7D0000H7DFFFFH
x16 (Word
Mode)
3F8000H3FFFFFH
3F0000H3F7FFFH3E8000H3EFFFFH
7C0000H7CFFFFH
7B0000H7BFFFFH
7A0000H7AFFFFH
790000H79FFFFH
780000H78FFFFH
3E0000H3E7FFFH3D8000H3DFFFFH
3D0000H3D7FFFH3C8000H3CFFFFH
3C0000H3C7FFFH-
770000H77FFFFH
760000H76FFFFH
750000H75FFFFH
740000H74FFFFH
3B8000H3BFFFFH
3B0000H3B7FFFH3A8000H3AFFFFH
3A0000H3A7FFFH-
730000H73FFFFH
720000H72FFFFH
710000H71FFFFH
700000H70FFFFH
6F0000H6FFFFFH
6E0000H6EFFFFH
6D0000H6DFFFFH
6C0000H6CFFFFH
6B0000H6BFFFFH
398000H39FFFFH
390000H397FFFH388000H38FFFFH
380000H387FFFH378000H37FFFFH
370000H377FFFH368000H36FFFFH
360000H367FFFH358000H35FFFFH
6A0000H6AFFFFH
690000H69FFFFH
680000H68FFFFH
670000H67FFFFH
350000H357FFFH348000H34FFFFH
340000H347FFFH338000H33FFFFH
660000H66FFFFH
650000H65FFFFH
640000H64FFFFH
630000H63FFFFH
620000H62FFFFH
330000H337FFFH328000H32FFFFH
320000H327FFFH318000H31FFFFH
310000H317FFFH-
610000H61FFFFH
600000H60FFFFH
5F0000H5FFFFFH
308000H30FFFFH
300000H307FFFH2F8000H2FFFFFH
32Kw ord 134
32Kw ord 133
32Kw ord 132
32Kw ord 131
32Kw ord 130
32Kw ord 129
32Kw ord 128
32Kw ord 127
32Kw ord 126
32Kw ord 125
32Kw ord 124
32Kw ord 123
32Kw ord 122
32Kw ord 121
32Kw ord 120
32Kw ord 119
32Kw ord 118
BANK(IV)
E0000HEFFFFH
D0000HDFFFFH
C0000HCFFFFH
B0000HBFFFFH
A0000HAFFFFH
90000H9FFFFH
80000H8FFFFH
70000H7FFFFH
60000H6FFFFH
32Kw ord 28
32Kw ord 27
390000H39FFFFH
380000H38FFFFH
370000H37FFFFH
360000H36FFFFH
350000H35FFFFH
32Kw ord 67
x8 (Byte
Mode)
5E0000H5EFFFFH
5D0000H5DFFFFH
5C0000H5CFFFFH
BANK(III)
90000H97FFFH
88000H8FFFFH
80000H87FFFH
78000H7FFFFH
32Kw ord 29
x16 (Word
Mode)
1E0000H1E7FFFH
1D8000H1DFFFFH
1D0000H1D7FFFH
BANK(IV)
120000H12FFFFH
110000H11FFFFH
100000H10FFFFH
F0000HFFFFFH
32Kw ord 31
32Kw ord 30
x8 (Byte
Mode)
3C0000H3CFFFFH
3B0000H3BFFFFH
3A0000H3AFFFFH
BANK(III)
B8000HBFFFFH
B0000HB7FFFH
A8000HAFFFFH
A0000HA7FFFH
98000H9FFFFH
32Kw ord 32
BANK(I)
170000H17FFFFH
160000H16FFFFH
150000H15FFFFH
140000H14FFFFH
130000H13FFFFH
32Kw ord 33
BANK(II)
x16 (Word
Mode)
D0000HD7FFFH
C8000HCFFFFH
C0000HC7FFFH
BANK(III)
x8 (Byte
Mode)
1A0000H1AFFFFH
190000H19FFFFH
180000H18FFFFH
128M-bit DINOR(IV) Flash Memory Map (Bottom 64Mbit / A22=VIL)
32Kw ord 117
32Kw ord 116
32Kw ord 115
32Kw ord 114
32Kw ord 113
32Kw ord 112
32Kw ord 111
32Kw ord 110
32Kw ord 109
32Kw ord 108
32Kw ord 107
32Kw ord 106
32Kw ord 105
32Kw ord 104
32Kw ord 103
32Kw ord 102
32Kw ord 68
A21-A-1
(Byte
Mode)
A21-A0
(Word
Mode)
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Block Organization
80000H87FFFH
78000H7FFFFH
70000H77FFFH
68000H6FFFFH
60000H67FFFH
58000H5FFFFH
50000H57FFFH
90000H9FFFFH
80000H8FFFFH
70000H7FFFFH
60000H6FFFFH
50000H5FFFFH
40000H4FFFFH
30000H3FFFFH
48000H4FFFFH
40000H47FFFH
38000H3FFFFH
30000H37FFFH
28000H2FFFFH
20000H27FFFH
18000H1FFFFH
20000H2FFFFH
10000H1FFFFH
00000H0FFFFH
A21-A-1
(Byte
Mode)
10000H17FFFH
08000H0FFFFH
00000H07FFFH
A21-A0
(Word
Mode)
32Kw ord 27
32Kw ord 26
32Kw ord 25
32Kw ord 24
32Kw ord 23
32Kw ord 22
32Kw ord 21
32Kw ord 20
32Kw ord 19
32Kw ord 18
32Kw ord 17
32Kw ord 16
32Kw ord 15
32Kw ord 14
32Kw ord 13
32Kw ord 12
32Kw ord 11
32Kw ord 10
32Kw ord 9
32Kw ord 8
32Kw ord 7
32Kw ord 6
32Kw ord 5
32Kw ord 4
32Kw ord 3
32Kw ord 2
32Kw ord 1
32Kw ord 0
3D0000H3DFFFFH
3C0000H3CFFFFH
3B0000H3BFFFFH
3A0000H3AFFFFH
390000H39FFFFH
380000H38FFFFH
370000H37FFFFH
1E8000H1EFFFFH
1E0000H1E7FFFH
1D8000H1DFFFFH
1D0000H1D7FFFH
1C8000H1CFFFFH
1C0000H1C7FFFH
1B8000H1BFFFFH
360000H36FFFFH
350000H35FFFFH
340000H34FFFFH
330000H33FFFFH
1B0000H1B7FFFH
1A8000H1AFFFFH
1A0000H1A7FFFH
198000H19FFFFH
320000H32FFFFH
310000H31FFFFH
300000H30FFFFH
2F0000H2FFFFFH
2E0000H2EFFFFH
2D0000H2DFFFFH
2C0000H2CFFFFH
190000H197FFFH
188000H18FFFFH
180000H187FFFH
178000H17FFFFH
170000H177FFFH
168000H16FFFFH
160000H167FFFH
2B0000H2BFFFFH
2A0000H2AFFFFH
290000H29FFFFH
280000H28FFFFH
270000H27FFFFH
260000H26FFFFH
250000H25FFFFH
158000H15FFFFH
150000H157FFFH
148000H14FFFFH
140000H147FFFH
138000H13FFFFH
130000H137FFFH
128000H12FFFFH
240000H24FFFFH
230000H23FFFFH
220000H22FFFFH
A21-A-1
(Byte
Mode)
120000H127FFFH
118000H11FFFFH
110000H117FFFH
A21-A0
(Word
Mode)
32Kw ord 64
32Kw ord 63
32Kw ord 62
32Kw ord 61
32Kw ord 60
32Kw ord 59
32Kw ord 58
32Kw ord 57
32Kw ord 56
32Kw ord 55
32Kw ord 54
32Kw ord 53
32Kw ord 52
32Kw ord 51
32Kw ord 50
32Kw ord 49
32Kw ord 48
32Kw ord 47
32Kw ord 46
32Kw ord 45
32Kw ord 44
32Kw ord 43
32Kw ord 42
32Kw ord 41
32Kw ord 40
32Kw ord 39
32Kw ord 38
32Kw ord 37
32Kw ord 36
32Kw ord 35
32Kw ord 34
5F0000H5FFFFFH
5E0000H5EFFFFH
5D0000H5DFFFFH
5C0000H5CFFFFH
5B0000H5BFFFFH
5A0000H5AFFFFH
590000H59FFFFH
2F8000H2FFFFFH
2F0000H2F7FFFH
2E8000H2EFFFFH
2E0000H2E7FFFH
2D8000H2DFFFFH
2D0000H2D7FFFH
2C8000H2CFFFFH
580000H58FFFFH
570000H57FFFFH
560000H56FFFFH
550000H55FFFFH
2C0000H2C7FFFH
2B8000H2BFFFFH
2B0000H2B7FFFH
2A8000H2AFFFFH
540000H54FFFFH
530000H53FFFFH
520000H52FFFFH
510000H51FFFFH
500000H50FFFFH
4F0000H4FFFFFH
4E0000H4EFFFFH
2A0000H2A7FFFH
298000H29FFFFH
290000H297FFFH
288000H28FFFFH
280000H287FFFH
278000H27FFFFH
270000H277FFFH
4D0000H4DFFFFH
4C0000H4CFFFFH
4B0000H4BFFFFH
4A0000H4AFFFFH
490000H49FFFFH
480000H48FFFFH
470000H47FFFFH
268000H26FFFFH
260000H267FFFH
258000H25FFFFH
250000H257FFFH
248000H24FFFFH
240000H247FFFH
238000H23FFFFH
460000H46FFFFH
450000H45FFFFH
440000H44FFFFH
A21-A-1
(Byte
Mode)
230000H237FFFH
228000H22FFFFH
220000H227FFFH
A21-A0
(Word
Mode)
32Kw ord 100
32Kw ord 99
32Kw ord 98
32Kw ord 97
32Kw ord 96
32Kw ord 95
32Kw ord 94
32Kw ord 93
32Kw ord 92
32Kw ord 91
32Kw ord 90
32Kw ord 89
32Kw ord 88
32Kw ord 87
32Kw ord 86
32Kw ord 85
32Kw ord 84
32Kw ord 83
32Kw ord 82
32Kw ord 81
32Kw ord 80
32Kw ord 79
32Kw ord 78
32Kw ord 77
32Kw ord 76
32Kw ord 75
32Kw ord 74
32Kw ord 73
32Kw ord 72
32Kw ord 71
32Kw ord 70
32Kw ord 69
x16 (Word
Mode)
3FF000H3FFFFFH
3FE000H3FEFFFH
3FD000H3FDFFFH
3FC000H3FCFFFH
3FB000H3FBFFFH
3FA000H3FAFFFH
7F2000H7F3FFFH
7F0000H7F1FFFH
7E0000H7EFFFFH
7D0000H7DFFFFH
7C0000H7CFFFFH
7B0000H7BFFFFH
7A0000H7AFFFFH
3F9000H3F9FFFH
3F8000H3F8FFFH
3F0000H3F7FFFH3E8000H3EFFFFH
3E0000H3E7FFFH3D8000H3DFFFFH
3D0000H3D7FFFH-
790000H79FFFFH
780000H78FFFFH
770000H77FFFFH
760000H76FFFFH
3C8000H3CFFFFH
3C0000H3C7FFFH3B8000H3BFFFFH
3B0000H3B7FFFH-
750000H75FFFFH
740000H74FFFFH
730000H73FFFFH
720000H72FFFFH
710000H71FFFFH
700000H70FFFFH
6F0000H6FFFFFH
3A8000H3AFFFFH
3A0000H3A7FFFH398000H39FFFFH
390000H397FFFH388000H38FFFFH
380000H387FFFH378000H37FFFFH
6E0000H6EFFFFH
6D0000H6DFFFFH
6C0000H6CFFFFH
6B0000H6BFFFFH
6A0000H6AFFFFH
690000H69FFFFH
680000H68FFFFH
370000H377FFFH368000H36FFFFH
360000H367FFFH358000H35FFFFH
350000H357FFFH348000H34FFFFH
340000H347FFFH-
670000H67FFFFH
660000H66FFFFH
338000H33FFFFH
330000H337FFFH-
4Kw ord 134
4Kw ord 133
4Kw ord 132
4Kw ord 131
4Kw ord 130
4Kw ord 129
4Kw ord 128
4Kw ord 127
32Kw ord 126
32Kw ord 125
32Kw ord 124
32Kw ord 123
32Kw ord 122
32Kw ord 121
32Kw ord 120
32Kw ord 119
32Kw ord 118
32Kw ord 117
32Kw ord 116
32Kw ord 115
32Kw ord 114
32Kw ord 113
32Kw ord 112
32Kw ord 111
32Kw ord 110
32Kw ord 109
32Kw ord 108
32Kw ord 107
32Kw ord 106
32Kw ord 105
BANK(VI)
100000H10FFFFH
F0000HFFFFFH
E0000HEFFFFH
D0000HDFFFFH
C0000HCFFFFH
B0000HBFFFFH
A0000HAFFFFH
32Kw ord 28
32Kw ord 65
32Kw ord 101
x8 (Byte
Mode)
7FE000H7FFFFFH
7FC000H7FDFFFH
7FA000H7FBFFFH
7F8000H7F9FFFH
7F6000H7F7FFFH
7F4000H7F5FFFH
BANK(VII)
A0000HA7FFFH
98000H9FFFFH
90000H97FFFH
88000H8FFFFH
32Kw ord 30
32Kw ord 29
32Kw ord 66
x16 (Word
Mode)
328000H32FFFFH
320000H327FFFH
318000H31FFFFH
310000H317FFFH
308000H30FFFFH
300000H307FFFH
BANK(VIII)
140000H14FFFFH
130000H13FFFFH
120000H12FFFFH
110000H11FFFFH
32Kw ord 31
32Kw ord 67
x8 (Byte
Mode)
650000H65FFFFH
640000H64FFFFH
630000H63FFFFH
620000H62FFFFH
610000H61FFFFH
600000H60FFFFH
BANK(VI)
D8000HDFFFFH
D0000HD7FFFH
C8000HCFFFFH
C0000HC7FFFH
B8000HBFFFFH
B0000HB7FFFH
A8000HAFFFFH
32Kw ord 32
x16 (Word
Mode)
218000H21FFFFH
210000H217FFFH
208000H20FFFFH
200000H207FFFH
1F8000H1FFFFFH
1F0000H1F7FFFH
BANK(V)
1B0000H1BFFFFH
1A0000H1AFFFFH
190000H19FFFFH
180000H18FFFFH
170000H17FFFFH
160000H16FFFFH
150000H15FFFFH
32Kw ord 33
x8 (Byte
Mode)
430000H43FFFFH
420000H42FFFFH
410000H41FFFFH
400000H40FFFFH
3F0000H3FFFFFH
3E0000H3EFFFFH
BANK(VI)
x16 (Word
Mode)
108000H10FFFFH
100000H107FFFH
F8000HFFFFFH
F0000HF7FFFH
E8000HEFFFFH
E0000HE7FFFH
BANK(V)
9
x8 (Byte
Mode)
210000H21FFFFH
200000H20FFFFH
1F0000H1FFFFFH
1E0000H1EFFFFH
1D0000H1DFFFFH
1C0000H1CFFFFH
128M-bit DINOR(IV) Flash Memory Map (Top 64Mbit / A22=VIH)
32Kw ord 104
32Kw ord 103
32Kw ord 102
32Kw ord 68
A21-A-1
(Byte
Mode)
A21-A0
(Word
Mode)
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Bus Operation
BYTE#=VIH
Pins
F-CE#
OE#
WE#
F-RP#
Array
VIL
VIL
VIH
VIH
Data Output
Status Register
VIL
VIL
VIH
VIH
Status Register Data
Identifier Code
VIL
VIL
VIH
VIH
Identifier Code
Mode
Read
DQ0-15
Page
VIL
VIL
VIH
VIH
Data Output
Output Disable
VIL
VIH
VIH
VIH
High-Z
Program
VIL
VIH
VIL
VIH
Command/Data in
Erase
VIL
VIH
VIL
VIH
Command
Others
VIL
VIH
VIL
VIH
Command
Stand by
VIH
1)
X
1)
X
VIH
High-Z
Deep Power Down
X1)
X1)
X1)
VIL
High-Z
F-CE#
OE#
WE#
F-RP#
DQ0-7
VIL
VIL
VIH
VIH
Data Output
Write
BYTE#=VIL
Pins
Mode
Array
Status Register
VIL
VIL
VIH
VIH
Status Register Data
Identifier Code
VIL
VIL
VIH
VIH
Identifier Code
Page
VIL
VIL
VIH
VIH
Data Output
Output Disable
Read
Write
VIL
VIH
VIH
VIH
High-Z
Program
VIL
VIH
VIL
VIH
Command/Data in
Erase
VIL
VIH
VIL
VIH
Command
Others
Stand by
Deep Power Down
1)
10
VIL
VIH
VIL
VIH
Command
VIH
X1)
X1)
VIH
High-Z
1)
1)
1)
VIL
High-Z
X
X
X
X can be VIH or VIL for control pins.
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Software Command Definition
Command List (WP# =VIH or VIL)
1st Bus Cycle
Command
Read Array
Page Read
Data 1)
Mode
Address
Write
A227)
Write
A0-A21=X8)
A227)
(DQ0-15)(DQ0-7)
Mode
2nd Bus Cycle
Address
Data 1)
A22-A18 A0 (DQ0-15)(DQ0-7)
3rd-5th Bus Cycle
Mode
Address
Read
SA+i6)
Data 1)
(DQ0-15)(DQ0-7)
FFH
F3H
Read
SA5)
90H
Read
A22=VIL
RD0
RDi
8)
Device Identifier
Write
A0-A21=X
A22=VIL
8)
A0-A21=X
Read Status Register
Clear Status Register
Write
Write
IA3)
ID
2)
Bank2)
A227)
70H
50H
Read
Bank
Bank2)
SRD 4)
A0-A21=X8)
Suspend
Write
Bank2)
B0H
Resume
Write
Bank2)
D0H
1) In the case of Word mode(BYTE#=VIH), upper byte data (DQ15-DQ8) is ignored.
2) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)
3) IA=ID code address: A0=VIL (Manufacturer’s code): A0=VIH (Device code), ID=ID code
4) SRD=Status Register Data
5) SA=A21-A2:1st Page Address, A1,A0:voluntary address / RD0=1st Page read data
6) SA+i: Page address(is equal to 1st Page Address of A21-A2), A1,A0: voluntary address / RDi: 2nd Page read data
7) In case of Bottom 64M-bit area, A22 must be set to VIL.
In case of Top 64M-bit area, A22 must be set to VIH.
8) X can be VIH or VIL.
Command List (WP# =VIH)
1st Bus Cycle
Command
Mode
Address
Write
Write
Bank7)
Bank7)
Write
7)
Data 1)
Mode
Address
Write
Write
WA2)
WA0 3)
Data 1)
(DQ0-15)(DQ0-7)
Word Program
Page Program
Page Buffer to Flash
Block Erase/Confirm
40H
41H
Bank
0EH
7)
3rd-129th Bus Cycles
3rd-257th Bus Cycles(Byte mode)
2nd Bus Cycle
20H
Mode Address
(DQ0-15)(DQ0-7)
Write
Write
WD 2)
WD03)
4)
D0H
5)
D0H1)
WA
Bank
Erase All Unlocked Blocks
Write
8)
A22
A0-A21=X9)
A7H
Write
A22
A0-A21=X9)
D0H1)
Clear Page Buffer
Write
A228)
55H
Write
A228)
D0H1)
8)
(DQ0-15)(DQ0-7)
Write
WAn 3)
WDn3)
1)
Write
9)
BA
Data 1)
9)
A0-A21=X
A0-A21=X
Single Data Load to Page Buffer
Write
A228)
A0-A21=X9)
74H
Write
WA2)
WD 2)
Flash to Page Buffer
Write
Bank7)
F1H
Write
RA6)
D0H1)
1) In the case of Word mode(BYTE#=VIH), upper byte data (DQ15-DQ8) is ignored.
2) WA=Write Address, WD=Write Data
3) WA0, WAn=Write Address, WD0, WDn=Write Data.
Word mode (BYTE#=VIH) : Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128
words (128-word x 16-bit), and also A22-A7 (block address, page address) must be valid.
Byte mode (BYTE#=VIL) : Write address and write data must be provided sequentially from 00H to FFH for A6-A-1. Page size is 256
Bytes (256-byte x 8-bit), and also A22-A7 (block address, page address) must be valid.
4) WA=Write Address: A22-A7 (block address, page address) must be valid.
5) BA=Block Address : A22-A12[Bank(I),Bank(VIII)], A22-A15 [Bank(II) ~ Bank(VII)]
6) RA=Read Address: A22-A7 (block address, page address) must be valid.
7) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)
8) In case of Bottom 64M-bit area, A22 must be set to VIL.
In case of Top 64M-bit area, A22 must be set to VIH.
9) X can be VIH or VIL.
11
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Software Command Definition
Command List (WP# =VIL)
Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are needed for page
program operation.
Setup Command for
Software Lock Release
Word Program
Page Program
Page Buffer to Flash
Block Erase/Confirm
Clear Page Buffer
Single Data Load to Page Buffer
Flash to Page Buffer
Setup Command for
Software Lock Release
1st Bus Cycle
Data
Address
Mode
2nd Bus Cycle
1)
(DQ0-15/DQ0-7)
8)
Write
Write
Write
Write
Write
Write
Write
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
60H
60H
60H
60H
60H
60H
60H
Mode
Write
Write
Write
Write
Write
Write
Write
4th Bus Cycle
Mode
1)
(DQ0-15/DQ0-7)
8)
6)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
Block
6)
Block
6)
Block
6)
Block
6)
Block
6)
Block
6)
Block
1)
Mode
(DQ0-15/DQ0-7)
8)
6)
Data
Address
Bank
Bank8)
Bank8)
Block#
Block# 6)
Block# 6)
Write
Write
Write
Bank
Bank8)
Bank8)
7BH
7BH
7BH
Block Erase/Confirm
Write
Bank8)
Block# 6)
Write
Bank8)
7BH
Clear Page Buffer
Write
8)
Bank
Block#
6)
Write
8)
Bank
7BH
Single Data Load to Page Buffer
Write
Write
Bank8)
Bank8)
Block# 6)
Block# 6)
Write
Write
Bank8)
Bank8)
7BH
7BH
6th Bus Cycle
ACH
ACH
ACH
ACH
ACH
ACH
ACH
8th-134th Bus Cycles
8th-262th Bus Cycles(Byte mode)
7th Bus Cycle
Data 1)
Address
Write
Write
Bank8)
Bank8)
Page Buffer to Flash
Block Erase/Confirm
Write
Write
8)
Bank
Bank8)
0EH
20H
Write
Write
WA
BA5)
D0H
D0H 1)
Clear Page Buffer
Write
55H
Write
Write
74H
Write
A229)
A0-A21=X10)
WA2)
D0H 1)
Single Data Load to Page Buffer
A229)
A0-A21=X10)
A229)
A0-A21=X10)
Flash to Page Buffer
Write
Bank8)
F1H
Write
RA7)
D0H 1)
(DQ0-15/DQ0-7)
40H
41H
Mode
Address
Write
Write
WA2)
WA0 3)
Data
Mode
Word Program
Page Program
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
8)
Bank
(DQ0-15/DQ0-7)
8)
Write
Write
Write
Setup Command for
Program or Erase Operations
Write
Write
Write
Write
Write
Write
Write
(DQ0-15/DQ0-7)
8)
1)
Word Program
Page Program
Page Buffer to Flash
Flash to Page Buffer
Mode
3rd Bus Cycle
1)
Data
Address
5th Bus Cycle
Data
Address
Address
Data
4)
(DQ0-15/DQ0-7)
WD 2)
WD03)
Mode Address
Write
Data
(DQ0-15/DQ0-7)
WAn 3)
WDn3)
1)
WD 2)
1) In the case of word mode(BYTE#=VIH) upper byte data (DQ15-DQ8) is ignored.
2) WA=Write Address, WD=Write Data
3) WA0, WAn=Write Address, WD0, WDn=Write Data. Write address and write data must be provided sequentially
from 00H to 7FH for A6-A0(word mode) and from 00H to FFH for A6-A-1(byte mode), respectively.
Page size is 128 words (128-word x 16-bit/ word mode) or Page size is 256 bytes (256-word x 8-bit/ byte mode),
and also A22-A7 (block address, page address) must be valid.
4) WA=Write Address: A22-A7 (block address, page address) must be valid.
5) BA=Block Address : A21-A12[Bank(I),Bank(VIII)], A21-A15 [Bank(II) ~ Bank(VII)]
6) Block=Block Address: A21-A15, Block#=A21#-A15#
Address
Block
Block#
DQ7
fixed 0
fixed 0
DQ6
A21
A21#
DQ5
A20
A20#
DQ4
A19
A19#
DQ3
A18
A18#
DQ2
A17
A17#
DQ1
A16
A16#
DQ0
A15
A15#
7) RA=Read Address: A22-A7 (block address, page address) must be valid.
8) Bank=Bank address (Bank(I)-Bank(VIII): A22-18)
9) In case of Bottom 64M-bit area, A22 must be set to VIL.
In case of Top 64M-bit area, A22 must be set to VIH.
10) X can be VIH or VIL.
12
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Block Locking
F-RP#
Write Protection Provided
Bank (I),(VIII)
Bank (II),(VII) Bank (III),(VI)
Boot
Parameter/Main
Main
Main
Locked
Locked
Locked
Locked
F-WP#
VIL
X
VIH
Notes
Bank (IV),(V)
Main
Locked
VIL
Locked
Locked
Locked
Locked
Locked
VIH
Unlocked
Unlocked
Unlocked
Unlocked
Unlocked
Deep Power Down Mode
All Blocks Locked(Valid to operate
Softw are Lock Release)
All Blocks Unlocked
WP# pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0).
Status Register
Symbol
(I/O Pin)
S.R. 7
S.R. 6
S.R. 5
S.R. 4
S.R. 3
S.R. 2
S.R. 1
S.R. 0
13
(DQ7)
(DQ6)
(DQ5)
(DQ4)
(DQ3)
(DQ2)
(DQ1)
(DQ0)
Definition
Status
Write State Machine Status
Suspend Status
Erase Status
Program Status
Block Status after Erase
Reserved
Reserved
Reserved
"1"
"0"
Ready
Suspended
Error
Error
Error
-
Bus y
Operation in Progress/Completed
Successful
Successful
Successful
-
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Device ID Code
Pins
Code
Manufacturer Code
Device Code
A22
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex. Data
VIL
VIL
VIL
VIH
"0"
"1"
"0"
"0"
"0"
"1"
"1"
"1"
"1"
"1"
"1"
"0"
"0"
"0"
"0"
"1"
1CH
B9H
The output of upper byte data (DQ15-DQ8) is “0H”.
A22 must be set “VIL”.
Absolute Maximum Ratings
Symbol
Parameter
VCC
VCC Voltage
VI1
Ta
Tbs
Tstg
Iout
All Input or Output Voltage1)
Ambient Temperature
Temperature under Bias
Storage Temperature
Output Short Circuit Current
Conditions
With Respect to GND
Min.
Max.
Units
-0.2
4.6
V
-0.6
-40
-50
-65
4.6
85
95
125
100
V
°C
°C
°C
mA
1)Minimum DC voltage is –0.6V on input / output pins. During transitions, the level may undershoot to –2.0V for periods
<20ns. Maximum DC voltage on input / output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V
for periods <20ns.
DC electrical characteristics
Symbol
(Ta= -40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Parameter
Limits
Test Conditions
Min.
-2
ILI
Input Leakage Current
0V< VIN< VCC
ILO
Output Leakage Current
0V< VOUT< VCC
VCC= 3.6V, VIN= GND/VCC, F-CE#= F-RP#=
F-WP#= VCC±0.3V
VCC= 3.6V, VIN= VIL/VIH, F-RP#= VIL
VCC= 3.6V, VIN= GND or VCC, F-RP#= GND±
0.3V
ISB2
VCC Stand by Current
ISB3
ISB4
VCC Deep Power Down Current
ICC1 VCC Read Current for Word
ICC1P VCC Page Read Current for Word
ICC2 VCC Write Current for Word
ICC3 VCC Program Current
ICC4 VCC Erase Current
ICC5 VCC Suspend Current
VIL
VIH
VOL
VOH1
VOH2
VLKO
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Low VCC Lock Out Voltage2)
Typ.1)
-20
Max.
2
20
0.2
12
10
50
0.2
12
Vcc = 3.6V, VIN = VIL/VIH, F-RP# = OE# = 5MHz
VIH, F-CE# =VIL, Iout = 0mA
20
30
1MHz
4
8
5MHz
5
10
Vcc = 3.6V, VIN = VIL/VIH, RP# = OE# =
VIH, CE# = VIL, Iout = 0mA
Vcc = 3.6V, VIN = VIL/VIH, F-RP# = OE# = VIH, FCE# = WE# = VIL
15
VCC = 3.6V, VIN = VIL/VIH, F-CE#= F-RP# = FWP# = VIH
VCC = 3.6V, VIN = VIL/VIH, F-CE#= F-RP# = FWP# = VIH
VCC = 3.6V, VIN = VIL/VIH, F-CE#= F-RP# = FWP# = VIH
35
35
400
-0.5
2.4
IOL = 4.0mA
IOH = -2.0mA
IOH = -100uA
0.85xVCC
VCC-0.4
1.5
0.4
VCC+0.5
0.45
2.2
All currents are in RMS unless otherwise noted.
1) Typical values at Flash VCC=3.3V, Ta=25 °C.
2) To protect against initiation of write cycle during Flash VCC power up / down, a write cycle is locked out for Flash VCC less than VLKO.
If Flash VCC is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Flash
VCC is less than VLKO, the alteration of memory contents may occur.
14
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC electrical characteristics
(Ta=-40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Read Only Mode
Limits
Symbol
tRC
ta(AD)
ta(CE)
ta(OE)
ta(PAD)
tCEPH
tCLZ
tDF(CE)
tOLZ
tDF(OE)
tPHZ
ta(BYTE)
tBHZ
tOH
tBCD
tBAD
tOEH
tPS
tAVAV
tAVQV
tELQV
tGLQV
tPAVQV
tELQX
tEHQZ
tGLQX
tGHQZ
tPLQZ
tFL/HQV
tFLQZ
tOH
tELFL/H
tAVFL/H
tWHGL
tPHEL
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Page Read Access Time
CE# "H"Pulse width
Chip Enable to Output in Low-Z
Chip Enable High to Output in High-Z
Output Enable to Output in Low-Z
Output Enable to High to Output in High-Z
RP# Low to Output High-Z
BYTE# access time
BYTE# low to output high-Z
Output Hold from CE#, OE# and Addresses
CE# low to BYTE# high or low
Address to BYTE# high or low
OE# Hold from WE# High
RP# Recovery to CE# Low
Units
Flash VCC=3.0-3.6V
Min.
70
Typ.
Max.
70
70
30
25
30
0
25
0
25
150
70
25
0
5
5
10
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-Timing measurements are made under AC waveforms for read operations.
15
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC electrical characteristics
(Ta=-40 ~85 °C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Read / Write Mode (WE# control)
Limits
Symbol
tWC
tAS
tAH
tDS
tDH
tOEH
tCS
tCH
tWP
tWPH
tBS
tBH
tGHWL
tBLS
tBLH
tDAP
tDAP
tDAP
tDAE
tWHRL
tPS
tAVAV
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tELWL
tWHEH
tWLWH
tWHWL
tFL/HWH
tWHFL/H
tGHWL
tPHHWH
tQVPH
tWHRH1
tWHRH1
tWHRH1
tWHRH2
tWHRL
tPHWL
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE# Hold from WE# High
Chip Enable Setup Time
Chip Enable Hold Time
Write Pulse Width
Write Pulse Width High
Byte enable high or low set-up time
Byte enable high or low hold time
OE# Hold to WE# Low
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
Duration of Auto Program Operation(Word Mode)
Duration of Auto Program Operation(Byte Mode)
Duration of Auto Program Operation(Page Mode)
Duration of Auto Block Erase Operation
Delay Time During Internal Operation
RP# Recovery to CE# Low
Units
Flash VCC=3.0-3.6V
Min.
70
35
0
35
0
10
0
0
35
30
35
70
0
70
0
Typ.
Max.
30
30
4
150
300
300
80
600
70
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
-Read timing parameters during command write operations mode are the same as during read only operation mode.
-Typical values at Flash VCC=3.3V and Ta=25 °C.
Read / Write Mode (CE# control)
Limits
Symbol
Parameter
Min.
tWC
tAS
tAH
tDS
tDH
tOEH
tWS
tWH
tCEP
tCEPH
tBS
tBH
tGHEL
tBLS
tBLH
tDAP
tDAP
tDAP
tDAE
tEHRL
tPS
tAVAV
tAVEH
tEHAX
tDVEH
tEHDX
tEHGL
tWLEL
tEHWH
tELEH
tEHEL
tFL/HEH
tEHFL/H
tGHEL
tPHHEH
tQVPH
tEHRH1
tEHRH1
tEHRH1
tEHRH2
tEHRL
tPHEL
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
OE# Hold from CE# High
Write Enable Setup Time
Write Enable Hold Time
CE# Pulse Width
CE#"H" Pulse Width
Byte enable high or low set-up time
Byte enable high or low hold time
OE# Hold to CE# Low
Block Lock Setup to Write Enable High
Block Lock Hold from Valid SRD
Duration of Auto Program Operation(Word Mode)
Duration of Auto Program Operation(Byte Mode)
Duration of Auto Program Operation(Page Mode)
Duration of Auto Block Erase Operation
Delay Time During Internal Operation
RP# Recovery to CE# Low
Units
Flash VCC=3.0-3.6V
Typ.
Max.
70
35
0
35
0
10
0
0
35
30
35
70
0
70
0
30
30
4
150
150
300
300
80
600
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
-Timing measurements are made under AC waveforms for read operations.
-Typical values at Flash VCC=3.3V and Ta=25 °C.
16
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Program / Erase Time
Parameter
Min.
Block Erase Time
Main Block Write Time (Byte Mode)
Main Block Write Time (Word Mode)
Page Write Time
Flash to Page Buffer Time
Typ.
Max.
Units
150
2
1
4
100
600
8
4
80
150
ms
sec
sec
ms
µs
Program Suspend / Erase Suspend Time
Parameter
Min.
Typ.
Program Susupend Time
Erase Susupend Time
Max.
Unit
15
15
µs
µs
Min.
Typ.
Flash VCC Power Up / Down Timing
symbol
Parameter
tVCS
tVHEL
F-RP#=VIH Setup Time from Flash VCC min.
F-CE#=VIL Setup Time from Flash VCC min.
2
60
Max.
Unit
µs
µs
During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming.
The device must be protected against initiation of write cycle for memory contents during power up / down. The delay time
of min. 60 µsec is always required before read operation or write operation is initiated from the time Flash VCC reaches
Flash VCC min. during power up /down. By holding F-RP#=VIL, the contents of memory is protected during Flash VCC
power up / down. During power up, F-RP# must be held VIL for min. 2µs from the time Flash VCC reaches Flash VCC min..
During power down, F-RP# must be held VIL until Flash VCC reaches GND. F-RP# doesn’t have latch mode, therefore FRP# must be held VIH during read operation or erase / program operation.
17
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Flash VCC Power up / down Timing
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
3.0V
V CC
tVHEL
GND
RP#
CE#
WE#
tVCS
V IH
V IL
V IH
tPS
V IL
tPS
V IH
V IL
AC Waveforms for Read Operation and Test Conditions
Test Conditions for
AC Characteristics
tRC
A22 -A0 (WORD)
A22 -A-1 (BYTE)
F-CE#
OE#
V IH
V IL
ta(AD)
V IH
V IL
V IH
Input Voltage : VIL=0V, V IH=Flash Vcc
Input Rise and Fall Times : <5ns
Reference Voltage
at timing measurement : (Flash Vcc)/2
Output Load : 1 TTL gate +
CL(30pF)
or
Address Valid
tDF(CE)
tCEPH
V IL
ta(CE)
tOEH
tDF(OE)
V IH
WE#
V IL
V OH
DATA
VO
V IH
F-RP#
1.3V
High-Z
tPS
tCLZ
FFH
ta(OE)
tOLZ
tOH
1N914
High-Z
Output Valid
tPHZ
3.3kohm
DUT
V IL
CL=30pF
CL=30pF
- After inputting Read Array Command FFH, it is necessary to make F-CE# “H” pulse more than 30ns (tCEPH).
And after inputting Read Array Command FFH, it is also necessary to keep 30ns to recover before starting read
after WE# rises “H” in case of changing a part or all of addresses( A22~A0/A22~A-1) and F-CE#=“L”.
18
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Byte AC Waveforms for Read Operation
ADDRESS
A22-A0
F-CE#
OE#
V IH
ta(AD)
V IH
V IL
tDF(CE)
V IH
tBCD
tBAD
V IL
V IH
BYTE#
V IL
DATA
D7-D0
V OH
DATA
D14-D8
D15/A-1
Address Valid
Address Valid
V IL
High-Z
V OL
V OH
ta(CE)
ta(OE)
tOLZ
tCLZ
tDF(OE)
tBAD
tOH
ta(BYTE)
Output Valid
tBHZ
Valid
High-Z
Valid
V OL
V IH
V IL
Valid
ta(BYTE)
ta(AD)
Address Valid
D15
A-1
When BYTE# = VIH, F-CE# = OE# = VIL, D15/A-1 is output status. At this time, input signal must not be applied.
19
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Word / Byte Program Operation (WE# Control)
ADDRESS VIH
A22-A0 (Word) V
IL
A22-A -1(Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
VIH
Bank Address Address Valid
Valid
tWC
Bank Address Valid
tAH
tAS
tCS
Program
Bank Address Valid
Read Status Register
tCH
tWP
VIL
ta(CE)
tWPH
tOEH
ta(OE)
VIH
VIL
VIH
tWHRL
tDS
High-Z
VIL
DIN
40H
VIL
SRD
Busy
Ready
tDH
tPS
VIH
SRD
VIL
tBS
VIH
tBLH
tDAP
tBLS
VIH
FFH
Write Read Array Command
tBH
VIL
AC Waveforms for Word / Byte Program Operation (F-CE# Control)
ADDRESS VIH
A22-A0 (Word) V
IL
A22-A -1(Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
20
Bank Address
Valid
Address Valid
tWC
tAS
Bank Address Valid
tAH
Program
VIH
tCEP
tWS
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Read Status Register
ta(CE)
VIH
VIL
Bank Address Valid
tOEH
tWH
tEHRL
tDS
High-Z
40H
tPS
ta(OE)
DIN
SRD
Busy
Ready
FFH
Write Read Array Command
tDAP
tBLS
tBS
SRD
tDH
tBLH
tBH
VIL
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Page Program Operation (WE# Control)
ADDRESS VIH
A22-A7
VIL
A6-A0 (Word)
V
A6-A -1(Byte) IH
VIL
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
VIH
Bank Address
Valid
Address Valid
The Other Bank
Address Valid
00H
Valid
01H-7EH
7FH
00H
Valid
01H-FEH
FFH
tWC
tCH
tWP
VIL
tWPH
tOEH
ta(CE)
ta(OE)
tOEH
ta(OE) tGHWL
VIL
tWHRL
tDH
High-Z
41H
VIL
DIN
VIL
DOUT
DIN
DIN
\
tDS
tPS
VIH
SRD
SRD
Busy
Ready
VIL
tDAP
tBLH
tBS
VIH
FFH
Write Read Array Command
tBLS
VIH
Bank Address Valid
Read Status Register
ta(CE)
VIH
VIH
Bank Address Valid
tAH
tAS
tCS
Address Valid
tBH
VIL
AC Waveforms for Page Program Operation (F-CE# Control)
ADDRESS VIH
A22 - A7
VIL
A6-A0 (Word)
VIH
A6-A -1(Byte)
VIL
F-CE#
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
21
Bank Address
Valid
tWC
VIH
VIL
VIH
The Other Bank
AddressVaild
Valid
Address
Address Valid
00H
Valid
01H-7EH
7FH
00H
Valid
01H-FEH
FFH
tWH
VIL
tCEP
tCEPH
VIL
VIL
VIH
VIL
VIH
VIL
VIH
ta(CE)
ta(OE)
tGHEL
tOEH
tOEH
ta(OE)
tEHRL
tDH
High-Z
41H
tPS
DIN
DOUT
DIN
SRD
DIN
Busy
tDS
SRD
Ready
tDAP
FFH
Write Read Array Command
tBLH
tBLS
tBS
Bank Address Valid
Read Status Register
ta(CE)
VIH
VIH
Bank Address Valid
tAH
tAS
tWS
Address Valid
tBH
VIL
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Erase Operation (WE# Control)
ADDRESS VIH
A22-A0 (Word) V
IL
A22-A -1(Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
VIH
Bank Address
Valid
Bank Address Valid
Address Valid
tWC
tAH
tAS
tCS
Erase
ta(CE)
tCH
tWP
VIL
tWPH
tOEH
ta(OE)
VIH
VIL
VIH
tWHRL
tDS
High-Z
20H
VIL
D0H
VIL
SRD
SRD
Busy
Ready
tDH
tPS
VIH
VIL
tDAE
tBS
VIH
FFH
Write Read Array Command
tBLS
VIH
Bank Address Valid
Read Status Register
tBLH
tBH
VIL
AC Waveforms for Erase Operation (F-CE# Control)
ADDRESS VIH
A22-A0 (Word) V
IL
A22-A -1(Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
BYTE#
22
Bank Address
Valid
tWC
Bank Address Valid
Address Valid
tAH
tAS
Erase
ta(CE)
VIH
VIL
VIH
tCEP
tWS
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Bank Address Valid
Read Status Register
tOEH
tWH
tEHRL
tDS
High-Z
20H
tPS
ta(OE)
D0H
SRD
SRD
Busy
Ready
tDH
tDAE
tBLS
tBS
FFH
Write Read Array Command
tBLH
tBH
VIL
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Word / Byte Program Operation with BGO (WE# Control)
Program in one bank
ADDRESS VIH
A22 - A7 VIL
Bank Address
Valid
A6-A0 (Word) VIH
OE#
WE#
DATA
VIH
tAH
tAS
tWC
VIH
VIL
Address Valid
Address Valid
A6-A -1(Byte) VIL
F-CE#
Read Status Register
tCS
Change Bank Address
Read Array in another bank
Address
Valid
Address
Valid
Address
Valid
Address
Valid
Program
ta(CE)
tCH
tWP
VIL
tWPH
tOEH
ta(OE)
VIH
VIL
VIH
tWHRL
tDS
High-Z
40H
VIL
SRD
DIN
Busy
DOUT
DOUT
tDH
AC Waveforms for Word / Byte Program Operation with BGO (F-CE# Control)
Read Status Register
Program in one bank
ADDRESS VIH
A22 - A7 VIL
Bank Address
Valid
A6-A0 (Word) VIH
A6-A -1(Byte) VIL
F-CE#
OE#
WE#
DATA
23
Address Valid
Address Valid
tW C
VIH
tAH
tAS
tWS
tCEP
VIL
VIH
VIL
Address
Valid
Address
Valid
Address
Valid
ta(CE)
VIH
VIH
Address
Valid
Program
VIL
VIL
Change Bank Address
Read Array in another bank
tOEH
tW H
tEHRL
tDS
High-Z
40H
ta(OE)
SRD
DIN
Busy
DOUT
DOUT
tDH
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Page Program Operation with BGO (WE# Control)
Change Bank Address
Read Array in another bank
Program in one bank
ADDRESS VIH
A22-A7
VIL
Bank Address
Valid
Address Valid
A6-A0 (Word) VIH
A6-A -1(Byte) V
IL
F-CE#
OE#
WE#
DATA
VIH
01H-7EH
7FH
00H
01H-FEH
FFH
tWC
VIH
VIL
00H
Address
Valid
Address
Valid
Address
Valid
ta(CE)
tAH
tAS
tCS
Address
Valid
ta(OE)
tCH
VIL
tWP
tWPH
tOEH
\
VIH
VIL
VIH
tWHRL
tDH
High-Z
VIL
41H
DIN
DIN
SRD
DIN
Busy
DOUT
DOUT
tDS
AC Waveforms for Page Program Operation with BGO (F-CE# Control)
Change Bank Address
Read Array in another bank
Program in one bank
ADDRESS VIH
A22 - A7
VIL
Bank Address
Valid
A6-A0 (Word) VIH
A6-A -1(Byte)
F-CE#
OE#
WE#
DATA
24
VIL
VIL
VIH
00H
01H-7EH
7FH
00H
01H-FEH
FFH
tWC
VIH
VIL
tWH
tCEP
Address
Valid
ta(CE)
tAH
tAS
tWS
Address
Valid
Address Valid
ta(OE)
tCEPH
tOEH
VIH
VIL
VIH
VIL
tEHRL
tDH
High-Z
41H
DIN
DIN
tDS
DIN
SRD
Busy
DOUT
DOUT
tDAP
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Erase Operation with BGO (WE# Control)
Program in one bank
ADDRESS VIH
A22-A0 (Word)
V
A22-A-1 (Byte) IL
VIH
F-CE#
VIL
OE#
WE#
DATA
VIH
Read Status Register
Bank Address
Valid
Change Bank Address
Read Array in another bank
Address
Valid
Address Valid
tWC
tAH
tAS
tCS
tCH
tWP
VIL
ta(CE)
tWPH
tOEH
ta(OE)
VIH
VIL
VIH
tWHRL
tDS
High-Z
20H
VIL
Address
Valid
SRD
D0H
DOUT
Busy
DOUT
tDH
AC Waveforms for Erase Operation with BGO (F-CE# Control)
Program in one bank
ADDRESS VIH
A22-A0 (Word) VIL
A22-A-1 (Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
25
Bank Address
Valid
tWC
Read Status Register
Address Valid
VIH
VIL
Address
Valid
ta(CE)
tWS
tCEP
VIL
VIH
Address
Valid
tAH
tAS
VIH
VIL
Change Bank Address
Read Array in another bank
tOEH
tWH
tEHRL
tDS
High-Z
20H
ta(OE)
SRD
D0H
Busy
DOUT
DOUT
tDH
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Suspend Operation (WE# Control)
ADDRESS VIH
A22-A0 (Word) V
A22-A-1 (Byte) IL
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
Bank Address Valid
Bank Address Valid
tAH
tAS
tCS
VIH
tCH
ta(CE)
tWP
VIL
Read Status Register
tOEH
ta(OE)
VIH
VIL
VIH
Suspend Time
High-Z
S.R.6,7=1
SRD
B0H
VIL
Valid
VIH
VIL
tBLH
VIH
VIL
AC Waveforms for Suspend Operation (F-CE# Control)
ADDRESS VIH
A22-A0 (Word) V
IL
A22-A-1 (Byte)
VIH
F-CE#
VIL
OE#
WE#
DATA
F-RP#
F-WP#
26
Bank Address Valid
Bank Address Valid
tAH
tAS
Read Status Register
tOEH
VIH
VIL
VIH
tWS
tCEP
tWH
VIL
VIH
VIL
ta(OE)
Suspend Time
High-Z
B0H
ta(CE)
S.R.6,7=1
SRD
Valid
VIH
VIL
tBLH
VIH
VIL
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
AC Waveforms for Device ID Read Operation with BBR(Back Bank Read)
Change Bank Address
ADDRESS VIH
A22 - A0
VIL
F-CE#
OE#
WE#
DATA
Bank Address Valid
VIH
High-Z
VIL
ta(CE)
ta(OE)
ta(AD)
VIL
VIH
ta(CE)
ta(OE)
tWP
VIH
Address Valid
tCH
tCS
VIL
Bank Address Valid
ta(CE)
tWC
VIH
VIL
Address Valid
Return Bank Address
90H
ta(OE)
ta(AD)
ta(AD)
Dout
ID
ID
AC Waveforms for Status Register Read Operation with BBR(Back Bank Read)
Change Bank Address
ADDRESS VIH
VIL
A22 - A0
F-CE#
OE#
WE#
DATA
27
Bank Address Valid
VIL
VIH
tCS
VIL
VIL
ta(OE)
High-Z
ta(CE)
ta(OE)
tEHRL
VIL
VIH
ta(CE)
tCH
tWP
VIH
Bank Address Valid
Address Valid
ta(CE)
VIH
Return Bank Address
70H
ta(OE)
ta(AD)
ta(AD)
SRD
Dout
SRD
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Word / Byte Program Flow Chart
Start
Page Program Flow Chart
Start
Write 40H
Write 41H
Write Address,
Data
n=0
Status Register
Read
Write Address n,
DATA n
NO
SR.7 = 1?
YES
Write
B0H?
NO
n=n+1
NO
n = 7FH?
n = FFH?
YES
YES
Status Register
Read
Full Status Check
If Desired
Suspend Loop
Write D0H
Word / Byte Program
Completed
NO
SR.7 = 1?
YES
YES
NO
YES
Full Status Check
If Desired
Suspend Loop
Block Erase Flow Chart
Write D0H
Page Program
Completed
Start
Write
B0H?
YES
Write 20H
Status Register Check Flow Chart
Start
Write D0H
Block Address
YES
Command
Sequence Error
NO
Block Erase
Error
NO
Program Error
(Page Program)
NO
Block Erase Error
(Block Fail)
SR.4,5 = 1?
Status Register
Read
NO
SR.5 = 0?
NO
SR.7 = 1?
YES
Full Status Check
If Desired
Erase
Completed
Write
B0H?
YES
NO
YES
SR.4 = 0?
YES
Suspend Loop
Write D0H
YES
SR.3 = 0?
YES
Pass
(Block Erase, Program)
28
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Single Data Load to Page Buffer
Flow Chart
Suspend / Resume Flow Chart
Start
Start
Write 74H
Write B0H
Write Address,
Data
Status Register
Read
NO
Load
Finished?
Suspend
NO
S.R. 7=1?
YES
YES
Single Data Load
To Page Buffer
Completed
NO
S.R. 6=1?
Erase/ Program
Finished
YES
Write FFH
Page Buffer to Flash Flow Chart
Start
Read Array
Data
Write 0EH
Read
Finished?
NO
YES
Write D0H
Resume
Write D0H
Page Address
Operation
Restart
Status Register
Read
Clear Page Buffer Flow Chart
NO
SR.7 = 1?
YES
Full Status Check
If Desired
Write
BOH?
YES
NO
Start
Write 55H
Suspend Loop
Write D0H
Page Buffer
To Flash
Completed
29
Write D0H
YES
Clear Page Buffer
Completed
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Operation Status (F-WP#=VIH)
Clear
Status Register
50H
Read
Status Register
Read/Standby State
(Random Read Mode)
70H
70H
90H
Read
Device Identifier
Back Bank Read State
(Random Read)
FFH
90H
Read Array
Change Bank
Address
FFH
Read Array
(Random Read)
Others 3)
D0H
Setup State
Clear Page Buffer
Setup
74H
55H
Single Data Load
to Page Buffer
Setup
WD
F1H
D0H
41H
0EH
Flash to
Page Buffer
Page Buffer to
Flash
Setup
Setup
Other
D0H
Page Program
Setup
Wdi
I=0-127
Program &
Verify
Ready
40H
A7H
20H
Word Program
Setup
Block Erase
Setup
WD
Internal State
B0H
B0H
D0H
D0H
Read
Status Register
D0H
Erase All Unlocked
Blocks Setup
D0H
Others
Erase &
Verify
Read
Status Register
Change
Bank Address
Read State with BGO
Read Array
(Random Read)
Read State with BGO
Read Array
(Random Read)
Read
Status Register
Suspend
State
Change
Bank Address
70H
FFH
Read Array
(Random Read)
1) After setting up Clear Page Buffer, D0H enables to clear Page Buffer.
2) To access any bank during Erase All Unlocked Block results Status Register Read.
Although Read Status Register Command and Read Array Command can be issued under Suspend State,
output data make no sense.
30
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
M5M29KE131BVP
Notice: This is not a final specification.
Some parametric limits are subject to change.
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Operation Status (F-WP#=VIL)
50H
Clear
Status Register
Read
Status Register
Read/Standby State
(Random Read Mode)
70H
70H
90H
Read
Device Identifier
Back Bank Read State
FFH
90H
Read Array
(Random Read)
Change Bank
Address
WD
Change Bank
Address
Clear Page Buffer
Setup
55H
Single Data Load
to Page Buffer
Setup
Others
3)
BA#
Software Lock
Release Setup
Read Array
Setup State
Others
D0H
D0H
Others 4)
(Random Read)
Read Array
(Random Read)
FFH
7BH
74H
Page Buffer to
Flash
Setup
Setup
Other
D0H
3)
BA
Software Lock
Release Setup
60H
Software Lock
Release Setup
41H
Page Program
Setup
Wdi
I=0-127
Program &
Verify
Ready
Others
ACH Software Lock
Release Setup
Software Lock
Release Setup
0EH
F1H
Flash to
Page Buffer
Others
40H
20H
Word Program
Setup
WD
Block Erase
Setup
D0H
Internal State
B0H
B0H
D0H
D0H
Other
Erase &
Verify
Read
Status Register
Read
Status Register
Change Bank
Address
Read
Status Register
Read State with BGO
Read Array
(Random Read)
Read State with BGO
Read Array
(Random Read)
Suspend
State
70H
FFH
Change Bank
Address
Read Array
(Random Read)
1) BA, BA#: Block Address, Block Address# (Shown in Command List(F-WP#=VIL) in detail).
2) After setting up Clear Page Buffer, D0H enables to clear Page Buffer.
31
Rev.0.2_48a_bezz
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
Renesas LSIs
M5M29KE131BVP
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Package Dimension
32
48P3R-C
Rev.0.2_48a_bezz
Renesas LSIs
Preliminary
Notice: This is not a final specification.
Some parametric limits are subject to change.
M5M29KE131BVP
134,217,728-BIT (16,777,216-WORD BY 8-BIT / 8,388,608-WORD BY 16-BIT)
CMOS FLASH MEMORY
Stacked-uMCP (micro Multi Chip Package)
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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REJ03C0183-0010Z
© 2003 Renesas Technology Corp.
New publication, effective April 2003.
Specifications subject to change without notice