MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DESCRIPTION The MITSUBISHI Mobile FLASH M5M29GB/T161BWG are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. The M5M29GB/T161BWG are fabricated by CMOS technology for the peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 6x8-balls CSP (0.75mm ball pitch) . FEATURES Organization Boot Block M5M29GB161BWG ........................ Bottom Boot M5M29GT161BWG ........................ Top Boot .................................1048,576 word x 16bit (M5M29GB/T161BWG) ............................. VCC = 2.7~3.6V Supply voltage ................................ Access time Other Functions Soft Ware Command Control Selective Block Lock Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I) and Bank(II) .............................. 90ns (Max.) Power Dissipation ................................. 54 mW (Max. at 5MHz) Read (After Automatic Power saving) .......... 0.33µW (typ.) .......................126 mW (Max.) Program/Erase ................................. Standby 0.33µW (typ.) ....................... 0.33µW (typ.) Deep power down mode Auto program for Bank(I) ................................. 4ms (typ.) Program Time Program Unit (Byte Program) .........................1word (Page Program) ......................... 128word Auto program for Bank(II) ................................. 4ms (typ.) Program Time ................................. 128word Program Unit Auto Erase ................................. 40 ms (typ.) Erase time Erase Unit Bank(I) Boot Block ..................... 16Kword x 1 .............. 16Kword x 7 Parameter Block ...................... Bank(II) Main Block 32Kword x 28 Package 7mm x 8.5mm CSP (Chip Scale Package) - 6 x 8 balls, 0.75mm ball pitch APPLICATION Digital Cellular Phone Telecommunication Mobile Computing Machine PDA (Personal Digital Assistance) Car Navigation System Video Game Machine Program/Erase cycles .........................................100Kcycles PIN CONFIGURATION (TOP VIEW) 8.5mm A13 A11 A8 5 A14 A10 WE# RP# 4 A15 A12 A9 3 A16 D14 2 NC 1 INDEX A19 A7 A4 A18 A17 A5 A2 NC NC A6 A3 A1 D5 D11 D2 D8 CE# A0 D15 D6 D12 D3 D9 D0 GND GND D7 D13 D4 VCC D10 D1 OE# A B C D E F G H WP2# WP1# 7.0mm 6 M5M29GB/T161BWG CSP(0.75mm ball pitch):48FJA 16-bit version NC : NO CONNECTION 1 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BLOCK DIAGRAM 128 WORD PAGE BUFFER Main Block Bank(II) X-DECODER Y-DECODER 32KW VCC (3.3V) 28 GND (0V) Main Block Bank(I) ADDRESS INPUTS A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Parameter Block7 Parameter Block6 Parameter Block5 Parameter Block4 Parameter Block3 Parameter Block2 Parameter Block1 Boot Block 32KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW 16KW Y-GATE / SENSE AMP. STATUS / ID REGISTER CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT WRITE PROTECT INPUT WRITE PROTECT INPUT RESET/POWER DOWN INPUT CE# OE# WE# WP1# WP2# RP# MULTIPLEXER CUI WSM INPUT/OUTPUT BUFFERS DQ15 DQ14DQ13 DQ12 DQ3DQ2 DQ1DQ0 DATA INPUTS/OUTPUTS M5M29GB/T161BWG (16 bit version) 2 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FUNCTION The M5M29GB/T161BWG includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption. Read The M5M29GB/T161BWG has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the M5M29GB/T161BWG automatically resets to read array mode. In the read array mode, low level input to CE# and OE#, high level input to WE# and RP#, and address signals to the address inputs (A19-A0:M5M29GB/T161BWG) output the data of the addressed location to the data input/output (D15-D0:M5M29GB/T161BWG). Deep Power-Down When RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid. Automatic Power-Saving (APS) The Automatic Power-Saving minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. While in this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed. Write Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE# to low level, while CE# is at low level and OE# is at high level. Address and data are latched on the earlier rising edge of WE# and CE#. Standard micro-processor write timings are used. Alternating Background Operation (BGO) The M5M29GB/T161BWG allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Read array operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. Output Disable When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. 3 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the Command User Interface. Read Array Command (FFH) The device is in Read Array mode on initial device power up and after exit from deep powerdown, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically. Read Device Identifier Command (90H) It can normally read device identifier codes when Read Device Identifier Code Command(90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from address 0000H and 0001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE# or CE#. So CE# or OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. C)Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H) Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programing the data on the page buffer is cleared automatically. This command is valid for only Bank(I) alike Word Program. Clear Page Buffer Command (55H) Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. DATA PROTECTION Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Program Commands A)Word Program (40H) Word program is executed by a two-command sequence. The Word Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The Word Program Command is Valid for only Bank(I). B)Page Program for Data Blocks (41H) Page Program for Bank(I) and Bank(II) allows fast programming of 128words of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle , write data must be serially inputted. Address A6-A0 have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation. 4 The M5M29GB/T161BWG provides selectable block locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the M5M29GB/T161BWG have a master Write Protect pin (WP1# & WP2#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when WP1# or WP2# is low. When WP1# & WP2# are high , all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for details. Power Supply Voltage When the power supply voltage (Vcc) is less than VLKO, Low VCC Lock-Out voltage, the device is set to the Read-only mode. Regarding DC electrical characteristics of VLKO, see P.9 A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin (2.7V). During power up, RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device. MEMORY ORGANIZATION The M5M29GB/T161BWG has one 16Kword boot block, seven 16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword main blocks for Bank(II). A block is erased independently of other blocks in the array. Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Mitsubishi 16M Flash Memory Type name M 5 M 29G T 160B WG Operating Voltage : 29G : 2.7 - 3.6V Standard / BGO Type 29W : 1.65 - 2.2V Standard / BGO Type Boot Block : T : Top Boot B : Bottom Boot Density/Write Protect/ Word Organizetion: 160B : 16M WP1#, x8/x16 161B : 16M WP1# & WP2#, x16 5 Package : VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout) WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY MEMORY ORGANIZATION x16 ( Wordmode) x16 ( Wordmode) F0000H-F7FFFH 32Kword MAIN BLOCK 34 F8000H-FBFFFH 16Kword PARAMETER BLOCK 34 E8000H-EFFFFH 32Kword MAIN BLOCK 33 F4000H-F7FFFH 16Kword PARAMETER BLOCK 33 E0000H-E7FFFH 32Kword MAIN BLOCK 32 F0000H-F3FFFH 16Kword PARAMETER BLOCK 32 D8000H-DFFFFH 32Kword MAIN BLOCK 31 EC000H-EFFFFH 16Kword PARAMETER BLOCK 31 D0000H-D7FFFH 32Kword MAIN BLOCK 30 E8000H-EBFFFH 16Kword PARAMETER BLOCK 30 C8000H-CFFFFH 32Kword MAIN BLOCK 29 E4000H-E7FFFH 16Kword PARAMETER BLOCK 29 C0000H-C7FFFH 32Kword MAIN BLOCK 28 E0000H-E3FFFH 16Kword PARAMETER BLOCK 28 B8000H-BFFFFH 32Kword MAIN BLOCK 27 D8000H-DFFFFH 32Kword MAIN BLOCK 27 B0000H-B7FFFH 32Kword MAIN BLOCK 26 D0000H-D7FFFH 32Kword MAIN BLOCK 26 A8000H-AFFFFH 32Kword MAIN BLOCK 25 C8000H-CFFFFH 32Kword MAIN BLOCK 25 A0000H-A7FFFH 32Kword MAIN BLOCK 24 C0000H-C7FFFH 32Kword MAIN BLOCK 24 98000H-9FFFFH 32Kword MAIN BLOCK 23 B8000H-BFFFFH 32Kword MAIN BLOCK 23 90000H-97FFFH 32Kword MAIN BLOCK 22 B0000H-B7FFFH 32Kword MAIN BLOCK 22 88000H-8FFFFH 32Kword MAIN BLOCK 21 A8000H-AFFFFH 32Kword MAIN BLOCK 21 32Kword MAIN BLOCK 20 78000H-7FFFFH 32Kword MAIN BLOCK 19 98000H-9FFFFH 32Kword MAIN BLOCK 19 70000H-77FFFH 32Kword MAIN BLOCK 18 90000H-97FFFH 32Kword MAIN BLOCK 18 68000H-6FFFFH 32Kword MAIN BLOCK 17 88000H-8FFFFH 32Kword MAIN BLOCK 17 60000H-67FFFH 32Kword MAIN BLOCK 16 80000H-87FFFH 32Kword MAIN BLOCK 16 58000H-5FFFFH 32Kword MAIN BLOCK 15 78000H-7FFFFH 32Kword MAIN BLOCK 15 50000H-57FFFH 32Kword MAIN BLOCK 14 70000H-77FFFH 32Kword MAIN BLOCK 14 48000H-4FFFFH 32Kword MAIN BLOCK 13 68000H-6FFFFH 32Kword MAIN BLOCK 13 40000H-47FFFH 32Kword MAIN BLOCK 12 60000H-67FFFH 32Kword MAIN BLOCK 12 38000H-3FFFFH 32Kword MAIN BLOCK 11 58000H-5FFFFH 32Kword MAIN BLOCK 11 30000H-37FFFH 32Kword MAIN BLOCK 10 50000H-57FFFH 32Kword MAIN BLOCK 10 28000H-2FFFFH 32Kword MAIN BLOCK 9 48000H-4FFFFH 32Kword MAIN BLOCK 9 20000H-27FFFH 32Kword MAIN BLOCK 8 40000H-47FFFH 32Kword MAIN BLOCK 8 1C000H-1FFFFH 16Kword PARAMETER BLOCK 7 38000H-3FFFFH 32Kword MAIN BLOCK 7 18000H-1BFFFH 16Kword PARAMETER BLOCK 6 30000H-37FFFH 32Kword MAIN BLOCK 6 14000H-17FFFH 16Kword PARAMETER BLOCK 5 28000H-2FFFFH 32Kword MAIN BLOCK 5 10000H-13FFFH 16Kword PARAMETER BLOCK 4 20000H-27FFFH 32Kword MAIN BLOCK 4 0C000H-0FFFFH 16Kword PARAMETER BLOCK 3 18000H-1FFFFH 32Kword MAIN BLOCK 3 08000H-0BFFFH 16Kword PARAMETER BLOCK 2 10000H-17FFFH 32Kword MAIN BLOCK 2 04000H-07FFFH 16Kword PARAMETER BLOCK 1 08000H-0FFFFH 32Kword MAIN BLOCK 1 00000H-07FFFH 32Kword MAIN BLOCK 0 16Kword BOOT BLOCK 0 A19-A0 (M5M29GT161BWG) A19-A0 (M5M29GB161BWG) M5M29GB161BWG Memory Map M5M29GT161BWG Memory Map Sep.1999. Rev4.0 BANK(II) 32Kword MAIN BLOCK 20 A0000H-A7FFFH BANK(I) 80000H-87FFFH BANK(I) FC000H-FFFFFH BANK(II) 32Kword MAIN BLOCK 35 00000H-03FFFH 6 16Kword BOOT BLOCK 35 F8000H-FFFFFH MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BUS OPERATIONS Bus Operations for Word-Wide Mode (M5M29GB/T161BWG) Pins CE# Array Status Register Lock Bit Status Identifier Code Output disable Stand by Program Write Erase Others Deep Power Down VIL VIL VIL VIL VIL VIH VIL VIL VIL X Mode Read OE# VIL VIL VIL VIL VIH X 1) VIH VIH VIH X WE# RP# DQ0-15 VIH VIH VIH VIH VIH X VIL VIL VIL X VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z 1) X can be VIH or VIL for control pins. 7 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SOFTWARE COMMAND DEFINITION Command List Read Array Device Identifier Read Status Register Clear Status Register Clear Page Buffer Word Program 5) Page Program 7) Single Data Load to Page Buffer 5) Page Buffer to Flash 5) Block Erase / Confirm Suspend Resume Read Lock Bit Status Lock Bit Program / Confirm Erase All Unlocked Blocks Data Data Mode Address (DQ15-0) 1) Write Write Write Write Write Write Write Write Write Write Write Write Write X X Bank3) X X Bank(I) 5) Bank Bank(I) 5) Bank(I) 5) Bank Bank Bank X Bank X FFH 90H 70H 50H 55H 40H 41H 74H 0EH 20H B0H D0H 71H 77H A7H Write Write 3rd ~129th bus cycles (M5M29GB/T161BWG) 2nd bus cycle 1st bus cycle Command Mode Address (DQ15-0) Read IA 2) Read Bank ID 2) SRD4) Write Write Write Write Write Write X WA 6) WA0 7) WA WA 8) BA 9) D0H 1) WD 6) WD0 7) WD D0H 1) D0H 1) Read Write Write BA BA X Data Mode Address (DQ15-0) Write WAn 7) WDn 7) DQ6 10) D0H 1) D0H 1) 1) Upper byte data (DQ8-DQ15) is ignored. 2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code 3) Bank = Bank Address (Bank(I) or Bank(II)). A19-A17. 4) SRD = Status Register Data 5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I). 6) WA = Write Address,WD = Write Data 7) WA0,WAn=Write Address, WD0,WDn=Write Data. : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit). and also A19-A7(Block Address, Page Address) must be valid. 8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid. 9) BA = Block Address : Bank1: A19-A14 Bank2: A19-A15 10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked. 8 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY BLOCK LOCKING 161BWG Lock Bit WP2# (Internally) RP# WP1# VIL X X VIL VIH VIH VIL VIH VIL VIH VIL VIH X 0 1 X X 0 1 Write Protection Provided BANK(I) BANK(II) Lock Bit Boot Parameter Data Locked Locked Locked Locked Locked Locked Locked Locked Locked Locked Unlocked Unlocked Unlocked Unlocked Unlocked Unlocked Locked Locked Locked Locked Locked Locked Locked Locked Locked Locked Locked Unlocked Note Deep Power Down Mode All Blocks Unlocked All Blocks Locked Only Parameter Block is Unlocked 1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H). WP1# & WP2# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0). 2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and 00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode to array read mode. STATUS REGISTER Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Reserved Definition "1" Ready Suspended Error Error Error - "0" Busy Operation in Progress / Completed Successful Successful Successful - *DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive. 9 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY DEVICE IDENTIFIER CODE Pins A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Hex. Data Manufacturer Code VIL 0 0 0 1 1 1 0 0 1CH Device Code (-T161BWG) VIH 1 0 1 0 0 0 0 0 A0H Device Code (-B161BWG) VIH 1 0 1 0 0 0 0 1 A1H Code The upper data(D15-8) is "0". ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI1 Parameter Vcc voltage All input or output voltage except Vcc,A9,RP# 1) Conditions Min Max Unit With respect to Ground -0.2 -0.6 4.6 4.6 V V Ta Ambient temperature -40 85 °C Tbs Temperature under bias -50 95 °C Tstg I OUT Storage temperature Output short circuit current -65 125 100 °C mA 1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns. CAPACITANCE Symbol CIN COUT Parameter Test conditions Input capacitance (Address, Control Pins) Output capacitance Min Limits Typ Ta = 25°C, f = 1MHz, Vin = Vout = 0V Max 8 12 Unit pF pF DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85°C, Vcc = 2.7V ~ 3.6V, unless otherwise noted) Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 Parameter Input leakage current Output leakage current VCC standby current VCC deep powerdown current ICC1 VCC read current for Word or Byte ICC2 VCC Write current for Word or Byte ICC3 ICC4 ICC5 VIL VIH VOL VOH1 VOH2 VLKO VCC program current VCC erase current VCC suspend current Input low voltage Input high voltage Output low voltage Output high voltage Low VCC Lock-Out voltage 2) Test conditions Min 0V≤VIN≤VCC 0V≤VOUT≤VCC VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=GND or VCC, CE# = RP# = WP# = VCC±0.3V VCC = 3.6V, VIN=VIL/VIH, RP# = VIL VCC = 3.6V, VIN=GND or VCC, RP# =GND±0.3V VCC = 3.6V, VIN=VIL/VIH, CE# = VIL, 5MHz RP#=OE#=VIH, IOUT = 0mA 1MHz VCC = 3.6V,VIN=VIL/VIH, CE# =WE#= VIL, RP#=OE#=VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH – 0.5 2.0 IOL = 4.0mA IOH = –2.0mA IOH = –100µA Limits Typ1) 50 0.1 5 µA 5 15 µA 0.1 8 2 5 15 4 µA µA µA µA mA 15 mA 35 35 200 0.8 mA mA µA V V V V V V Vcc+0.5 0.45 0.85Vcc Vcc–0.4 1.5 Unit Max ±1.0 ±10 200 2.2 All currents are in RMS unless otherwise noted. 1) Typical values at Vcc=3.3V, Ta=25°C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents may occur. 10 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V) Read-Only Mode Limits Symbol Vcc=2.7-3.6V Parameter tRC tAVAV ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tOH tOH tPS tPHEL Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z Min 90 Typ RP# recovery to CE# low Max 25 ns ns ns ns ns ns ns ns 150 ns 90 90 30 0 25 0 RP# low to output high-Z Output hold from CE#, OE#, addresses Unit 90ns 0 ns 150 ns Timing measurements are made under AC waveforms for read operations. AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V) Write Mode (WE# control) Symbol tWC tAS tAH tDS tDH tOEH Limits Vcc=2.7-3.6V Parameter tRE tCS tCH tWP tWPH tGHWL tBLS tBLH tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from WE# high Latency between Read and Write FFH or 71H Chip enable set-up time Chip enable hold time tWLWH tWHWL tGHWL tPHHWH tQVPH tDAP tDAE tWHRL tPS Write pulse width Write pulse width high OE# hold to WE# Low Block Lock set-up to write enable high Block Lockhold from valid SRD Duration of auto-program operation tWHRH1 tWHRH2 Duration of auto-block erase operation tWHRL Write enable high to F-RY/BY# low tPHWL RP# high recovery to write enable low Min 90 50 0 50 0 10 30 0 0 90ns Typ Unit Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns 60 30 0 90 0 150 4 80 40 600 90 ms ms ns ns Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25°C 11 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85°C, Vcc = 2.7V ~ 3.6V) Write Mode (F-CE# control) Parameter Symbol tWC tAS tAH tDS tDH tOEH tRE tWS tWH tCEP tCEPH tGHEL tBLS tBLH tAVAV tAVWH tEHAX tDVWH tEHDX tEHGL tWLEL tEHWH tELEH tEHEL tGHEL tPHHEH tQVPH Write cycle time Address set-up time Address hold time Data set-up time Data hold time OE# hold from CE# high Latency between Read and Write FFH or 71H Write enable set-up time Write enable hold time CE# pulse width CE# pulse width high OE# hold to CE# Low Block Lock set-up to chip enable high Block Lockhold from valid SRD Duration of auto-program operation tDAP tEHRH1 tDAE tEHRH2 Duration of auto-block erase operation tEHRL tEHRL CE# high to F-RY/BY# low tPS tPHWL RP# high recovery to write enable low Min 90 50 0 50 0 Limits Vcc=2.7-3.6V 90ns Typ Unit Max ns ns ns ns ns ns ns 10 30 0 0 60 30 90 90 0 ns ns ns ns ns ns ns 4 80 40 600 90 ms ms ns ns 150 Read timing parameters during command write operation mode are the same as during read-only operation mode. Typical values at Vcc=3.3V, Ta=25°C Erase and Program Performance Min Parameter Block Erase Time Main Block Write Time (Page Mode) Page Write Time Typ Max Unit 40 1.0 4 600 1.8 80 ms sec ms Typ Max Unit 15 15 µs µs Max Unit Program Suspend Latency / Erase Suspend Time Parameter Min Program Suspend Latency Erase Suspend Time Please see page 19. Vcc Power Up / Down Timing Symbol tVCS Parameter RP# =VIH set-up time from Vccmin Min 2 Typ µs Please see page 12. During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down. By holding RP# VIL, the contents of memory is protected during Vcc power up/down. During power up, RP# must be held VIL for min.2µs from the time Vcc reaches Vccmin. During power down, RP# must be held VIL until Vcc reaches GND. RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation. 12 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Vcc POWER UP / DOWN TIMING Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit 3.3V VCC GND tVCS VIH RP# VIL VIH CE# VIL tPS tPS VIH WE# VIL AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS TEST CONDITIONS FOR AC CHARACTERISTICS VIH ADDRESSES ADDRESS VALID VIL tRC VIH CE# Input voltage : VIL = 0V, VIH = 3.0V Input rise and fall times : ≤5ns Reference voltage at timing measurement : 1.5V ta (AD) VIL tDF(CE) ta (CE) VIH OE# Output load : 1TTL gate +CL(30pF) VIL tDF(OE) tOEH or VIH WE# ta (OE) VIL tOH tOLZ VOH DATA tCLZ HIGH-Z VOL OUTPUT VALID tPS 1N914 tPHZ VIH RP# 1.3V HIGH-Z 3.3kΩ DUT VIL CL AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION VIH ADDRESSES ADDRESS VALID VIL CE# tRC VIH ta (AD) VIL OE# ta (CE) VIL WE# tRE tDF(OE) VIH ta (OE) VIL DATA VOH HIGH-Z FFH or 71H Valid VOL tPS RP# tDF(CE) VIH VIH tOH tOLZ tCLZ OUTPUT VALID HIGH-Z tPHZ VIL In the case of use CE# is Low fixed, it is allowed to define a timming specification of tRE from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE). (This is only for FFH,71H program and read) 13 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control) The other bank address VIH A19~A7 VALID VALID 00H VALID PROGRAM READ STATUS WRITE READ REGISTER ARRAY COMMAND ADDRESS VALID BANK ADDRESS VALID VIL A6~A0 VIH VIL tWC CE# tCS OE# ta(CE) ta(CE) tCH ta(OE) tWPH VIH tWP VIH tDAP tDH tDS 41H tOEH tGHWL ta(OE) tOEH VIL DATA 7FH VIH VIL WE# tAH tAS VIH VIL 01H~7EH DOUT DIN DIN SRD DIN FFH VIL tPS RP# VIH VIL WP1#, WP2# tBLH tBLS VIH VIL AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control) The other bank address VIH A19~A7 A6~A0 VALID VALID 00H VALID tAS VIH VIL tCEPH 01H~7EH 7FH ta(CE) ta(OE) ta(OE) tCEP tWS tOEH tWH tOEH tGHEL tDAP VIH VIL DATA BANK ADDRESS VALID tAH ta(CE) VIH VIL WE# ADDRESS VALID VIH tWC OE# READ STATUS WRITE READ REGISTER ARRAY COMMAND VIL VIL CE# PROGRAM tDH tDS VIH 41H DIN DOUT DIN DIN SRD FFH VIL tPS RP# VIH VIL WP1#, WP2# 14 VIH tBLS tBLH VIL Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I)) PROGRAM VIH ADDRESS VALID ADDR VIL CE# tCS tAH tCH tWP VIH VIL WE# tAS WRITE READ ARRAY COMMAND BANK(I) ADDRESS VALID ta(CE) VIH VIL OE# tWC READ STATUS REGISTER ta(OE) tOEH tWPH VIH VIL tDS VIH 40H DATA DIN SRD FFH VIL VIH RST# tDH tPS tDAP VIL tBLS tBLH WP1#, VIH WP2# VIL AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (CE# control) PROGRAM VIH ADDRESS VALID ADDR VIL CE# tWC tAS (to only BANK(I)) READ STATUS REGISTER WRITE READ ARRAY COMMAND BANK(I) ADDRESS VALID tAH ta(CE) VIH VIL OE# VIL WE# ta(OE) VIH tCEP tWS tOEH tWH VIH VIL tDS VIH 40H DATA DIN SRD FFH VIL VIH tDH tPS RP# VIL tDAP tBLS tBLH WP1#, VIH WP2# VIL 15 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR ERASE OPERATIONS (WE# control) ERASE VIH ADDRESSES tWC tAH tAS ta(CE) VIH VIL tCS tCH ta(OE) VIH OE# VIL tOEH tWPH tDAE VIH WE# VIL tWP tDH tDS VIH DATA WRITE READ ARRAY COMMAND BANK ADDRESS VALID ADDRESS VALID VIL CE# READ STATUS REGISTER 20H SRD D0H FFH VIL tPS RP# VIH tBLS VIL WP1#, WP2# tBLH VIH VIL AC WAVEFORMS FOR ERASE OPERATIONS (CE# control) ERASE VIH ADDRESSES ADDRESS VALID VIL tWC tAH tAS ta(CE) VIL tCEPH tCEP ta(OE) VIH OE# tOEH VIL tWS VIL tDH tDS VIH DATA tDAE tWH VIH WE# WRITE READ ARRAY COMMAND BANK ADDRESS VALID VIH CE# READ STATUS REGISTER 20H D0H SRD FFH VIL tPS RP# VIH WP1#, WP2# VIH VIL 16 tBLS tBLH VIL Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control) Change Bank Address ARRAY READ FROM THE OTHER BANK WITH BGO PROGRAM DATA TO ONE BANK VIH ADDRESS VALID VIH VIL tWC tAS 7FH VALID VALID ta(CE) ~ ~ ~ ~ tCS tCH VIH ta(OE) tOEH tWP tWPH VIL VIH ~ ~ WE# VALID tAH VIH VIL OE# 01H~7EH 00H A6~A0 CE# VALID VIL ~ ~ ~ ~ A19~A7 VIL 41H ~ ~ tDS VIH DATA DIN DIN DIN SRD DOUT DOUT VIL tDH AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control) Change Bank Address PROGRAM DATA TO ONE BANK ARRAY READ FROM THE OTHER BANK WITH BGO VIH ADDRESS VALID A19~A7 VALID VALID VALID VALID ~ ~ ~ ~ VIL VIH CE# tWC VIH VIL ta(CE) tAH tCEPH ta(OE) tCEP tOEH tWS tCH VIH VIL DATA 7FH ~ ~ WE# tAS VIH VIL OE# 01H~7EH 00H VIL ~ ~ A6~A0 tDS VIH 41H DIN DIN DIN SRD DOUT DOUT VIL tDH 17 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control) Change Bank Address PROGRAM DATA TO BANK(I) VIH READ STATUS REGISTER ADDRESS VALID A19~A7 ARRAY READ FROM BANK(II) WITH BGO VALID VALID VALID VALID VIL VIH A6~A0 CE# VALID VIL tAS tCS tCH VIH ta(OE) tOEH tWP tWPH VIL WE# ta(CE) VIH VIL OE# tWC tAH VIH VIL tDS VIH 40H DATA DIN SRD DOUT DOUT VIL tDH AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (CE# control) PROGRAM DATA TO BANK(I) VIH READ STATUS REGISTER ADDRESS VALID A19~A7 Change Bank Address ARRAY READ FROM BANK(II) WITH BGO VALID VALID VALID VALID VIL VIH VALID A6~A0 VIL CE# tWC VIH VIL WE# ta(CE) tCEPH VIL OE# tAS VIH tCEP tWS ta(OE) tOEH tCH VIH VIL tDS VIH 40H DATA DIN SRD DOUT DOUT VIL tDH 18 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control) Change Bank Address READ STATUS REGISTER BLOCK ERASE IN ONE BANK VIH ADDRESSES ADDRESS VALID VIL tWC CE# tAH tAS tCS ta(OE) tOEH tWP tWPH VIH VALID ta(CE) tCH VIH VIL WE# VALID VIH VIL OE# ARRAY READ FROM THE OTHER BANK WITH BGO VIL tDS VIH DATA 20H D0H SRD DOUT DOUT VIL tDH AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (CE# control) Change Bank Address BLOCK ERASE IN ONE BANK VIH ADDRESSES ADDRESS VALID VIL CE# tWC VIH VIL WE# tAS tAH VIH tCEPH VIL OE# READ DATA FROM THE OTHER BANK WITH BGO READ STATUS REGISTER tCEP VALID VALID ta(CE) ta(OE) tOEH tWS tCH VIH VIL tDS VIH DATA 20H SRD D0H DOUT DOUT VIL tDH 19 Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY AC WAVEFORMS FOR SUSPEND OPERATION (WE# control) READ STATUS REGISTER VIH ADDRESSES VIL BANK ADDRESS VALID tAS tAH VIH CE# BANK ADDRESS VALID ta(CE) VIL tCS tCH ta(OE) VIH OE# tOEH VIL Program Suspend Latency VIH WE# VIL tWP S.R.6,7=1 VIH DATA RP# VIL VIH tBLS VIL WP1#, WP2# VALID SRD B0H tBLH VIH VIL AC WAVEFORMS FOR SUSPEND OPERATION (CE# control) READ STATUS REGISTER VIH ADDRESSES VIL BANK ADDRESS VALID tAS tAH VIH CE# BANK ADDRESS VALID ta(CE) tCEP VIL ta(OE) VIH OE# VIH WE# tOEH VIL Program Suspend Latency tWS tWH VIL S.R.6,7=1 VIH DATA RP# B0H VIH VIL WP1#, WP2# 20 VALID SRD VIL tBLS tBLH VIH VIL Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY FULL STATUS CHECK PROCEDURE LOCK BIT PROGRAM FLOW CHART STATUS REGISTER READ SR.4 =1 and SR.5 =1 ? NO START WRITE 77H COMMAND SEQUENCE ERROR YES WRITE D0H BLOCK ADDRESS SR.5 = 0 ? BLOCK ERASE ERROR NO SR.7 = 1 ? NO YES YES PROGRAM ERROR (PAGE, LOCK BIT) SR.4 = 0 ? NO LOCK BIT PROGRAM FAILED SR.4 = 0 ? NO YES YES PROGRAM ERROR (BLOCK) SR.3 = 0 ? NO LOCK BIT PROGRAM SUCCESSFUL YES SUCCESSFUL (BLOCK ERASE, PROGRAM) BYTE PROGRAM FLOW CHART PAGE PROGRAM FLOW CHART START START WRITE 40H WRITE 41H n=0 WRITE ADDRESS , DATA SR.7 = 1 ? n = n+1 WRITE ADDRESS n, DATA n STATUS REGISTER READ NO WRITE B0H ? NO n = FFH ? or n = 7FH ? NO YES YES FULL STATUS CHECK IF DESIRED PAGE PROGRAM COMPLETED YES STATUS REGISTER READ SUSPEND LOOP WRITE D0H YES SR.7 = 1 ? NO * Word program is admitted to only BANK(I). YES FULL STATUS CHECK IF DESIRED PAGE PROGRAM COMPLETED 21 WRITE B0H ? NO YES SUSPEND LOOP WRITE D0H YES Sep.1999. Rev4.0 MITSUBISHI LSIs M5M29GB/T161BWG 16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY SUSPEND / RESUME FLOW CHART CLEAR PAGE BUFFER START START SUSPEND WRITE B0H WRITE 55H STATUS REGISTER READ WRITE D0H SR.7 = 1? NO PAGE BUFFER CLEAR COMPLETED YES SR.6 =1? PROGRAM / ERASE COMPLETED NO SINGLE DATA LOAD TO PAGE BUFFER YES WRITE FFH START WRITE 74H READ ARRAY DATA WRITE ADDRESS , DATA DONE READING ? NO YES DONE LOADING? NO RESUME WRITE D0H OPERATION RESUMED YES SINGLE DATA LOAD TO PAGE BUFFER COMPLETED * The bank address is required when writing this command. Also, there is no need to suspend the erase or program operation when reading data from the other bank. Please use BGO function. BLOCK ERASE FLOW CHART PAGE BUFFER TO FLASH START START WRITE 20H WRITE 0EH WRITE D0H BLOCK ADDRESS WRITE D0H PAGE ADDRESS STATUS REGISTER READ STATUS REGISTER READ NO NO SR.7 = 1 ? WRITE B0H ? NO YES FULL STATUS CHECK IF DESIRED SUSPEND LOOP SR.7 = 1 ? YES FULL STATUS CHECK IF DESIRED WRITE D0H PAGE BUFFER TO FLASH COMPLETED 22 YES BLOCK ERASE COMPLETED WRITE B0H ? NO YES SUSPEND LOOP WRITE D0H YES Sep.1999. Rev4.0 Clear Status Register Read Status Register 50H 70H 70H 90H 71H 70H Read Device Identifier 90H Read Lock Status 71H 71H 90H FFH FFH FFH Read Array Setup State Clear Page Buffer Setup D0H 55H WD 0EH 74H Single Data Load to Page Buffer Setup Page Buffer to Flash Setup 41H Page Program Setup D0H OTHER 40H Internal State Lock Bit Program Setup Byte Program Setup WDi i=0-127 WD 20H 77H D0H D0H Suspend State Read Array (From The Other Bank) Change Bank Address 70H FFH Read Array 70H MITSUBISHI LSIs Sep.1999. Rev4.0 Read State with BGO Read Status Register 16,777,216-BIT (1048,576-WORD BY16-BIT) B0H M5M29GB/T161BWG B0H OTHER CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY Read Status Register D0H Erase All Unlocked Blocks Setup OTHER D0H Erase & Verify Read Status Register Change Bank Address Block Erase Setup D0H OTHER Program & Verify Ready A7H OPERATION STATUS and EFFECTIVE COMMAND 23 Read/Standby State