MITSUBISHI M6MGB160S2BVP

MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
DESCRIPTION
FEATURES
The MITSUBISHI M6MGB/T160S2BVP is a Stacked Multi
• Access time
Chip Package (S-MCP) that contents 16M-bits flash memory
Flash Memory
90ns (Max.)
and 2M-bits Static RAM in a 48-pin TSOP (TYPE-I).
SRAM
85ns (Max.)
• Supply voltage
Vcc=2.7 ~ 3.6V
16M-bits Flash memory is a 2097152 bytes /1048576 words,
• Ambient temperature
3.3V-only, and high performance non-volatile memory
W version
Ta=-20 ~ 85°C
fabricated by CMOS technology for the peripheral circuit
• Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch
and DINOR(DIvided bit-line NOR) architecture for the
memory cell.
2M-bits SRAM is a 262144 bytes / 131072 words
APPLICATION
unsynchronous SRAM fabricated by silicon-gate CMOS
technology.
Mobile communication products
M6MGB/T160S2BVP is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .
10.0 mm
PIN CONFIGURATION (TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
A19
S-CE
WE#
F-RP#
F-WP#
S-VCC
F-RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
F-VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
F-CE#
A0
14.0 mm
F-VCC
S-VCC
GND
A-1-A16
A17-A19
DQ0-DQ15
F-CE#
S-CE
OE#
WE#
F-WP#
F-RP#
F-RY/BY#
BYTE#
1
:Vcc for Flash
NC:Non Connection
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready /Busy
:Flash/SRAM Byte Enable
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
BLOCK DIAGRAM
16Mb Flash Memory
128 WORD PAGE BUFFER
Main Block
Bank(II)
32KW
F-VCC(3.3V)
28
X-DECODER
GND (0V)
Main Block
Parameter Block7
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
Parameter Block1
Boot Block
Bank(I)
ADDRESS
INPUTS
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
32KW
16KW
16KW
16KW
16KW
16KW
16KW
16KW
16KW
Y-GATE / SENSE AMP.
Y-DECODER
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
READY/BUSY OUTPUT
F-CE#
OE#
WE#
F-WP#
F-RP#
BYTE#
CUI
WSM
INPUT/OUTPUT
BUFFERS
F-RY/BY#
DQ15/A-1 DQ14DQ13 DQ12
2Mb SRAM
S-CE
BYTE#
WE#
OE#
2
SENSE AMP.
OUTPUT BUFFER
OUTPUT BUFFER
DATAINPUT
BUFFER
CLOCK
GENERATOR
DATAINPUT
BUFFER
A16
262144 WORD x
8 BITS
or
131072 WORD x
16 BITS
SENSE AMP.
A15
ROW DECODER
A0
DATA INPUTS/OUTPUTS
ADDRESS INPUT BUFFER
A-1
DQ3DQ2 DQ1DQ0
DQ 0
DQ 7
DQ 8
DQ15/A-1
S-VCC
GND
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
1. Flash Memory
DESCRIPTION
The Flash Memory of M6MGB/T160S2BVP is 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with alternating
BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank
while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and
personal computing, and communication products. The Flash Memory of M6MGB/T160S2BVP is fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells.
FEATURES
Organization
.................................1048,576 word x 16bit
.................................2,097,152 word x 8 bit
............................. VCC = 2.7~3.6V
Supply voltage ................................
Access time
.............................. 90ns (Max.)
Power Dissipation
................................. 54 mW (Max. at 5MHz)
Read
(After Automatic Power saving) .......... 0.33mW (typ.)
Program/Erase .................................126 mW (Max.)
................................. 0.33mW (typ.)
Standby
Deep power down mode ....................... 0.33mW (typ.)
Auto program for Bank(I)
................................. 4ms (typ.)
Program Time
Program Unit
.........................1word/1byte
(Byte Program)
(Page Program) ......................... 128word/256byte
Auto program for Bank(II)
................................. 4ms (typ.)
Program Time
................................. 128word/256byte
Program Unit
Auto Erase
................................. 40 ms (typ.)
Erase time
Erase Unit
Bank(I) Boot Block ..................... 16Kword/32Kbyte x 1
..............
Parameter Block
16Kword/32Kbyte x 7
......................
Bank(II) Main Block
32Kword/64Kbyte x 28
Program/Erase cycles
3
Boot Block
M6MGB160S2BVP ........................ Bottom Boot
M6MGT160S2BVP ........................ Top Boot
Other Functions
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)
.........................................
100Kcycles
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
FUNCTION
The Flash Memory of M6MGB/T160S2BVP includes on-chip
program/erase control circuitry. The Write State Machine (WSM)
controls block erase and byte/page program operations.
Operational modes are selected by the commands written to the
Command User Interface (CUI). The Status Register indicates the
status of the WSM and when the WSM successfully completes the
desired program or block erase operation.
A Deep Powerdown mode is enabled when the F-RP# pin is at
GND, minimizing power consumption.
Read
The Flash Memory of M6MGB/T160S2BVP has three read modes,
which accesses to the memory array, the Device Identifier and the
Status Register. The appropriate read command are required to
be written to the CUI. Upon initial device powerup or after exit
from deep powerdown, the Flash Memory automatically resets to
read array mode. In the read array mode, low level input to F-CE#
and OE#, high level input to WE# and F-RP#, and address signals
to the address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode)
output the data of the addressed location to the data input/output
(D7-D0:Byte Mode, D15-D0:Word Mode).
Deep Power-Down
When F-RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, F-RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or F-CE# isn't
changed more than 200ns after the last alternation. The
power consumption becomes the same as the stand-by
mode. While in this mode, the output data is latched and can
be read out. New data is read out correctly when addresses
are changed.
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while F-CE# is at low level and OE# is
at high level. Address and data are latched on the earlier rising
edge of WE# and F-CE#. Standard micro-processor write timings
are used.
Alternating Background Operation (BGO)
The Flash Memory of M6MGB/T160S2BVP allows to read array
from one bank while the other bank operates in software
command write cycling or the erasing / programming operation in
the background. Read array operation with the other bank in BGO
is performed by changing the bank address without any additional
command. When the bank address points the bank in software
command write cycling or the erasing / programming operation,
the data is read out from the status register. The access time with
BGO is the same as the normal read operation.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When F-CE# is at VIH, the device is in the standby mode and
its power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
4
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.
Read Device Identifier Command (90H)
It can normally read device identifier codes when Read Device
Identifier Code Command(90H) is written to the command latch.
Following the command write, the manufacturer code and the
device code can be read from address 0000H and 0001H,
respectively.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of OE# or F-CE#. So F-CE# or OE# must be toggled every
status read.
Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.
C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 256byte/128word can be loaded to the
page buffer by this two-command sequence. On the other hand,
all of the loaded data to the page buffer is programed
simultaneously by writing Page Buffer to Flash command of 0EH
followed by the confirm command of D0H. After completion of
programing the data on the page buffer is cleared automatically.
This command is valid for only Bank(I) alike Word/Byte Program.
Clear Page Buffer Command (55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.
DATA PROTECTION
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Program Commands
A)Word/Byte Program (40H)
Word/Byte program is executed by a two-command sequence.
The Word/Byte Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word/Byte Program
Command is Valid for only Bank(I).
B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words/256bytes of data. Writing of 41H initiates the page
program operation for the Data area. From 2nd cycle to 257th
cycle (Byte Mode)129th cycle (Word Mode), write data must be
serially inputted. Address A6-A0,A-1 (Byte Mode) / A6-A0 (Word
Mode) have to be incremented from 00H to 7FH/FFH. After
completion of data loading, the WSM controls the program pulse
application and verify operation.
5
The Flash Memory of M6MGB/T160S2BVP provides selectable
block locking of memory blocks. Each block has an associated
nonvolatile lock-bit which determines the lock status of the block.
In addition, the Flash Memory has a master Write Protect pin
(F-WP#) which prevents any modifications to memory blocks
whose lock-bits are set to "0", when F-WP# is low. When F-WP#
is high, all blocks can be programmed or erased regardless of
the state of the lock-bits, and the lock-bits are cleared to "1" by
erase. See the BLOCK LOCKING table on P.9 for details.
Power Supply Voltage
When the power supply voltage (F-VCC) is less than VLKO, Low
V CC Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of VLKO, see P.10.
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time F-Vcc reaches
F-Vccmin (2.7V).
During power up, F-RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
MEMORY ORGANIZATION
The Flash Memory of M6MGB/T160S2BVP has one 32Kbyte boot
block, seven 32Kbyte parameter blocks, for Bank(I) and
twenty-eight 64Kbyte main blocks for Bank(II). A block is erased
independently of other blocks in the array.
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
MEMORY ORGANIZATION
x8 ( Bytemode)
x16 ( Wordmode)
x16 ( Wordmode)
1F0000H-1FFFFFH
F8000H-FFFFFH
32Kword MAIN BLOCK 35
1F8000H-1FFFFFH
FC000H-FFFFFH
1E0000H-1EFFFFH
F0000H-F7FFFH
32Kword MAIN BLOCK 34
1F0000H-1F7FFFH
F8000H-FBFFFH 16Kword PARAMETER BLOCK 34
1D0000H-1DFFFFH
E8000H-EFFFFH
32Kword MAIN BLOCK 33
1E8000H-1EFFFFH
F4000H-F7FFFH 16Kword PARAMETER BLOCK 33
1C0000H-1CFFFFH
E0000H-E7FFFH
32Kword MAIN BLOCK 32
1E0000H-1E7FFFH
F0000H-F3FFFH 16Kword PARAMETER BLOCK 32
1B0000H-1BFFFFH
D8000H-DFFFFH
32Kword MAIN BLOCK 31
1D8000H-1DFFFFH
EC000H-EFFFFH 16Kword PARAMETER BLOCK 31
1A0000H-1AFFFFH
D0000H-D7FFFH
32Kword MAIN BLOCK 30
1D0000H-1D7FFFH
E8000H-EBFFFH 16Kword PARAMETER BLOCK 30
190000H-19FFFFH
C8000H-CFFFFH
32Kword MAIN BLOCK 29
1C8000H-1CFFFFH
E4000H-E7FFFH 16Kword PARAMETER BLOCK 29
180000H-18FFFFH
C0000H-C7FFFH
32Kword MAIN BLOCK 28
1C0000H-1C7FFFH
E0000H-E3FFFH 16Kword PARAMETER BLOCK 28
170000H-17FFFFH
B8000H-BFFFFH
32Kword MAIN BLOCK 27
1B0000H-1BFFFFH
D8000H-DFFFFH
32Kword MAIN BLOCK 27
160000H-16FFFFH
B0000H-B7FFFH
32Kword MAIN BLOCK 26
1A0000H-1AFFFFH
D0000H-D7FFFH
32Kword MAIN BLOCK 26
150000H-15FFFFH
A8000H-AFFFFH
32Kword MAIN BLOCK 25
190000H-19FFFFH
C8000H-CFFFFH
32Kword MAIN BLOCK 25
140000H-14FFFFH
A0000H-A7FFFH
32Kword MAIN BLOCK 24
180000H-18FFFFH
C0000H-C7FFFH
32Kword MAIN BLOCK 24
130000H-13FFFFH
98000H-9FFFFH
32Kword MAIN BLOCK 23
170000H-17FFFFH
B8000H-BFFFFH
32Kword MAIN BLOCK 23
120000H-12FFFFH
90000H-97FFFH
32Kword MAIN BLOCK 22
160000H-16FFFFH
B0000H-B7FFFH
32Kword MAIN BLOCK 22
110000H-1FFFFFH
88000H-8FFFFH
32Kword MAIN BLOCK 21
150000H-15FFFFH
A8000H-AFFFFH
32Kword MAIN BLOCK 21
100000H-10FFFFH
80000H-87FFFH
32Kword MAIN BLOCK 20
140000H-14FFFFH
A0000H-A7FFFH
32Kword MAIN BLOCK 20
F0000H-FFFFFH
78000H-7FFFFH
32Kword MAIN BLOCK 19
130000H-13FFFFH
98000H-9FFFFH
32Kword MAIN BLOCK 19
E0000H-EFFFFH
70000H-77FFFH
32Kword MAIN BLOCK 18
120000H-12FFFFH
90000H-97FFFH
32Kword MAIN BLOCK 18
D0000H-DFFFFH
68000H-6FFFFH
32Kword MAIN BLOCK 17
110000H-11FFFFH
88000H-8FFFFH
32Kword MAIN BLOCK 17
C0000H-CFFFFH
60000H-67FFFH
32Kword MAIN BLOCK 16
100000H-10FFFFH
80000H-87FFFH
32Kword MAIN BLOCK 16
B0000H-BFFFFH
58000H-5FFFFH
32Kword MAIN BLOCK 15
F0000H-FFFFFH
78000H-7FFFFH
32Kword MAIN BLOCK 15
A0000H-AFFFFH
50000H-57FFFH
32Kword MAIN BLOCK 14
E0000H-EFFFFH
70000H-77FFFH
32Kword MAIN BLOCK 14
90000H-9FFFFH
48000H-4FFFFH
32Kword MAIN BLOCK 13
D0000H-DFFFFH
68000H-6FFFFH
32Kword MAIN BLOCK 13
80000H-8FFFFH
40000H-47FFFH
32Kword MAIN BLOCK 12
C0000H-CFFFFH
60000H-67FFFH
32Kword MAIN BLOCK 12
70000H-7FFFFH
38000H-3FFFFH
32Kword MAIN BLOCK 11
B0000H-BFFFFH
58000H-5FFFFH
32Kword MAIN BLOCK 11
60000H-6FFFFH
30000H-37FFFH
32Kword MAIN BLOCK 10
A0000H-AFFFFH
50000H-57FFFH
32Kword MAIN BLOCK 10
50000H-5FFFFH
28000H-2FFFFH
32Kword MAIN BLOCK 9
90000H-9FFFFH
48000H-4FFFFH
32Kword MAIN BLOCK 9
40000H-4FFFFH
20000H-27FFFH
32Kword MAIN BLOCK 8
80000H-8FFFFH
40000H-47FFFH
32Kword MAIN BLOCK 8
38000H-3FFFFH
1C000H-1FFFFH
16Kword PARAMETER BLOCK 7
70000H-7FFFFH
38000H-3FFFFH
32Kword MAIN BLOCK 7
30000H-37FFFH
18000H-1BFFFH
16Kword PARAMETER BLOCK 6
60000H-6FFFFH
30000H-37FFFH
32Kword MAIN BLOCK 6
28000H-2FFFFH
14000H-17FFFH
16Kword PARAMETER BLOCK 5
50000H-5FFFFH
28000H-2FFFFH
32Kword MAIN BLOCK 5
20000H-27FFFH
10000H-13FFFH
16Kword PARAMETER BLOCK 4
40000H-4FFFFH
20000H-27FFFH
32Kword MAIN BLOCK 4
18000H-1FFFFH
0C000H-0FFFFH
16Kword PARAMETER BLOCK 3
30000H-3FFFFH
18000H-1FFFFH
32Kword MAIN BLOCK 3
10000H-17FFFH
08000H-0BFFFH
16Kword PARAMETER BLOCK 2
20000H-2FFFFH
10000H-17FFFH
32Kword MAIN BLOCK 2
08000H-0FFFFH
04000H-07FFFH
16Kword PARAMETER BLOCK 1
10000H-1FFFFH
08000H-0FFFFH
32Kword MAIN BLOCK 1
00000H-07FFFH
00000H-03FFFH
00000H-0FFFFH
00000H-07FFFH
32Kword MAIN BLOCK 0
A19-A-1
(Byte Mode)
Flash Memory of M6MGB160S2BVP
Memory Map
6
BANK(II)
16Kword BOOT BLOCK 0
A19-A0
(Word Mode)
16Kword BOOT BLOCK 35
BANK(I)
BANK(I)
A19-A-1
(Byte Mode)
BANK(II)
x8 ( Bytemode)
A19-A0
(Word Mode)
Flash Memory of M6MGT160S2BVP
Memory Map
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
BUS OPERATIONS
Bus Operations for Word-Wide Mode
Mode
Pins
Array
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
Read
F-CE#
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
OE#
VIL
VIL
VIL
VIL
VIH
X 2)
VIH
VIH
VIH
X
WE#
F-RP#
DQ0-15
F-RY/BY#
VIH
VIH
VIH
VIH
VIH
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
VOH (Hi-Z)
X 1)
X
VOH (Hi-Z)
X
X
X
X
X
VOH (Hi-Z)
WE#
F-RP#
DQ0-7
F-RY/BY#
VIH
VIH
VIH
VIH
VIH
X
VIL
VIL
VIL
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
VOH (Hi-Z)
X 1)
X
VOH (Hi-Z)
X
X
X
X
X
VOH (Hi-Z)
Bus Operations for Byte-Wide Mode
Mode
Pins
Array
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
Read
F-CE#
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
OE#
VIL
VIL
VIL
VIL
VIH
X 2)
VIH
VIH
VIH
X
1) X at F-RY/BY# is VOL or VOH(Hi-Z).
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
7
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
SOFTWARE COMMAND DEFINITION
Command List
Command
Read Array
Device Identifier
Read Status Register
Clear Status Register
Clear Page Buffer
Byte/Word Program 5)
Page Program 7)
Single Data Load to Page Buffer 5)
Page Buffer to Flash 5)
Block Erase / Confirm
Suspend
Resume
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
Data
Data
Mode
Address
(DQ7-0) 1)
(DQ15-0)
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
Bank3)
X
X
Bank(I) 5)
Bank
Bank(I) 5)
Bank(I) 5)
Bank
Bank
Bank
X
Bank
X
FFH
90H
70H
50H
55H
40H
41H
74H
0EH
20H
B0H
D0H
71H
77H
A7H
Write
Write
3rd ~257th bus cycles (Byte Mode)
3rd ~129th bus cycles (Word Mode)
2nd bus cycle
1st bus cycle
Mode
Address
(DQ7-0)
(DQ15-0)
Read
IA 2)
Read
Bank
ID 2)
SRD4)
Write
Write
Write
Write
Write
Write
X
WA 6)
WA0 7)
WA
WA 8)
BA 9)
D0H 1)
WD 6)
WD0 7)
WD
D0H 1)
D0H 1)
Read
Write
Write
BA
BA
X
Data
Mode
Address
(DQ7-0)
(DQ15-0)
Write
WAn 7)
WDn 7)
DQ6 10)
D0H 1)
D0H 1)
1) In the word-wide version(Byte#=H), upper byte data (DQ8-DQ15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code
3) Bank = Bank Address (Bank(I) or Bank(II)) : A19-A17.
4) SRD = Status Register Data
5) Byte/Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address,WD = Write Data
7) WA0,WAn=Write Address, WD0,WDn=Write Data.
Byte Mode : Write Address and Write Data must be provided sequentially from 00H to FFH for A6-A0,A-1. Page size is 256Byte (256byte x 8bit),
and also A19-A7(Block Address, Page Address) must be valid.
Word Mode : Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit).
and also A19-A7(Block Address, Page Address) must be valid.
8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid.
9) BA = Block Address : BA = Block Address : A19-A14(Bank1) A19-A15(Bank2)
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
8
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
BLOCK LOCKING
Lock
Bit
F-RP# F-WP# (Internally)
VIL
X
VIL
VIH
VIH
X
0
1
X
Write Protection Provided
BANK(I)
BANK(II)
Note
Lock Bit
Boot
Parameter
Data
Locked
Locked
Locked
Locked Deep Power Down Mode
Locked
Locked
Locked
Locked
Locked
Locked Unlocked Unlocked
Unlocked Unlocked Unlocked Unlocked All Blocks Unlocked
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).
F-WP# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).
2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and
00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode
to array read mode.
STATUS REGISTER
Symbol
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
(DQ7)
(DQ6)
(DQ5)
(DQ4)
(DQ3)
(DQ2)
(DQ1)
(DQ0)
Status
Write State Machine Status
Suspend Status
Erase Status
Program Status
Block Status after Program
Reserved
Reserved
Reserved
Definition
"1"
Ready
Suspended
Error
Error
Error
-
"0"
Busy
Operation in Progress / Completed
Successful
Successful
Successful
-
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the
over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
9
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
DEVICE IDENTIFIER CODE
Pins
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex. Data
Manufacturer Code
VIL
0
0
0
1
1
1
0
0
1CH
Device Code (-T160S2BVP)
VIH
1
0
1
0
0
0
0
0
A0H
Device Code (-B160S2BVP)
VIH
1
0
1
0
0
0
0
1
A1H
Code
In the word-wide mode, the upper data(D15-8) is "0".
ABSOLUTE MAXIMUM RATINGS
Symbol
F-Vcc
VI1
Parameter
Flash Vcc voltage
All input or output voltage 1)
Conditions
Min
Max
Unit
With respect to Ground
-0.2
-0.6
4.6
4.6
V
V
Ta
Ambient temperature
-20
85
°C
Tbs
Temperature under bias
-50
95
°C
Tstg
I OUT
Storage temperature
Output short circuit current
-65
125
100
°C
mA
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is F-VCC+0.5V which, during transitions, may overshoot to F-VCC+1.5V for periods <20ns.
CAPACITANCE
Parameter
Symbol
CIN
COUT
Test conditions
Input capacitance (Address, Control Pins)
Output capacitance
Limits
Typ
Min
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
Max
8
12
Unit
pF
pF
Note: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM.
DC ELECTRICAL CHARACTERISTICS (Ta = -20~ 85°C, F-Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Symbol
Parameter
ILI
ILO
ISB1
Input leakage current
Output leakage current
F-VCC standby current
ISB2
ISB3
F-VCC deep powerdown current
ISB4
ICC1
F-VCC read current for Word or Byte
ICC2
F-VCC Write current for Word or Byte
ICC3
ICC4
ICC5
VIL
VIH
VOL
VOH1
VOH2
VLKO
F-VCC program current
F-VCC erase current
F-VCC suspend current
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Low VCC Lock-Out voltage 2)
Test conditions
Limits
Typ1)
Min
Unit
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
50
Max
±2.0
±11
200
F-VCC = 3.6V, VIN=GND or F-VCC,
F-CE# = F-RP# = F-WP# = F-VCC±0.3V
0.1
5
mA
5
15
mA
0.1
8
2
5
15
4
mA
0V£VIN£F-VCC
0V£VOUT£F-VCC
F-VCC = 3.6V, VIN=VIL/VIH, F-RP# = VIL
F-VCC = 3.6V, VIN=GND or VCC, F-RP# =GND±0.3V
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = VIL,
F-RP#=OE#=VIH, IOUT = 0mA
5MHz
1MHz
F-VCC = 3.6V,VIN=VIL/VIH, F-CE# =WE#= VIL,
F-RP#=OE#=VIH
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP# = VIH
– 0.5
2.0
IOL = 4.0mA
IOH = –2.0mA
IOH = –100mA
mA
15
mA
35
35
200
0.8
mA
mA
mA
V
V
V
V
V
V
F-Vcc+0.5
0.45
0.85(F-Vcc)
F-Vcc–0.4
1.5
mA
mA
mA
2.2
All currents are in RMS unless otherwise noted.
1) Typical values at F-Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.
If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
10
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C)
Read-Only Mode
Limits
Symbol
Parameter
Speed Item: -90
F-Vcc=2.7~3.6V
Min
Typ
90
Unit
Max
25
ns
ns
ns
ns
ns
ns
ns
ns
F-RP# low to output high-Z
150
ns
ta(BYTE) tFL/HQV BYTE# access time
tBHZ
tFLQZ BYTE# low to output high-Z
90
25
ns
tRC
ta (AD)
ta (CE)
ta (OE)
tCLZ
tDF(CE)
tOLZ
tDF(OE)
tPHZ
tAVAV
tAVQV
tELQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tPLQZ
Read cycle time
Address access time
Chip enable access time
Output enable access time
Chip enable to output in low-Z
Chip enable high to output in high Z
Output enable to output in low-Z
Output enable high to output in high Z
tOH
tOH
Output hold from CE#, OE#, addresses
90
90
30
0
25
0
ns
ns
0
tBCD
tELFL/H F-CE# low to BYTE# high or low
5
ns
tBAD
tAVFL/H Address to BYTE# high or low
5
ns
tOEH
tWHGL
OE# hold from WE# high
10
ns
tPS
tPHEL
F-RP# recovery to F-CE# low
150
ns
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~85°C)
Write Mode (WE# control)
Symbol
tWC
tAS
tAH
tDS
tDH
tOEH
tAVAV
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
tELWL
tWHEH
tWLWH
tWHWL
tFL/HWH
tWHFL/H
tGHWL tGHWL
tBLS tPHHWH
tBLH tQVPH
Write cycle time
Address set-up time
Address hold time
Data set-up time
Data hold time
OE# hold from WE# high
Latency between Read and Write FFH or 71H
Chip enable set-up time
Chip enable hold time
Write pulse width
Write pulse width high
Byte enable high or low set-up time
Byte enable high or low hold time
OE# hold to WE# Low
Block Lock set-up to write enable high
Block Lockhold from valid SRD
tDAP
tDAE
tWHRL
tPS
Duration of auto-program operation
Duration of auto-block erase operation
WE# high to F-RY/BY# low
F-RP# high recovery to write enable low
tRE
tCS
tCH
tWP
tWPH
tBS
tBH
tWHRH1
tWHRH2
tWHRL
tPHWL
Limits
Speed Item: -90
Parameter
Min
90
50
0
F-Vcc=2.7~3.6V
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
0
10
30
0
0
60
30
50
90
0
90
0
4
80
40
600
90
150
ms
ms
ns
ns
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at F-Vcc=3.3V, Ta=25°C
11
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC ELECTRICAL CHARACTERISTICS (Ta = -20 ~ 85°C)
Write Mode (CE# control)
Parameter
Symbol
tWC
tAS
tAH
tDS
tDH
tOEH
tAVAV
tAVWH
tEHAX
tDVWH
tEHDX
tEHGL
tWLEL
tEHWH
tELEH
tRE
tWS
tWH
tCEP
tCEPH
tBS
tBH
tGHEL
tBLS
tBLH
tDAP
tDAE
tEHEL
tFL/HWH
tWHFL/H
tGHEL
tPHHEH
tQVPH
Write cycle time
Address set-up time
Address hold time
Data set-up time
Data hold time
OE# hold from F-CE# high
Latency between Read and Write FFH or 71H
Write enable set-up time
Write enable hold time
F-CE# pulse width
F-CE# pulse width high
Byte enable high or low set-up time
Byte enable high or low hold time
OE# hold to F-CE# Low
Block Lock set-up to write enable high
Block Lockhold from valid SRD
tEHRL
tEHRH1 Duration of auto-program operation
tEHRH2 Duration of auto-block erase operation
tEHRL F-CE# high to F-RY/BY# low
tPS
tPHWL
Limits
Speed Item: -90
F-Vcc=2.7~3.6V
Min
Typ
Max
90
50
0
50
0
Unit
10
30
0
0
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
50
90
90
90
0
ns
ns
ns
ns
ns
ns
4
80
40
600
ms
ms
90
ns
ns
150
F-RP# high recovery to write enable low
Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at F-Vcc=3.3V, Ta=25°C
Erase and Program Performance
Min
Parameter
Block Erase Time
Main Block Write Time (Page Mode)
Page Write Time
Typ
Max
Unit
40
1.0
4
600
1.8
80
ms
sec
ms
Typ
Max
Unit
15
15
ms
Max
Unit
Program Suspend Latency / Erase Suspend Time
Min
Parameter
Program Suspend Latency
Erase Suspend Time
ms
Please see page 19.
Vcc Power Up / Down Timing
Symbol
tVCS
Parameter
RP# =VIH set-up time from Vccmin
Min
2
Typ
ms
Please see page 12.
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2msec is always required before read operation or write operation is initiated from the time F-Vcc reaches F-Vccmin
during power up/down.
By holding F-RP# VIL, the contents of memory is protected during F-Vcc power up/down.
During power up, F-RP# must be held VIL for min.2ms from the time F-Vcc reaches F-Vccmin.
During power down, F-RP# must be held VIL until Vcc reaches GND.
F-RP# doesn't have latch mode ,therefore F-RP# must be held VIH during read operation or erase/program operation.
12
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
Read /Write Inhibit
F-VCC
Read /Write Inhibit
3.3V
GND
tVCS
F-RP#
VIH
VIL
F-CE#
VIH
VIL
WE#
tPS
tPS
VIH
VIL
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
TEST CONDITIONS
FOR AC CHARACTERISTICS
VIH
ADDRESSES
ADDRESS VALID
VIL
F-CE#
tRC
VIH
VIL
OE#
ta (CE)
tDF(CE)
VIH
VIL
WE#
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : £5ns
Reference voltage
at timing measurement : 1.5V
ta (AD)
Output load : 1TTL gate +
CL(30pF)
or
tDF(OE)
tOEH
VIH
ta (OE)
VIL
tOH
tOLZ
DATA
VOH
VOL
F-RP#
HIGH-Z
tCLZ
tPS
VIH
VIL
*: When BYTE#=VIL , A-1 must be applied.
13
OUTPUT VALID
1.3V
HIGH-Z
1N914
tPHZ
3.3kW
DUT
CL =30pF
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
VIH
ADDRESSES
ADDRESS VALID
VIL
F-CE#
tRC
VIH
ta (AD)
VIL
tDF(CE)
ta (CE)
VIH
OE#
VIL
tRE
tDF(OE)
VIH
WE#
ta (OE)
VIL
VOH HIGH-Z
DATA
tOH
tOLZ
FFH or 71H
tCLZ
Valid
OUTPUT VALID
VOL
tPS
F-RP#
HIGH-Z
tPHZ
VIH
VIL
In the case of use F-CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
BYTE AC WAVEFORMS FOR READ OPERATION
ADDRESSES VIH
(A0 - A19,A-1*) VIL
ADDRESS VALID
ADDRESS VALID
ta(AD)
F-CE#
VIH
VIL
tDF(CE)
ta(CE)
OE#
VIH
ta(OE)
VIL
BYTE#
ta(BYTE)
tOLZ
VIL
VIH
DATA
(D0 - D7) VIL
VIH
DATA
(D8 - D14) VIL
D15 / A-1
VIH
VIL
tBAD
tCLZ
VIH
tDF(OE)
ta(BYTE)
tBCD
HIGH-Z
tOH
tBAD
OUTPUT VALID
VALID
VALID
tBHZ
ta(AD)
HIGH-Z
VALID
A-1
D15
A-1
When BYTE#=VIH, F-CE#=OE#=VIL , D15/A-1 is output status. At this time, input signal must not be applied.
14
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
The other bank
address
VIH
BANK ADDRESS
VALID
A19~A7
VIL
BYTE#=VIL
(A6~A-1)
BYTE#=VIH
(A6 ~A0)
VALID
tCS
OE#
01H~FEH
FFH
01H~7EH
7FH
ta(CE)
ta(CE)
tCH
ta(OE)
tWPH
VIH
tWP
VIH
tDAP
tDH
tDS
41H
tOEH
tGHWL
ta(OE)
tOEH
VIL
DATA
BANK ADDRESS VALID
VIH
VIL
WE#
tAH
tAS
VIH
VIL
DOUT
DIN
DIN
FFH
tWHRL
VOH
VOL
VIH
BYTE#
SRD
DIN
VIL
F-RY/BY#
READ STATUS
WRITE READ
REGISTER ARRAY COMMAND
ADDRESS VALID
VALID
00H
VIL
tWC
F-CE#
VALID
00H
VIH
PROGRAM
tBH
tBS
VIL
tPS
F-RP#
VIH
VIL
WP#
tBLH
tBLS
VIH
VIL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (F-CE# control)
VIH
A19~A7
VIL
BYTE#=VIL
(A6~A-1)
BYTE#=VIH
(A6 ~A0)
The other bank
address
BANK ADDRESS
VALID
VALID
VIL
OE#
FFH
7FH
ta(CE)
ta(OE)
tCEP
tWS
tOEH
tWH
tOEH
tGHEL
tDAP
VIH
tDH
tDS
VIH
41H
DIN
VIL
F-RY/BY#
01H~FEH
01H~7EH
ta(OE)
VIH
VIL
DATA
BANK ADDRESS VALID
tAH ta(CE)
tCEPH
VIL
WE#
tAS
VIH
VIL
READ STATUS
WRITE READ
REGISTER ARRAY COMMAND
ADDRESS VALID
VALID
00H
tWC
F-CE#
VALID
00H
VIH
PROGRAM
DOUT
DIN
DIN
SRD
FFH
tEHRL
VOH
VOL
tBS
VIH
BYTE#
F-RP#
VIL
VIH
15
tPS
VIH
VIL
WP#
tBH
tBLS
tBLH
VIL
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
PROGRAM
VIH
BANK ADDRESS
VALID
ADDR
VIL
F-CE#
tWC
tCS
WRITE READ
ARRAY COMMAND
BANK(I) ADDRESS VALID
tAH
tCH
tWP
VIH
VIL
WE#
tAS
READ STATUS
REGISTER
ta(CE)
VIH
VIL
OE#
ADDRESS
VALID
ta(OE)
tOEH
tWPH
VIH
VIL
tDS
VIH
40H
DATA
DIN
SRD
FFH
VIL
tDH
VIH
F-RY/BY#
tWHRL
VIL
tBS
VIH
BYTE#
VIL
tPS
tBH
VIH
F-RP#
F-WP#
tDAP
VIL
tBLS
tBLH
VIH
VIL
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (F-CE# control)
VIH
ADDR
VIL
F-CE#
PROGRAM
BANK ADDRESS
VALID
ADDRESS
VALID
tWC
tAS
(to only BANK(I))
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
BANK(I) ADDRESS VALID
tAH
ta(CE)
VIH
VIL
OE#
VIL
WE#
ta(OE)
VIH
tCEP
tWS
tOEH
tWH
VIH
VIL
tDS
VIH
40H
DATA
DIN
SRD
FFH
VIL
tDH
VIH
F-RY/BY#
tEHRL
VIL
tBS
VIH
BYTE#
VIL
tBH
tPS
VIH
F-RP#
F-WP#
VIL
tDAP
tBLS
tBLH
VIH
VIL
16
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
READ STATUS
REGISTER
ERASE
VIH
BANK ADDRESS
VALID
ADDRESSES
VIL
BANK ADDRESS VALID
ADDRESS VALID
tWC
tAH
tAS
ta(CE)
VIH
F-CE#
VIL
tCS
tCH
ta(OE)
VIH
OE#
VIL
tOEH
tWPH
tDAE
VIH
WE#
VIL
tWP
F-RY/BY#
tDH
tDS
VIH
DATA
20H
SRD
D0H
VIL
FFH
tWHRL
VOH
tBS
VOL
tBH
VIH
BYTE#
WRITE READ
ARRAY COMMAND
VIL
tPS
F-RP#
VIH
VIL
F-WP#
tBLH
tBLS
VIH
VIL
AC WAVEFORMS FOR ERASE OPERATIONS (F-CE# control)
VIH
ADDRESSES
VIL
READ STATUS
REGISTER
ERASE
BANK ADDRESS
VALID
ADDRESS VALID
tWC
BANK ADDRESS VALID
tAH
tAS
ta(CE)
VIH
F-CE#
VIL
tCEPH
tCEP
ta(OE)
VIH
OE#
tOEH
VIL
tWS
tDAE
tWH
VIH
WE#
VIL
F-RY/BY#
20H
SRD
D0H
VIL
FFH
tEHRL
VOH
VOL
tBS
tBH
VIH
BYTE#
tDH
tDS
VIH
DATA
WRITE READ
ARRAY COMMAND
VIL
tPS
F-RP#
VIH
VIL
tBLS
tBLH
VIH
F-WP#
17
VIL
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM THE OTHER BANK
WITH BGO
PROGRAM DATA TO ONE BANK
A19~A7
VIH
BANK ADDRESS
VALID
VIL
BYTE#=VIL
(A6~A-1) VIH
BYTE#=VIH
(A6 ~A0) VIL
F-CE#
01H~FEH
FFH
00H
01H~7EH
7FH
tAS
tCS
VALID
VALID
VALID
VALID
ta(CE)
tAH
tCH
VIH
ta(OE)
tOEH
tWP
tWPH
VIL
WE#
00H
VIH
VIL
OE#
tWC
ADDRESS VALID
VIH
VIL
tDS
VIH
DATA
41H
DIN
DIN
DIN
SRD
VIL
DOUT
tWHRL
tDH
VIH
DOUT
F-RY/BY#
VIL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (F-CE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
A19~A7
VIH
VIL
BANK ADDRESS
VALID
BYTE#=VIL
(A6~A-1) VIH
BYTE#=VIH
(A6 ~A0) VIL
F-CE#
tWC
VIH
VIL
WE#
ADDRESS VALID
00H
01H~FEH
FFH
00H
01H~7EH
7FH
tAS
tCEPH
tCEP
tWS
VALID
VALID
VALID
VALID
ta(CE)
tAH
VIH
VIL
OE#
ARRAY READ FROM THE OTHER BANK
WITH BGO
ta(OE)
tOEH
tCH
VIH
VIL
DATA
tDS
VIH
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
VIL
VIH
tDH
tEHRL
F-RY/BY#
VIL
18
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
VIH
BANK ADDRESS
VALID
A19~A7
VIL
BYTE#=VIL VIH
(A6~A-1)
BYTE#=VIH VIL
(A6 ~A0)
ADDRESS VALID
VALID
tWC
tAH
tAS
VIL
tCS
tCH
VIH
OE#
VIH
WE#
VALID
VALID
VALID
ta(OE)
tOEH
tWP
tWPH
VIL
VALID
ta(CE)
VIH
F-CE#
ARRAY READ FROM BANK(II) WITH BGO
VIL
tDS
VIH
40H
DATA
DIN
SRD
DOUT
DOUT
VIL
tDH
VIH
F-RY/BY#
VIL
tWHRL
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (F-CE# control)
A19~A7
PROGRAM DATA TO
BANK(I)
VIH
BANK ADDRESS
VALID
VIL
BYTE#=VIL VIH
(A6~A-1)
BYTE#=VIH VIL
(A6 ~A0)
F-CE#
tWC
tAS
VIH
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
VALID
VALID
VALID
VALID
ta(CE)
VIH
VIL
WE#
ADDRESS VALID
VALID
tCEPH
VIL
OE#
READ STATUS
REGISTER
ta(OE)
tCEP
tOEH
tWS
tCH
VIH
VIL
tDS
VIH
40H
DATA
DIN
SRD
DOUT
DOUT
VIL
VIH
tDH
F-RY/BY#
VIL
tEHRL
19
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address
BLOCK ERASE IN
ONE BANK
VIH
BANK ADDRESS
VALID
ADDRESSES
VIL
ADDRESS VALID
tWC
F-CE#
tCS
VALID
VALID
ta(OE)
tOEH
tWP
tWPH
VIH
ARRAY READ FROM THE OTHER
BANK WITH BGO
ta(CE)
tCH
VIH
VIL
WE#
tAH
tAS
VIH
VIL
OE#
READ STATUS
REGISTER
VIL
tDS
VIH
DATA
20H
D0H
SRD
DOUT
DOUT
VIL
tDH
VIH
F-RY/BY#
VIL
tWHRL
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (F-CE# control)
Change Bank Address
VIH
ADDRESSES
VIL
F-CE#
BLOCK ERASE IN
ONE BANK
BANK ADDRESS
VALID
tWC
OE#
VIH
VIL
WE#
ADDRESS VALID
tAS
tAH
VIH
tCEPH
VIL
tCEP
tWS
READ DATA FROM THE OTHER BANK
WITH BGO
READ STATUS
REGISTER
VALID
VALID
ta(CE)
ta(OE)
tOEH
tCH
VIH
VIL
tDS
VIH
DATA
20H
SRD
D0H
DOUT
DOUT
VIL
VIH
tDH
F-RY/BY#
VIL
tEHRL
20
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)
READ STATUS
REGISTER
VIH
ADDRESSES
VIL
BANK ADDRESS VALID
tAS
tAH
VIH
F-CE#
BANK ADDRESS VALID
ta(CE)
VIL
tCS
tCH
ta(OE)
VIH
OE#
tOEH
VIL
Program Suspend Latency
VIH
WE#
VIL
tWP
S.R.6,7=1
VIH
DATA
F-RY/BY#
F-RP#
VALID SRD
B0H
VIL
VOH
VOL
VIH
VIL
tBLS
tBLH
VIH
F-WP#
VIL
AC WAVEFORMS FOR SUSPEND OPERATION (F-CE# control)
READ STATUS
REGISTER
VIH
ADDRESSES
BANK ADDRESS VALID
BANK ADDRESS VALID
VIL
tAS
tAH
VIH
F-CE#
ta(CE)
tCEP
VIL
ta(OE)
VIH
OE#
VIH
WE#
tOEH
VIL
Program Suspend Latency
tWS
tWH
VIL
S.R.6,7=1
VIH
DATA
F-RY/BY#
F-RP#
B0H
VALID SRD
VIL
VOH
VOL
VIH
VIL
tBLS
tBLH
VIH
F-WP#
21
VIL
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
FULL STATUS CHECK PROCEDURE
LOCK BIT PROGRAM FLOW CHART
STATUS REGISTER
READ
SR.4 =1
and
SR.5 =1
?
NO
START
WRITE 77H
COMMAND SEQUENCE ERROR
YES
WRITE D0H
BLOCK ADDRESS
SR.5 = 0 ?
BLOCK ERASE ERROR
NO
SR.7 = 1 ?
NO
YES
YES
PROGRAM ERROR
(PAGE, LOCK BIT)
SR.4 = 0 ?
NO
LOCK BIT PROGRAM
FAILED
SR.4 = 0 ?
NO
YES
YES
PROGRAM ERROR
(BLOCK)
SR.3 = 0 ?
NO
LOCK BIT PROGRAM
SUCCESSFUL
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
BYTE PROGRAM FLOW CHART
PAGE PROGRAM FLOW CHART
START
START
WRITE 40H
WRITE 41H
n=0
WRITE
ADDRESS , DATA
SR.7 = 1 ?
n = n+1
WRITE
ADDRESS n, DATA n
STATUS REGISTER
READ
NO
WRITE B0H ?
NO
n = FFH ?
or
n = 7FH ?
NO
YES
YES
FULL STATUS CHECK
IF DESIRED
YES
STATUS REGISTER
READ
SUSPEND LOOP
PAGE PROGRAM
COMPLETED
WRITE D0H
YES
SR.7 = 1 ?
NO
* Byte/Word program is admitted to only BANK(I).
YES
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
22
WRITE B0H ?
NO
YES
SUSPEND LOOP
WRITE D0H
YES
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
SUSPEND / RESUME FLOW CHART
CLEAR PAGE BUFFER
START
START
SUSPEND
WRITE B0H
WRITE 55H
STATUS REGISTER
READ
WRITE D0H
SR.7 = 1?
NO
PAGE BUFFER CLEAR
COMPLETED
YES
SR.6 =1?
PROGRAM / ERASE
COMPLETED
NO
SINGLE DATA LOAD TO PAGE BUFFER
YES
WRITE FFH
START
WRITE 74H
READ ARRAY DATA
WRITE
ADDRESS , DATA
DONE
READING ?
NO
YES
DONE
LOADING?
NO
RESUME
WRITE D0H
OPERATION
RESUMED
YES
SINGLE DATA LOAD
TO PAGE BUFFER
COMPLETED
* The bank address is required when writing this command. Also, there is
no need to suspend the erase or program operation when reading data
from the other bank. Please use BGO function.
BLOCK ERASE FLOW CHART
PAGE BUFFER TO FLASH
START
START
WRITE 20H
WRITE 0EH
WRITE D0H
BLOCK ADDRESS
WRITE D0H
PAGE ADDRESS
STATUS REGISTER
READ
STATUS REGISTER
READ
NO
NO
SR.7 = 1 ?
WRITE B0H ?
NO
YES
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
SR.7 = 1 ?
YES
FULL STATUS CHECK
IF DESIRED
WRITE D0H
PAGE BUFFER TO FLASH
COMPLETED
23
YES
BLOCK ERASE
COMPLETED
WRITE B0H ?
NO
YES
SUSPEND LOOP
WRITE D0H
YES
Sep. 1999 , Rev.2.0
Clear
Status Register
Read
Status Register
50H
70H
70H
90H
71H
70H
Read
Device Identifier
90H
Read
Lock Status
71H
71H
90H
FFH
FFH
FFH
Setup State
Clear
Page Buffer
Setup
D0H
55H
WD
0EH
74H
Single Data Load
to Page Buffer
Setup
Page Buffer to Flash
Setup
41H
Page Program
Setup
D0H
OTHER
40H
Internal State
Lock Bit Program
Setup
Byte Program
Setup
WDi
i=0-255
WD
20H
77H
D0H
B0H
B0H
D0H
Suspend State
Read Array
(From The Other Bank)
Change Bank
Address
70H
FFH
Read Array
70H
MITSUBISHI LSIs
Sep. 1999 , Rev.2.0
Read State with BGO
Read
Status Register
OTHER
M6MGB/T160S2BVP
Read
Status Register
D0H
Erase All Unlocked
Blocks Setup
OTHER
D0H
Erase &
Verify
Read
Status Register
Change Bank
Address
Block Erase
Setup
D0H
OTHER
Program &
Verify
Ready
A7H
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Read Array
OPERATION STATUS and EFFECTIVE COMMAND
24
Read/Standby State
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
2. SRAM
The SRAM of M6MGB/T160S2BVP is organized as
131,072-word by 16-bit/ 262,144-byte by 8-bit. These devices
operate on a single +2.7~3.6V powersupply, and are directly
TTL compatible to both input and output. Its fully static circuit
needs no clocks and no refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BYTE#, S-CE , WE# and OE#.
Each mode is summarized in the function table.
A write operation is executed whenever the low level WE#
overlaps with the high level S-CE. The address(A-1~A16:byte
mode, A0~A16:word mode) must be set up before the write
cycle and must be stable during the entire cycle.
A read operation is executed by setting WE# at a high level
and OE# at a low level while S-CE are in an active
state(S-CE=H).
When setting BYTE# at the low level and other pins are in
anactive stage , lower-byte I/O are in a selesctable mode in
whichboth reading and writing are enabled, and upper-byte are
in anon-selectable mode.
When setting S-CE at a low level,the chips are in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in ahigh-impedance
state, allowing OR-tie with other chips and memory expansion
by S-CE.
The power supply current is reduced as low as 0.3mA(25
C,typical), and the memory data can be held at +2V
powersupply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S-CE BYTE# WE# OE#
L
X
X
X
H
H
L
X
25
Mode
Non selection
Write
H
H
H
L
H
H
H
H
H
L
L
X
Write
H
L
Read
H
L
H
H
L
H
Read
DQ0~7 DQ8~15
Icc
High-Z High-Z Standby
Din
Din
Active
Dout
Dout
High-Z High-Z
Active
Active
Din
High-Z
Active
Dout
High-Z
Active
High-Z High-Z
Active
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
S-Vcc
VI
VO
Pd
Supply voltage
Input voltage
Ta
Tstg
Conditions
With respect to GND
Ratings
With respect to GND
With respect to GND
Output voltage
Power dissipation
Operating
temperature
Ta=25 C
Units
-0.5* ~ +4.6
-0.5* ~ S-Vcc + 0.5
0 ~ S-Vcc
700
mW
- 20 ~ +85
C
- 65 ~ +150
C
W-version
Storage temperature
V
* -3.0V in case of AC (Pulse width<
= 30ns)
DC ELECTRICAL CHARACTERISTICS
Symbol
( S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
Parameter
Conditions
Min
VIH
VIL
VOH1
VOH2
VOL
II
High-level input voltage
Low-level output voltage
Input leakage current
IOL=2mA
VI =0 ~ S-Vcc
IO
Output leakage current
S-CE=VIL or OE#=VIH, VI/O=0 ~ S-Vcc
Icc1
Active supply current
( AC,MOS level )
S-CE = S-Vcc-0.2V
other inputs <
= 0.2V or >
= S-Vcc-0.2V
Output - open (duty 100%)
f= 10MHz
f= 1MHz
Icc2
Active supply current
( AC,TTL level )
S-CE=VIH
other pins =VIH or VIL
Output - open (duty 100%)
f= 10MHz
f= 1MHz
2.0
-0.3 *
2.4
Low-level input voltage
High-level output voltage 1 IOH= -0.5mA
High-level output voltage 2 IOH= -0.05mA
Icc4 Stand by supply current
( AC,TTL level )
CI
CO
Input capacitance
Output capacitance
V
S-CE <
= 0.2V
Other inputs=0~S-Vcc
-W
-
45
5
60
15
60
15
30
-
+40 ~ +70 C
-
-
+25 ~ +40 C
-
1
5
- 20 ~ +25 C
-
0.3
2
-
-
0.5
S-CE=VIL
Other inputs= 0 ~ S-Vcc
10
mA
mA
mA
mA
* -3.0V in case of AC (Pulse width<
= 30ns)
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Parameter
0.6
45
5
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for S-Vcc=3.0V and Ta=25 C
Symbol
Units
S-Vcc+0.3V
0.4
±1
±1
<
Stand by supply current
( AC,MOS level )
Max
S-Vcc-0.5V
+70 ~ +85 C
Icc3
Typ
Limits
Conditions
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Min
Typ
Max
8
10
Units
pF
Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM.
26
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
AC ELECTRICAL CHARACTERISTICS
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
(1) TEST CONDITIONS
Supply voltage
Input pulse
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
VIH=2.2V,VIL=0.4V
5ns
1TTL
DQ
CL
VOH=VOL=1.5V
Transition is measured ±500mV from
steady state voltage.(for ten,tdis)
Including scope and
jig capacitance
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Parameter
Symbol
tCR
ta(A)
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S-CE low
Output disable time after OE# high
Output enable time after S-CE high
Output enable time after OE# low
Data valid time after address
SRAM
Min
85
Units
Max
85
85
45
30
30
10
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(CE)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
27
SRAM
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to WE#
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from WE# low
Output disable time from OE# high
Output enable time from WE# high
Output enable time from OE# low
Min
85
60
0
70
70
35
0
0
Units
Max
30
30
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~16
(Word Mode)
A-1~16
(Byte Mode)
ta(A)
S-CE
tv (A)
ta(CE)
tdis (CE)
(Note3)
(Note3)
ta (OE)
OE#
(Note3)
ten (OE)
tdis (OE)
(Note3)
WE# = "H" level
ten (CE)
DQ0~15
(Word Mode)
VALID DATA
DQ0~7
(Byte Mode)
Write cycle ( WE# control mode )
tCW
A0~16
(Word Mode)
A-1~16
(Byte Mode)
tsu (CE)
S-CE
tsu (A-WH)
(Note3)
(Note3)
OE#
tsu (A)
tw (W)
trec (W)
tdis (W)
WE#
ten(OE)
tdis(OE)
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
ten (W)
DATA IN
STABLE
tsu (D)
28
th (D)
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
Write cycle (S-CE control mode)
tCW
A0~16
(Word Mode)
A-1~16
(Byte Mode)
tsu (A)
tsu (CE)
trec (W)
S-CE
(Note4)
WE#
(Note3)
tsu (D)
th (D)
(Note3)
DQ0~15
(Word Mode)
DQ0~7
(Byte Mode)
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
Note 4: When the falling edge of WE# is simultaneously or priorto the rising edge of S- CE,
the outputs are maintained in the high impedance state.
Note 5: Don't apply inverted phase signal externally when DQ pin is in output mode.
29
Sep. 1999 , Rev.2.0
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test conditions
Min
S-Vcc (PD) Power down supply voltage
Icc (PD)
Max
S-Vcc=3.0V
Power down
supply current
S-CE = 0.2V
other inputs=0~3V
-W
Units
V
2.0
Chip select input S-CE
>
VI (CE)
Limits
Typ
+70 ~ +85 C
-
-
+40 ~ +70 C
-
-
+25 ~ +40 C
-
-20 ~ +25 C
-
0.2
24
V
mA
mA
1
8
3
mA
0.3
1
mA
Typical value is for Ta=25 C
(2) TIMING REQUIREMINTS
Limits
Symbol
Parameter
tsu (PD)
trec (PD)
Power down set up time
Test conditions
Min
Typ
Max
ns
0
5
Power down recovery time
Units
ms
(3) TIMING DIAGRAM
S-CE control mode
S-Vcc
2.7V
2.7V
S-CE
0.2V
0.2V
tsu (PD)
S-CE <
= 0.2V
trec (PD)
BYTE# TIMING DIAGRAM
(1) TIMING REQUIREMINTS
Symbol
tsu (BYTE)
trec (BYTE)
Limits
Parameter
Test conditions
Min
BYTE# set up time
5
5
BYTE# recovery time
Typ
Max
Units
ms
ms
(2) TIMING DIAGRAM
S-CE
tsu (BYTE)
trec (BYTE)
BYTE#
30
Sep. 1999 , Rev.2.0