HFC0100

HFC0100
QUASI RESONANT CONTROLLER
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The HFC0100 is a peak current mode controller
with Green Mode Operation. Its high efficiency
feature over the entire line and load range
meets the stringent world-wide energy
efficiency requirements.
•
•
•
•
The HFC0100 integrated with a high voltage
current source, its valley detector ensures
minimum Drain-Source voltage switching
(Quasi-Resonant operation). When the output
power falls below a given level, the controller
enters the burst mode.
The HFC0100 features variable protections like
Thermal Shutdown (TSD), Vcc Under voltage
Lockout (UVLO), Over Load Protection (OLP),
Over Voltage Protection (OVP).
The HFC0100 is available in the 8-pin SOIC8
package.
•
•
•
•
•
•
•
•
•
Universal Main Input Voltage (85~265VAC)
Quasi-Resonant Operation
Valley Switching for high efficiency and EMI
Active Burst Mode for low standby power
consumption
Internal High Voltage Current Source
High level of integration, allows a very low
number external component count
Maximum Frequency Limited
Internal Soft Start
Internal 250nS Leading Edge Blanking
Thermal shutdown (auto restart with
hysteresis)
Vcc Under Voltage Lockout with Hysteresis
(UVLO)
Over Voltage Protection
Over Load Protection.
APPLICATIONS
•
•
•
Battery charger: cellular phone, digital
camera, video camera, electrical shaver,
emergency lighting system, etc
Standby power supply: CRT-TV, ProjectionTV, LCD-TV, PDP-TV, Desk top PC, Audio
system, etc
SMPS: Inc jet printer, DVD player/recorder,
VCR, CD player, Set top box, Air
conditioner, refrigerator, washing machine,
dish washer, Adapter for NB, etc
All MPS parts are lead-free, halogen free, and adhere to the RoHS directive.
For MPS green status, please visit MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are Registered
Trademarks of Monolithic Power Systems, Inc.
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
1
HFC0100—QUASI RESONANT CONTROLLER
TYPICAL APPLICATION
T1
*
+
+
*
RTN
*
HV
4
5
Drive
N/C
3
6
CS
VCC
2
7
GND
VSD
1
8
FB
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
2
HFC0100—QUASI RESONANT CONTROLLER
ORDERING INFORMATION
Part Number*
HFC0100HS
Package
SOIC8
Top Marking
Free Air Temperature (TA)
HFC100
-40°C to +125°C
*For Tape & Reel, add suffix –Z (e.g. HFC0100HS–Z);
For RoHS compliant packaging, add suffix –LF (e.g. HFC0100HS–LF–Z)
PACKAGE REFERENCE
TOP VIEW
VSD
1
8
FB
VCC
2
7
GND
NC
3
6
CS
HV
4
5
Drive
ABSOLUTE MAXIMUM RATINGS
(1)
HV Break Down Voltage .............. -0.7V to 700V
Vcc, DRV to GND ...........................-0.3V to 22V
FB, CS, VSD to GND ........................-0.3V to 7V
(2)
Continuous Power Dissipation…(TA = +25°C)
………………………………………………....1.3W
Junction Temperature ...............................150°C
Thermal Shut Down ..................................150°C
Thermal Shut Down Hysteresis ..................50°C
Lead Temperature ....................................260°C
Storage Temperature .............. -60°C to +150°C
ESD Capability Human Body Model (All Pins
except HV) ............................................... 2.0kV
ESD Capability Machine Model ................. 200V
Recommended Operation Conditions
(3)
Operating Vcc range ...........................8V to 20V
Maximum Junction Temp. (TJ) ............. +125°C
Thermal Resistance
(4)
θJA
θJC
SOIC8 .....................................96 ...... 45 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
3
HFC0100—QUASI RESONANT CONTROLLER
ELECTRICAL CHARACTERICS
For typical value TJ=25℃
Parameter
Start-up Current Source (Pin HV)
Charging current from Pin HV
Leakage current from Pin HV
Symbol
Icharge
Ileak
Break Down Voltage
VBR
Supply Voltage Management (Pin Vcc)
Vcc Upper Level at which the Internal
VCCH
High Voltage Current Source Stops
Vcc Lower Level at which the Internal
VCCL
High Voltage Current Source Triggers
Vcc Re-charge Level at which the
Vccp
protection occurs
Internal IC Consumption, 1nF Load on
Icc1
Drive Pin,
Internal IC Consumption, Latch off
Icc2
phase,
Feedback Management (Pin FB)
Internal Pull Up Resistor
RFB
Internal Pull Up Voltage
Vup
FB Pin to Current Limit Division Ratio
Idiv
Internal Soft-Start Time
Tss
FB Decreasing Level at which the
VBURL
controller enter the Burst Mode
FB Increasing Level at which the
VBURH
controller leave the Burst Mode
Over Load Set Point
VOLP
Valley Switching Management (Pin VSD)
Valley Switching Threshold Voltage
VVSD
Valley Switching Hysteresis
Vhys
Pin VSD Clamp Voltage
VVSDH
VVSDL
Valley Switching Propagation Delay
TVSD
Minimum Off Time
Tmin
Re-start time After Last Valley detect
Trestart
Transition
OVP Sampling Delay
TOVPS
Pin VSD OVP reference level
VOVP
Internal Impedance
Rint
Current Sampling Management (Pin CS)
Leading Edge Blanking
TLEB
Driving Signal (Pin DRIVE)
Sourcing Resistor
RH
Sinking Resistor
RL
Conditions
Min
Typ
Max
Unit
Vcc=6V;VHV=400V
With
auxiliary
supply; VHV=400V,
Vcc=13V
1.4
2
2.6
mA
--
20
--
μA
700
--
--
V
10.6
11.8
13
V
7.2
8
8.8
V
--
5.5
--
V
Fs=100kHz,
Vcc=12V
--
2.0
--
mA
VCC=6V
--
450
--
μA
-----
10
4.5
3
2.4
-----
kΩ
V
-mS
--
0.5
--
V
--
0.7
--
V
--
3.7
--
V
40
--
55
10
70
--
mV
mV
7
7.5
8
-0.8
-0.65
-0.5
100
160
200
nS
6.6
7.8
9
μS
--
4.6
--
μS
----
3.5
6
24
----
μS
V
kΩ
--
250
--
nS
---
17
7
---
Ω
Ω
High
State;
Ipin2=3.0mA
Low State;
Ipin2=-2.0mA
Pull down from 2V
to -100mV
V
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
4
HFC0100—QUASI RESONANT CONTROLLER
PIN FUNCTIONS
Pin #
Name
1
VSD
2
Vcc
3
4
5
6
7
N/C
HV
Drive
CS
GND
8
FB
Description
Input from the auxiliary flyback signal, it ensures discontinuous operation and valley
switching. It also offers a fixed OVP detection.
Supply voltage Pin. This pin is connected to an external bulk capacitor of typically 22uf and a
ceramic capacitor of typically 0.1uF.
This Pin ensures adequate creepage distance.
Input for the start up current unit.
Output of the driving signal.
Input of the current sense.
Ground.
The Pin sets the peak current limit, by connecting an optocoupler to this Pin. A feedback
voltage of 3.7V will trigger an over load protection, and a feedback voltage of 0.5V will trigger
a burst mode operation.
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
5
HFC0100—QUASI RESONANT CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS
TA=25℃
3400
1000
3000
800
2600
FS=100kHz
FS=60kHz
700
600
2200
1800
8.5
11.8
8.3
11.6
8.1
11.4
11.2
0
25
50
12
10
7.9
9
TEMPERATURE (oC)
0
25
50
8
-40 -20
85 105 125
TEMPERATURE (oC)
Over Load Set Point
Vs Temperature
60
TMIN (us)
VOLP (V)
VVSD (mV)
0
25
50
85 105 125
50
TEMPERATURE (OC)
30
-40 -20
85 105 125
8.5
8
7.5
40
3.4
-40 -20
50
9
70
3.6
25
Minimum Off Time
Vs Temperature
80
3.8
0
TEMPERATURE (oC)
Valley Switching Threshold
Voltage Vs Temperature
4
0 25 50 85 105 125
TEMPERATURE (oC)
11
7.5
-40 -20
85 105 125
1.5
Pin FB Internal Pull Up
Resistor Vs Temperature
Vcc Lower Level at which
the Internal High Voltage
Current Source Triggers Vs
Temperature
7.7
11
-40 -20
2
1
-40 -20
10 11 12 13 14 15 16 17 18
VCC (V)
Vcc Upper Level at which
the Internal High Voltage
Current Source Stops Vs
Temperature
2.5
FS=60kHz
1000
10 11 12 13 14 15 16 17 18
VCC (V)
VCCL (V)
VCCH (V)
12
FS=100kHz
1400
500
400
3
ICHARGE (mA)
1100
900
Charging Current From Pin
HV (Vcc=6V, VHV=400V) Vs
Temperature
IC Consumption Vs
Vcc (1nF Output Load)
ICC1 (uA)
ICC1 (uA)
IC Consumption Vs
Vcc (No Output Load)
0
25
50
85 105 125
TEMPERATURE (OC)
7
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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6
HFC0100—QUASI RESONANT CONTROLLER
TYPICAL PERFORMANCE CHARACTERISTICS (continues)
TA=25℃
Pin VSD OVP reference level
Vs Temperature
OVP Sampling Delay
Vs Temperature
6.2
4
30
28
6.1
VREF (V)
3.6
3.4
26
6
24
5.9
3.2
3
-40 -20 0 25 50 85 105 125
TEMPERATURE (OC)
Sourcing Resistor
Vs Temperature
22
5.8
-40 -20
20
-40 -20
0 25 50 85 105 125
TEMPERATURE (OC)
Sinking Resistor
Vs Temperature
30
20
600
25
15
550
20
10
15
5
10
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
800
VBURH(mV)
TSAMPLE (us)
3.8
Pin VSD Internal Impedance
Vs Temperature
0 25 50 85 105 125
TEMPERATURE (OC)
FB Decreasing Level
at which the controller
enter the Burst Mode
Vs Temperature
500
450
0
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
400
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
FB Increasing Level
at which the controller
leave the Burst Mode
Vs Temperature
VBURH(mV)
750
700
650
600
-40 -20
0
25
50
85 105 125
TEMPERATURE (OC)
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
7
HFC0100—QUASI RESONANT CONTROLLER
BLOCK DIAGRAME
Figure 1— Block Diagram
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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8
HFC0100—QUASI RESONANT CONTROLLER
OPERATION
The HFC0100 incorporates all the necessary
features needed to a reliable Switch Mode Power
Supply. Its valley detector ensures minimum
Drain-Source voltage switching (Quasi-Resonant
operation). When the output power falls below a
given level, the regulator enters the burst mode.
An internal minimum off time limiter prevents the
free running frequency to exceed 150kHz.
+
2
Vcc
RVSD
1
VSD
55mV
HFC0100
Start-Up
Initially, the IC is self supplying from the internal
high voltage current source unit which drawn
from the HV pin.
Figure 2—Valley Detector
The IC starts switching and the internal high
voltage current source unit is stopped as soon as
the voltage on Pin Vcc reaches the threshold
VCCH—11.8V.
Before the supply is taken over by the auxiliary
winding of the transformer, the Vcc capacitor
supplies HFC0100 to maintain Vcc.
VDS
100V/div
Quasi-Resonant Operation
The HFC0100 operates in Discontinuous
Conduction Mode (DCM). The valley detector
ensures
minimum
Drain-Source
voltage
switching (Quasi-Resonant operation)
As a result, there are virtually no primary switch
turn on losses and no secondary diode recovery
losses. It ensures the reduction of the EMI noise.
Valley Switching
4us/div
Figure 3—Valley Switching
To ensure the switching frequency below the
EN55022 start limit---150kHz, HFC0100 employs
an internal minimum off time limiter---7.8μS,
shows as figure 4.
Figure2 shows the valley detector unit.
When the voltage:
(VDS − Vin )x
Naux
24kΩ
x
< 55mV
Npri 24kΩ + R VSD
VDS —Drain Source Voltage of the primary FET
VIN—Input Voltage
Naux —Auxiliary Winding Turns of the transformer
Npri —Primary Winding Turns of the transformer
The valley detector sends out a valley signal to
turn on the primary FET.
VDS
100V/div
Toff≥7.8uS
2us/div
Figure 4—Minimum Off Time Limit
Figure3 shows a typical drain source voltage
waveform with valley switching.
HFC0100 Rev. 1.02
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11/25/2015
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9
HFC0100—QUASI RESONANT CONTROLLER
VCC Under-Voltage Lock-out
When the Vcc below the UVLO threshold-8V, the
HFC0100 stops switching and the internal high
voltage current source unit re-starts, the Vcc
external bulk capacitor is re-charged by it.
Figure 5 shows the typical waveform with Vcc
under voltage lock out.
+
2
Vcc
RVSD
1
VSD
6V
HFC0100
Figure 6—OVP Sample Unit
To avoid the mis-trigger due to the oscillation of
the leakage inductance and the parasitic
capacitance, the OVP sampling has a TOVPS
blanking, typical 3.5μS, shows as Figure 7.
Figure 5—Vcc Under-Voltage Lock Out
Over-Voltage Protection (OVP)
The positive plateau of auxiliary winding voltage
is proportional to the output voltage, the OVP use
the auxiliary winding voltage instead of directly
monitoring the output voltage.
The Figure 6 shows the OVP sample unit.
If the voltage:
VO ×
N aux
24kΩ
×
> 6V
N SEC 24kΩ + R VSD
VO—Output voltage
Naux —Auxiliary Winding Turns of the transformer
NSEC—Secondary
transformer
Winding
Turns
of
the
The OVP circuit is triggered, and the HFC0100
stops the switching cycle and goes into latched
fault condition. The controller stays fully latched
in this position until the Vcc is decreased down to
3V, e.g. when the user unplugs the power supply
from the main supply and re-plugs it.
Figure 7
Over Load Protection (OLP)
The maximum output power is limited by the
maximum switching frequency and maximum
primary peak current. If the output consumes
more than the maximum output power, the output
voltage is drawn below the set point, this reduces
the current through the optocoupler LED, which
also reduces the transistor current, thus
increases the FB voltage.
By continuously monitoring the Pin FB voltage,
when the feedback voltage exceeds the
threshold VOLP—3.7V, it shuts off the switching
cycle. The HFC0100 enters a safe low power
operation that prevents from any lethal thermal or
stress damage. As soon as the default
disappears, the power supply resumes operation.
During the start up or load transient, the FB
voltage will be high enough temporarily to mistrigger the OLP, to prevent this undesired
protection, OLP circuit is designed to be triggered
after Vcc is decreased below 8.5V.
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
10
HFC0100—QUASI RESONANT CONTROLLER
Burst Operation
Current Limit Setting
To minimize the power dissipation in no load or
light load, the HFC0100 enters the burst mode
operation. As the load decreases, the FB voltage
decreases,, the HFC0100 stops the switching
cycle when the FB voltage drops below the
threshold VBURL—0.5V. And the output voltage
starts to drop at a rate dependent on the load.
This causes the FB voltage to rise again. Once
the FB voltage exceeds the threshold VBURH—
0.7V, switching resumes. The FB voltage then
falls and rises repeatedly. The burst mode
operation alternately enables and disables
switching cycle of the MOSFET thereby reducing
switching loss in the no load or light load
conditions.
The switch current is sensed by the resistor
series between the Source of the FET and the
ground. And the current limit is determined by the
Figure 8 shows the typical FB and Drive
waveform during the burst mode.
VBURH:0.7V
VBURL:0.5V
FB signal,
VLimit =
VFB VFB
=
I div
3
. To limit the
maximum output power, the current limit is
clamped at 1V when VFB is bigger than 3.3V.
Leading Edge Blanking
In order to avoid the premature termination of the
switching pulse due to the parasitic capacitance,
an internal leading edge blanking (LEB) unit is
employed between the CS Pin and the current
comparator input. During the blanking time, the
path, CS Pin to the current comparator input, is
blocked. Figure 9 shows the leading edge
blanking.
VLimit
TLEB=250nS
VFB
200mV/div
VDrive
5V/div
40us/div
t
Figure 8—Burst Mode
Thermal Shutdown (TSD)
To prevents from any lethal thermal damage. The
HFC0100 shuts down switching cycle when the
inner temperature exceeds 150DegC. As soon as
the inner temperature drops below 100DegC, the
power supply resumes operation.
Soft-Start
To reduce the stress on primary MOSFET and
secondary diode during start up, to smoothly
establish the output voltage, the HFC0100 has
an internal soft-start circuit that increases the
current comparator inverting input voltage,
together with the MOSFET current, slowly after it
starts up. The pulse width to the power switching
device is progressively increased to establish the
correct working conditions for transformers,
inductors, and capacitors.
Figure 9—Leading Edge Blanking
Over Power Compensation
In the case of current sensing, shows as figure
10, the turn off of the FET is delayed due to the
propagation delay of the control circuit, the delay
time is the inherent characteristic of the control
circuit, so Tdelay can be seen fixed. This delay will
cause an overshoot of the peak current. △I2 is
bigger than △I1 due to the bigger rising ratio(the
higher input voltage, the bigger rising ratio).
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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11
HFC0100—QUASI RESONANT CONTROLLER
The propagation delay is done by means of the
feedforward resistor, shown as Figure 11.
Through this method, adding one offset voltage
at CS pin (the higher input voltage, the bigger
offset voltage.).
Figure 10—Propagation delay of the current
limit
Figure 11—Over Power Compensation
Figure 12 shows the HFC0100 control flow chart.
Figure 13 shows the HFC0100 evolution of the
signals in presence of faults
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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12
HFC0100—QUASI RESONANT CONTROLLER
Start
Y
Internal High Voltage
Current Source ON
Shut Down
Internal High Voltage
Current Source
Y
Vcc>11.8V
N
Vcc Decrease
to 5.5V
Shut off the
Switching Pulse
Y
Vcc<8V
Y
OTP=
Logic
High?
N
Latch off the
Switching Pulse
N
Y
OVP=
Logic
High?
Y
Soft Start
N
Vcc<3V?
N
Thermal
Monitor
Monitor Vcc
Pin VSD
Monitor
Monitor VFB
Y
VFB<0.5V
0.5V<VFB<3.7V
VFB>0.7V
Y
N
Continuous
Fault Monitor
Burst Mode
Operation
Y
VFB>3.7V
Vcc<8.5V?
and
OLP=Logic
High
QR mode Operation
N
Toff<7.8uS
Y
Constraint
Toff_min≥7.8uS
N
OLP=Logic High
UVLO, OTP & OLP are auto restart, OVP
is latch
Release from the latch condition, need to
unplug from the main input.
Figure 12—Control Flow Chart
HFC0100 Rev. 1.02
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11/25/2015
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13
HFC0100—QUASI RESONANT CONTROLLER
Vcc
Start up
Regulation
Occurs Here
Over Voltage
Occurs Here
Unplug from
main input Normal
operation
Normal
operation
Normal
operation
11.8V
8.5V
5.5V
Driver
Pluses
Driver
High voltage
current source
On
Off
IFault Flag
Normal operation
OVP Fault
Occurs Here
Normal operation
OLP Fault
Occurs Here
Normal operation
OTP Fault
Occurs Here
Normal operation
Figure 13—Evolution of the Signals in Presence of Faults
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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14
HFC0100—QUASI RESONANT CONTROLLER
PACKAGE INFORMATION
SOIC8
0.189(4.80)
0.197(5.00)
8
0.050(1.27)
0.024(0.61)
5
0.063(1.60)
0.150(3.80)
0.157(4.00)
PIN 1 ID
1
0.228(5.80)
0.244(6.20)
0.213(5.40)
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.013(0.33)
0.020(0.51)
0.0075(0.19)
0.0098(0.25)
SEE DETAIL "A"
0.050(1.27)
BSC
SIDE VIEW
FRONT VIEW
0.010(0.25)
x 45o
0.020(0.50)
GAUGE PLANE
0.010(0.25) BSC
0o-8o
0.016(0.41)
0.050(1.27)
DETAIL "A"
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
HFC0100 Rev. 1.02
www.MonolithicPower.com
11/25/2015
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© 2015 MPS. All Rights Reserved.
15