Evaluation Board User Guide UG-589 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Interleaved Two-Switch Forward Topology Featuring the ADP1046A FEATURES CAUTION Interleaved 2-switch, forward switching power supply 12 V/25 A regulated output from 400 V dc input Voltage feedback loop Dynamic phase shedding Integrated current balance between phases I2C serial interface to PC Software graphic user interface (GUI) Programmable digital filters 7 PWM outputs including auxiliary PWM (for fan control) Digital trimming OrFET control for hot swap and redundancy Current, voltage, and temperature sense through GUI Digital current sharing This evaluation board uses high voltages and currents. Extreme caution must be taken especially on the primary side to ensure safety for the user. It is strongly advised to power down the evaluation board when not in use. A current-limited power supply is recommended as an input because no fuse is present on the board. GENERAL DESCRIPTION REFERENCE DESIGN CONTENTS The evaluation system package contains the following items: • • User Guide UG-589 ADP1046A 300 W interleaved two-switch forward board 11739-090 The USB-to-I2C dongle for serial communication (ADP1046AUSB-Z) and the software CD must be ordered separately. This evaluation board features the ADP1046A in a switching power supply application. With the evaluation board and software, the ADP1046A can be interfaced to any PC running Windows® 2000, Windows NT, or Windows XP via the computer's USB port. The evaluation board allows all the input and output functions of the ADP1046A to be exercised without the need for external components. The software allows control and monitoring of the ADP1046A internal registers. The board is set up for the ADP1046A to act as an isolated switching power supply with a rated load of 12 V/25 A from an input voltage ranging from 350 V dc to 400 V dc. Figure 1. Picture of Printed Circuit Board PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 48 UG-589 Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Synchronous Rectifier Peak Inverse Voltage (PIV) ............... 21 Reference Design Contents ............................................................. 1 Output Ripple ............................................................................. 21 Caution ............................................................................................... 1 Transient Voltage ........................................................................ 22 General Description ......................................................................... 1 Phase Shedding Turn-On/Off Time ........................................ 25 Revision History ............................................................................... 2 Primary Current During Load Transient ................................ 26 Demo Board Specifications ............................................................. 3 Output Overcurrent Protection................................................ 27 Topology and Circuit Description.................................................. 4 Digital Current Sharing ............................................................. 27 Advantages of Interleaving .............................................................. 5 Closed-Loop Frequency Response........................................... 28 Connectors ........................................................................................ 7 Efficiency ..................................................................................... 28 Settings Files and EEPROM ............................................................ 8 CS1 Linearity............................................................................... 28 Evaluation Board .............................................................................. 9 ACSNS Linearity ........................................................................ 29 Equipment ..................................................................................... 9 CS2 Linearity............................................................................... 29 Setup ............................................................................................... 9 No Load Power ........................................................................... 29 Board Settings ............................................................................. 11 Thermal Performance ................................................................ 29 Theory of Operation ...................................................................... 13 Evaluation Board Schematics and Artwork ................................ 30 During Startup ............................................................................ 13 Main Board Schematic .............................................................. 30 During Steady State .................................................................... 13 Interfaces Schematic .................................................................. 31 Configuring Flag Settings .............................................................. 14 Daughter Card Schematic ......................................................... 32 PWM Settings ................................................................................. 15 Main Board Layout .................................................................... 33 Fan Control ................................................................................. 16 Daughter Card Layout ............................................................... 36 Dynamic Phase Shedding and Standby Power ....................... 16 Bill of Materials ............................................................................... 38 Board Evaluation and Test Data ................................................... 17 Appendix I—Transformer Specifications.................................... 41 Startup .......................................................................................... 17 Appendix II—Output Inductor Specifications ........................... 42 Transformer Primary Waveform .............................................. 19 Appendix III—Register File (ADP1046A_I2SF_032011.46r) .. 43 Primary Current ......................................................................... 19 Appendix IV—Board File (ADP1046A_I2SF_032011.46b) ..... 46 Drain Voltage and Current ........................................................ 20 Related Links ................................................................................... 47 CS1 Pin Voltage and Current Balancing of Phases ................ 20 REVISION HISTORY 8/13—Revision 0: Initial Version Rev. 0 | Page 2 of 48 Evaluation Board User Guide UG-589 DEMO BOARD SPECIFICATIONS Table 1. Target Specifications Parameter VIN VOUT IOUT TA Efficiency Switching Frequency Output Voltage Ripple Min 350 10.8 0.0 0 Typ 385 12 25 50 91.5% 148.8 Max 400 13.2 25 50 100 Unit V V A ºC % kHz mV Rev. 0 | Page 3 of 48 Test Conditions/Comments With 300 LFM air flow Ambient temperature Typical reading at 385 V/25 A load At 25 A load UG-589 Evaluation Board User Guide TOPOLOGY AND CIRCUIT DESCRIPTION This user guide describes the ADP1046A in a typical dc-to-dc switching power supply in an interleaved two-switch forward topology with synchronous rectification. Figure 75 and Figure 76 show the schematics of the main power stage and the peripheral connections, respectively. The daughter card schematic is shown in Figure 77. The circuit is designed to provide a rated load of 12 V/ 25 A from an input voltage source of 350 V dc to 400 V dc. The ADP1046A is used to provide functions such as output voltage regulation, output overcurrent protection, primary cycle-bycycle protection, load current sharing with multiple power supplies over the share bus, and overtemperature protection. The interleaved two-switch forward topology is essentially two two-switch forward designs running 180 degrees out of phase in parallel with each other. The primary side consists of the input terminals (J1, J2), switches (Q1/Q2 for Phase 1, Q3/Q4 for Phase 2), the current sense transformer (T3 for Phase 1 and T4 for Phase 2) and the main power transformer (T1 for Phase 1 and T2 for Phase 2). The ADP1046A (U1 on the daughter card) resides on the secondary side and is powered via the USB 5 V with an ADP3303 LDO (U2 on the daughter card) present on the same daughter card. The gate signal for the primary switches comes from the ADP1046A through the MOSFET driver (U1) and passes through pulse transformers (T5 for Phase 1 and T6 for Phase 2). Diodes (D1/D2 for Phase 1 and D3/D4 for Phase 2) are responsible for circulating the magnetizing current of the transformer through the dc source during the off period of the switch and for clamping the maximum output voltage. C1 and C21 act as decoupling capacitors, and Y capacitors (C67, C68) reduce common-mode noise. The secondary side power stage consists of the synchronous rectifiers (Q5 for Phase 1 and Q6 for Phase 2) and freewheeling FETs (Q7 for Phase 1 and Q9 for Phase 2). The RC series connections (R2/C2, R4/C4, R25/C22, R3/C3) act as snubbers for these FETs. The secondary-side FETs are driven by U2 and U3, which are 4 A drivers with a UVLO of 4.2 V (typical). Also present on the secondary side are the output filter inductors (L1 for Phase 1 and L2 for Phase 2) and the output capacitors (C10 and C8) placed before the OrFET (Q8, Q10). Capacitors (C15, C16) provide high frequency decoupling to lower EMI. The OrFETs are driven by a diode (D7) and a capacitor (C13) that form a peak detector on the switch node of the transformer. The OrFET turn-off is through the GATE pin connected to the FET (Q14) that pulls the gate of the OrFET low, turning it off. The output load current is sensed using resistors (R5, R8). Alternatively, they can also be replaced by using the Rds_on of the OrFETs (open R26 and R16, and short R38 and R39 with 5.5 kΩ/0.01% Resistors R3 and R4 on the daughter card). The output voltage is sensed at VS1 and VS2 for OrFET control and VOUT for output load regulation. Jumpers (J18, J20) can be used for remote sensing. The primary current is sensed through the CS1 pin. A Zener diode (D17) protects the pin from exceeding its absolute maximum rating. A thermistor (RTD1) is placed on the secondary side between Q7 and Q9 and acts as thermal protection for the power supply. A 20 kΩ resistor is placed in parallel with the thermistor that allows the software GUI to read the temperature directly in degrees Celsius. The ADP1046A also features a line feedforward functionality. The switch node on the secondary side of the transformer (T1) is filtered through an RCD filter (R56, C25, D10), and a fraction of the voltage is fed into the ACSNS pin. Also present on the secondary side is the current sharing circuitry, flag LEDs (D11 to D12), and the communications port to the software through the I2C bus. There is a 4-pin connector for I2C communication. This allows the PC software to communicate with the evaluation board (and with other evaluation boards through the extra 4-pin connectors) through the USB port of the PC. The user can easily change register settings on the ADP1046A and monitor the status registers. It is recommended that the USB dongle be connected directly to the PC, not via the external hub. Instead of using an auxiliary supply, the board uses an on-board boost converter that converts the 5 V from the USB to the 12 V that powers the MOSFET drivers. Alternatively, an external 12 V connector (J6) is also present. During normal operation, the drivers are powered from the main 12 V output after the output is in regulation. The 5 V is input from the USB port and generates 3.3 V using an LDO for the ADP1046A. The board also has a connector for a fan capable of driving ~12 V/300 mA from the main 12 V output terminal. The fan is driven by the OUTAUX PWM signal and is duty cycle modulated, providing maximum speed at maximum load. Rev. 0 | Page 4 of 48 Evaluation Board User Guide UG-589 ADVANTAGES OF INTERLEAVING respective primary switches are on. Interleaving technology improves circuit efficiency, reduces current ripple generated at the output, and increases its effective ripple frequency. This allows for reduction of the output filter capacitor. The interleaving approach can also significantly reduce the input filter inductor and capacitor requirement and improve dynamic response. The interleaved two-switch forward (I2SF) topology is popular for its ruggedness. Because the primary switches of the twoswitch forward converter are turned on and off at the same instant, this topology is free of shoot-through problems associated with other topologies such as the full bridge. With an interleaved design, care must be taken not to turn on the synchronous rectifiers (Q5 and Q7, or Q6 and Q9) while their QB1 10:1 VX1 + VTp1 VIN LO1 VO CO SFW1 RL – QA1 QR1 QB2 10:1 VX2 + VTp2 LO2 SFW2 QA2 QR2 11739-001 – Figure 2. Topology of the Interleaved Two-Switch Forward Converter Rev. 0 | Page 5 of 48 UG-589 Evaluation Board User Guide QA1 QB1 QR1 t SFW1 t D t VTp1 D QA2 QB2 QR2 t SFW2 t D t VTp2 D IQA1 IQB1 t ILO1 t IQA2 IQB2 t ILO2 t t t0 t1 t3 t2 11739-002 ILO1 + ILO2 Figure 3. Summary of Key Waveforms for I2SF Topology The key waveforms are illustrated in Figure 3. For the first phase of the two-switch forward converter, the operation can be simplified into three modes: • • Energy transfer stage (t0 to t1): Both primary-side switches (QA1, QB1) and the secondary-side rectifier switch (QR1) are turned on and energy is transferred from input to output Transformer reset stage (t1 to t2): In this stage, two primary-side diodes (or body diodes) conduct and apply • reversed input voltage to the transformer winding to reset the transformer, while the secondary side is freewheeling (SFW2 is on). Dead time stage (t2 to t3): When the transformer is completely reset, the converter goes to the dead time stage with no current in the primary side, while the secondary-side current continues to freewheel. The second phase operates in a similar pattern but with a 180° phase shift in the PWMs. Rev. 0 | Page 6 of 48 Evaluation Board User Guide UG-589 CONNECTORS Table 2 lists the connectors on the board. Table 2. Board Connectors Evaluation Board Function +400 V/−400 V input +12 V/−12 V output External 12 V Fan connector I2C connector Digital share bus Daughter card connector 11739-003 Connector J1/J2 J3/J4 J6 J19 J10 J7 J5 Figure 4. I2C Connector (Pin 1 on Left) The pinout of the USB dongle is shown in Table 3. Table 3. I2C Connector Pin Descriptions Pin No. 1 2 3 4 Evaluation Board Function 5V SCL SDA Ground Rev. 0 | Page 7 of 48 UG-589 Evaluation Board User Guide SETTINGS FILES AND EEPROM The ADP1046A communicates with the GUI software using the I2C bus. The register settings (having extension .46r) and the board settings (having extension .46b) are two files that are associated with the ADP1046A software (see Appendix III—Register File (ADP1046A_I2SF_032011.46r) and Appendix IV—Board File (ADP1046A_I2SF_032011.46b)). The register settings file contains information such as the overvoltage and overcurrent limits, soft start timing, and PWM settings that govern the functionality of the part. The ADP1046A stores all settings in the EEPROM. The EEPROM on the ADP1046A does not contain any information about the board, such as current sense resistor, output inductor, and capacitor values. This information is stored in a board setup file (extension .46b) and is necessary for the GUI to display the correct information in the Monitor window as well as the Filter Settings window (not shown). The entire status of the power supply, such as the ORFET and enable/disable of the synchronous rectifiers, primary current, output voltage, and output current, can thus be digitally monitored and controlled using software only. Always make sure that the correct board file is loaded for the board currently in use. Each ADP1046A chip has trim registers for the temperature, input current, output voltage, output current, and ACSNS. These can be configured during production and are not overwritten whenever a new register settings file is loaded. This is done to retain the trimming of all the ADCs for that corresponding environmental and circuit condition (for example, component tolerances and thermal drift). A guided wizard called the Auto Trim can be used to trim the previously mentioned quantities of the trim registers (for example, temperature, input current, output voltage) so that the measurement value matches the values displayed in the GUI, which allows ease of control through the software. Click Voltage Settings or CS2 Settings in the Setup window (see Figure 9) to access the Auto Trim wizard. BOARD SETUP FILE GUI ADP1046A RAM I2C USB TO I2C INTERFACE DONGLE DIGITAL CLOCK 11739-004 EEPROM REGISTER SETTINGS FILE Figure 5. ADP1046A and GUI Interaction Rev. 0 | Page 8 of 48 Evaluation Board User Guide UG-589 EVALUATION BOARD EQUIPMENT • • • • • DC power supply (350 V to 400 V, 400 W) Electronic load (25 A/300 W) Oscilloscope with differential probes PC with ADP1046A GUI installed Precision digital voltmeters (HP34401or equivalent) for measuring dc voltage 2. 3. 4. SETUP Do not connect the USB cable to the evaluation board until the software has finished installing. Install the ADP1046A software by inserting the installation CD. The software setup starts automatically, and a guided 11739-005 1. process installs the software as well as the drivers for the USB-to-I2C adapter, which allows communication of the GUI with the IC. Insert the daughter card into Connector J5, as shown in Figure 6. Ensure that the PSON switch (SW1 on schematic; see Figure 76) is turned to the off position. It is located on the bottom left half of the board. Connect one end of the USB dongle to the board and the other end to the USB port on the PC using the USB-to-I2C interface dongle. The white LED, D21, should turn on. Figure 6. Printed Circuit Board with Daughter Card Rev. 0 | Page 9 of 48 UG-589 SCAN DASHBOARD SAVE SPY STORE NOW FOR REGISTERS WINDOW BOARD MONITOR TO EEPROM SETTINGS AND CONTROL TO EEPROM AND LOAD/SAVE FILES LOCK/ UNLOCK TRIM REGISTERS Figure 8. Scan for ADP1046A Now Icon Figure 7. ADP1046A Address of 0x50 in the GUI If the software does not detect the part, it enters simulation mode. Ensure that the connecter is connected to J10 (on the main board) or J7 (on the daughter card). Click the Scan Now icon (see Figure 8). 11739-209 6. Click the Store Board Settings to EEPROM icon (see Figure 8), and select the ADP1046A_I2SF_B_xxx.46b file. This file contains all the board information, including the values of the shunt and voltage dividers. Note that all board setting files have an extension of .46b. 11739-007 7. The software should report that the ADP1046A has been located on the board. Click Finish to proceed to the main software interface setup window (see Figure 9). The serial number shown next to the checkbox (see Figure 7) indicates the USB dongle serial number. The windows also displays the device I2C address. 11739-006 5. Evaluation Board User Guide Figure 9. Main Setup Window of the ADP1046A GUI Rev. 0 | Page 10 of 48 Evaluation Board User Guide The original register configuration is stored in the ADP1046A_I2SF_B_xxxx.46r register file. (Note that all register files have an extension of .46r.) The file can be loaded using the second icon from the left in Figure 10. The IC on the board is preprogrammed, and this step is optional. 9. Connect a dc power source (385 V dc nominal, current limit to ~1 A) and an electronic load set to 1 A at the output. 10. Connect a voltmeter at the TP37 and TP38 test points. Ensure that the differential probes are used and that the ground of the probes are isolated if oscilloscope measurements are made on the primary side of the transformer. 11. Turn the PSON switch (SW1 on schematic; see Figure 76) to the on position. Then click the dashboard settings icon (2nd icon from the left in Figure 8), and turn on the software via PSON. The board should now be operational and ready for evaluation. The output should read 12 V dc. 12. Click the Monitor tab and then the Flags and Readings button (not shown) to load the entire state of the power supply unit (PSU) in a single user-friendly window (see Figure 11). 13. After successful startup and the board is in a steady state condition, LEDs on the board provide the status of the board. All the LEDs turn on, indicating that there are no faults detected, such as overvoltage or overcurrent. In case of a fault, the PGOOD1 or PGOOD2 LED turns off, indicating that a flag has tripped due to an out of bounds condition. The Flags and Readings window displays the appropriate state of the PSU. Table 4. List of LEDs on the Evaluation Board LED D23 (Red) D24 (Red) D15 (Red) D12 (White) Description PGOOD1 signal (active low) PGOOD2 signal (active low) Indicates OrFET is turned on 12 V from auxiliary boost BOARD SETTINGS The board settings can be accessed from the main setup window (see Figure 9). 11739-008 8. UG-589 Figure 10. Different Icons on Dashboard for Loading and Saving .46r and .46b Files Rev. 0 | Page 11 of 48 Evaluation Board User Guide 11739-211 UG-589 Figure 11. Flags and Readings Window in GUI Showing the Entire Status of the PSU at Full Load Rev. 0 | Page 12 of 48 Evaluation Board User Guide UG-589 THEORY OF OPERATION DURING STARTUP The following steps briefly describe the start-up procedure of the ADP1046A and the power supply and operation of the state machine for the preprogrammed set of registers that are included in the design kit. 1. 2. 3. 4. After VDD (3.3 V) is applied to the ADP1046A, it takes approximately 20 µs for VCORE to reach 2.5 V. The digital core is now activated and the contents of the registers are downloaded in the EEPROM. The ADP1046A is now ready for operation. PSON is applied. The power supply begins the programmed soft start ramp of 80 ms only when the logical AND of hardware and software PSON is true (programmable). Because the soft start from precharge setting is active, the output voltage is sensed before the soft start ramp begins. Depending on the output voltage level of the effective soft start, the ramp is reduced by the proportional amount. The OrFET power-on is dependent on the voltage difference of VS1 and VS2. If the PSU is standalone, the OrFET gate turns on at the beginning of the soft start ramp when VS1 − VS2 is less than or equal to the programmed threshold in the GUI (see the OrFET Settings window in the GUI, which is accessed by clicking OrFET Settings in Figure 9). The output regulation is from VS3, and the normal filter is in operation. If the PSU is starting into a live bus already at 12 V, the OrFET turns on only at the end of the soft start ramp when the internal (or local) output voltage (VS1) climbs close to the regulation point and VS1 − VS2 is greater than the programmed threshold (threshold being a negative value ranging from −384 mV to 0 mV). Prior to this, the soft start 5. 6. filter is active, and the regulation/feedback path is through VS1. When the OrFET turns on (GATE pin signal is toggled), the feedback path is through VS3 and the compensation filter changes to normal mode or light load filter (depending on the load and light load threshold) in a time determined by the filter transitioning speed (programmable 1 to 32 switching cycles). The PSU is now running in a steady state and, depending on the load condition, one or both phases are active (second phase is on when the load current is greater than 14 A). PGOOD1 and PGOOD2 turn on after the programmed debounce. If a fault is activated during the soft start or steady state, the corresponding flag is set and the programmed action is taken, such as PSU disable and reenable after 1 sec, SR power-off, OrFET disable, and OUTAUX disable. DURING STEADY STATE The MOSFET drivers are powered using the auxiliary boost converter from the main 12 V when the output is in regulation before PSON is applied. The second phase is turned on only when the load current increases greater than 14 A. An asynchronous current detection on CS2 averages the load current every 75 µs, and the part exits light load mode. If a fault such as a undervoltage protection (UVP), overvoltage protection (OVP), CS2 overcurrent protection (OCP), or CS1 OCP occurs, the programmed action such as disable OrFET or disable PWMs takes place after the debounce period. If the PSU shuts down, the soft start ramp is initiated after the programmed delay. Rev. 0 | Page 13 of 48 UG-589 Evaluation Board User Guide CONFIGURING FLAG SETTINGS The Flag Settings window shows all the fault flags (if any) and the readings on one page (see Figure 12). The Get First Flag button (see Figure 11), which can be accessed by clicking the Monitor tab, determines the first flag that was set in case of a fault event. 11739-212 When a flag is triggered, the ADP1046A state machine waits for a programmable length of debounce time before taking any action. The response to each flag can be programmed individually. Click Setup and then Flag Settings (see Figure 9) to configure the flags. Figure 12. Flag Settings Window—Fault Configurations Rev. 0 | Page 14 of 48 Evaluation Board User Guide UG-589 PWM SETTINGS Click the Monitor tab and then PWM & SR Settings to access the PWM settings The ADP1046A has a fully programmable PWM setup that controls seven PWMs. Due to this flexibility, the IC can function in several different topologies, such as any isolated buck derived topology, push-pull, and flyback. Table 5. PWMs and Their Corresponding Switching Element The integrated volt-second balance feature is used as a current balancer of the two phases of the interleaved two-switch forward design. In other power conversion circuits such as full bridge, this feature can be used to eliminate the dc blocking capacitor. Switching Element Being Controlled Phase 1 primary switches Phase 1 synchronous rectifier Phase 1 freewheeling Phase 2 primary switches Phase 2 synchronous rectifier Phase 2 freewheeling Fan control 11739-213 Each PWM edge can be moved in 5 ns steps to achieve the appropriate dead time needed, and the maximum modulation limit sets the maximum duty cycle. This is displayed in Figure 13. PWM OUTA OUTB OUTC OUTD SR1 SR2 OUTAUX Figure 13. PWM Settings Window in the GUI Rev. 0 | Page 15 of 48 Evaluation Board User Guide 11739-013 UG-589 Figure 14. Fan Connection to Cool Heat Sink, Transformers, and Inductors FAN CONTROL The OUTAUX PWM is used to control an external fan connected to Connector J19. The average speed of the fan depends on the load. The PWM input to the fan is duty cycle modulated and is programmed with the main PWM output in a manner that provides the maximum speed at maximum load and vice versa. Note that the fan is not included in the kit. DYNAMIC PHASE SHEDDING AND STANDBY POWER Dynamic phase shedding is achieved using the light load feature of the ADP1046A. This setting is programmed to activate within 75 µs of detecting the output current via the CS2+ and CS2− pins. The IC is programmed to enter dual phase mode at 60% of the full load current and automatically turns off the PWMs for the second phase when the load current is less than approximately 54% of the full load current. Using an external microcontroller to communicate to the IC, the ADP1046A can also disable the synchronous rectifiers and save more power at no load by entering the pulse skipping mode, where the entire PWM pulse is skipped if the required duty cycle is less than the programmed value. Rev. 0 | Page 16 of 48 Evaluation Board User Guide UG-589 BOARD EVALUATION AND TEST DATA 11739-014 11739-016 STARTUP Figure 15. Startup at 350 V DC, No Load Green Trace: Output Voltage, 2 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div Figure 16. Startup at 350 V DC, 25 A Load (1 A/µs Slew Rate) Green Trace: Output Voltage, 2 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div 11739-017 11739-015 Figure 17. Startup at 385 V DC, No Load Green Trace: Output Voltage, 2 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div Figure 18. Startup at 385 V DC, 25 A Load (1 A/µs Slew Rate) Green Trace: Output Voltage, 2 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div Rev. 0 | Page 17 of 48 Evaluation Board User Guide 11739-020 11739-018 UG-589 Figure 21. Synchronous Rectifier During Startup at No Load Green Trace: Output Voltage, 2 V/div, 20 ms/div Blue Trace: Phase 1 Synchronous Rectifier (OUTC), 5 V/div, 20 ms/div Red Trace: Phase 2 Synchronous Rectifier (SR1), 5 V/div, 20 ms/div Yellow Trace: Load Current, 10 A/div, 20 ms/div Figure 20. Startup at 385 V DC, Load (1 A/µs Slew Rate) Yellow Trace: Phase 1 Drain Voltage on Q2, 100 V/div, 10 ms/div Red Trace: Phase 2 Drain Voltage on Q4, 100 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div Cursor Showing Phase 2 Enabled at 15 A 11739-021 11739-019 Figure 19. Startup at 350 V DC, Load (1 A/µs Slew Rate) Yellow Trace: Phase 1 Drain Voltage on Q2, 100 V/div, 10 ms/div Red Trace: Phase 2 Drain Voltage on Q4, 100 V/div, 10 ms/div Blue Trace: Load Current, 10 A/div, 10 ms/div Cursor Showing Phase 2 Enabled at 15 A Figure 22. Synchronous Rectifier During Startup at 25 A Load Green Trace: Output Voltage, 2 V/div, 20 ms/div Blue Trace: Phase 1 Synchronous Rectifier (OUTC), 5 V/div, 20 ms/div Red Trace: Phase 2 Synchronous Rectifier (SR1) Turning On at 15 A, 5 V/div, 20 ms/div Yellow Trace: Load Current, 10 A/div, 20 ms/div Rev. 0 | Page 18 of 48 Evaluation Board User Guide UG-589 Figure 25. Input RMS Current at 25 A Load, 350 V DC Yellow Trace: Primary Current, 1 A/div, 20 ms/div Green Trace: Output Voltage, 2 V/div, 20 ms/div Figure 24. Transformer Primary Waveform at 25 A Load, 400 V DC Red Trace: Voltage Across T1 Primary (Phase 1), 200 V/div, 2 µs/div Yellow Trace: Voltage Across T2 (Phase 2), 200 V/div, 2 µs/div 11739-025 11739-023 Figure 23. Transformer Primary Waveform at 25 A Load, 350 V DC Red Trace: Voltage Across T1 Primary (Phase 1), 200 V/div, 2 µs/div Yellow Trace: Voltage Across T2 (Phase 2), 200 V/div, 2 µs/div 11739-024 PRIMARY CURRENT 11739-022 TRANSFORMER PRIMARY WAVEFORM Figure 26. Input RMS Current at 25 A Load, 385 V DC Yellow Trace: Primary Current, 1 A/div, 20 ms/div Green Trace: Output Voltage, 2 V/div, 20 ms/div Rev. 0 | Page 19 of 48 UG-589 Evaluation Board User Guide Figure 27. Drain Voltage at 25 A Load, 385 V DC Red and Green Trace: Primary MOSFET Drain Voltage Across Q2 and Q4, 100 V/div, 2 µs/div Yellow Trace: CS1 Pin Voltage, 1 V/div, 2 µs/div 11739-028 11739-026 DRAIN VOLTAGE AND CURRENT Figure 29. CS1 Pin Voltage at 25 A Load, 350 V DC, Current Balancing Disabled Blue Trace: Voltage at CS1, 500 mV/div, 2 µs/div 11739-027 11739-029 CS1 PIN VOLTAGE AND CURRENT BALANCING OF PHASES Figure 30. CS1 Pin Voltage at 25 A Load, 385 V DC, Current Balancing Enabled Blue Trace: Voltage at CS1, 500 mV/div, 2 µs/div 11739-030 Figure 28. CS1 Pin Voltage at 25 A Load, 350 V DC, Current Balancing Enabled Blue Trace: Voltage at CS1, 500 mV/div, 2 µs/div Figure 31. CS1 Pin Voltage at 25 A Load, 385 V DC, Current Balancing Disabled Blue Trace: Voltage at CS1, 500 mV/div, 2 µs/div Rev. 0 | Page 20 of 48 Evaluation Board User Guide UG-589 Figure 34. Output Voltage at C65 (AC-Coupled), 350 V DC, 25 A, 50 mV/div, 5 µs/div, High Frequency Component 11739-032 11739-034 Figure 32. Synchronous Rectifier and Freewheeling MOSFET PIV at 25 A Load, 350 V DC Blue Trace: Synchronous Rectifier, 10 V/div, 500 ns/div Red Trace: Freewheeling FET Voltage, 20 V/div, 500 ns/div 11739-033 OUTPUT RIPPLE 11739-031 SYNCHRONOUS RECTIFIER PEAK INVERSE VOLTAGE (PIV) Figure 35. Output Voltage at C65 (AC-Coupled), 350 V DC, 25 A, 50 mV/div, 2 ms/div, Low Frequency Component 11739-035 Figure 33. Synchronous Rectifier and Freewheeling MOSFET PIV at 25 A Load, 385 V DC Blue Trace: Synchronous Rectifier, 10 V/div, 500 ns/div Red Trace: Freewheeling FET Voltage, 20 V/div, 500 ns/div Figure 36. Output Voltage at C65 (AC-Coupled), 385 V DC, 25 A, 50 mV/div, 5 µs/div, High Frequency Component Rev. 0 | Page 21 of 48 Evaluation Board User Guide Figure 40. Output Voltage Transient, 25% to 0% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 500 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 500 µs/div Figure 38. Output Voltage at 2700 µF Capacitor C10 (AC-Coupled), 385 V DC, 25 A, 100 mV/div, 5 µs/div, High Frequency Component 11739-040 11739-037 Figure 37. Output Voltage at C65 (AC-Coupled), 385 V DC, 25 A, 50 mV/div, 2 ms/div, Low Frequency Component 11739-039 11739-036 UG-589 Figure 41. Output Voltage Transient, 0% to 25% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 500 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 500 µs/div TRANSIENT VOLTAGE Figure 39. Output Voltage Transient, 25% to 0% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 500 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 500 µs/div 11739-041 11739-038 Load Step of 0% to 25% Figure 42. Output Voltage Transient, 0% to 25% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 500 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 500 µs/div Rev. 0 | Page 22 of 48 Evaluation Board User Guide UG-589 11739-042 11739-044 Load Step of 25% to 50% 11739-043 11739-045 Figure 45. Output Voltage Transient, 50% to 25% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Figure 43. Output Voltage Transient, 25% to 50% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Figure 46. Output Voltage Transient, 50% to 25% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Figure 44. Output Voltage Transient, 25% to 50% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Rev. 0 | Page 23 of 48 UG-589 Evaluation Board User Guide 11739-046 11739-048 Load Step of 50% to 75% 11739-047 11739-049 Figure 49. Output Voltage Transient, 75% to 50% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 1 ms/div Green Trace: Output Voltage (AC-Coupled), 200 mV/div, 1 ms/div Figure 47. Output Voltage Transient, 50% to 75% Load, 385 V DC, One Phase Only Yellow Trace: Load Current, 5 A/div, 1 ms/div Green Trace: Output Voltage (AC-Coupled), 200 mV/div, 1 ms/div Figure 50. Output Voltage Transient, 75% to 50% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Figure 48. Output Voltage Transient, 50% to 75% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 5 A/div, 200 µs/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 200 µs/div Rev. 0 | Page 24 of 48 Evaluation Board User Guide UG-589 Load Step of 75% to 100% Figure 51. Output Voltage Transient, 75% to 100% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 10 A/div, 1 ms/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 1 ms/div 11739-052 11739-050 PHASE SHEDDING TURN-ON/OFF TIME Figure 52. Output Voltage Transient, 100% to 75% Load, 385 V DC, Both Phases Active Yellow Trace: Load Current, 10A/div, 1 ms/div Green Trace: Output Voltage (AC-Coupled), 100 mV/div, 1 ms/div 11739-053 11739-051 Figure 53. Synchronous Rectifier PWM Turn-On Time During Load Step 10 A to 20 A Load, Blue Trace: Load Current, 10 A/div, 100 µs/div Green and Red Trace: Phase 2 Synchronous Rectifier and Freewheel PWMs (SR1 and SR2), 100 µs/div Figure 54. Synchronous Rectifier PWM Turn-On Time During Load Step 20 A to 10 A Load, Blue Trace: Load Current, 10 A/div, 100 µs/div Green and Red Trace: Phase 2 Synchronous Rectifier and Freewheel PWMs (SR1 and SR2), 100 µs/div Rev. 0 | Page 25 of 48 UG-589 Evaluation Board User Guide PRIMARY CURRENT DURING LOAD TRANSIENT 11739-054 11739-057 20 A to 10 A Load Step 10 A to 20 A Load Step Figure 58. Input Current During Load Step of 20 A to 10 A Showing Steady Balancing of Both Phases, Yellow Trace: Load Current, 5 A/div, 5 ms/div Red trace: Voltage at CS1 Pin, 500 mV/div, 5 ms/div Figure 56. Input Current During Load Step of 10 A to 20 A Showing Steady Balancing of Both Phases; Yellow Trace: Load Current, 5 A/div, 10 ms/div Red Trace: Voltage at CS1 Pin, 500 mV/div (20 µs/div Zoomed In) 11739-058 11739-055 Figure 55. Input Current During Load Step of 10 A to 20 A Yellow Trace: Load Current, 5 A/div, 10 ms/div Red Trace: Voltage at CS1 Pin, 500 mV/div (20 µs/div Zoomed In) 11739-056 Figure 59. Input Current During Load Step of 20 A to 10 A Showing Fade-Out of Phase 2 Yellow Trace: Load Current, 5 A/div, 5 ms/div Red Trace: Voltage at CS1 Pin, 500 mV/div (50 µs/div Zoomed In) Figure 57. Input Current During Load Step of 10 A to 20 A Showing Steady Balancing of Both Phases; Yellow Trace: Load Current, 5 A/div, 10 ms/div Red Trace: Voltage at CS1 Pin, 500 mV/div (20 µs/div Zoomed In) Rev. 0 | Page 26 of 48 Evaluation Board User Guide UG-589 DIGITAL CURRENT SHARING 11739-061 11739-059 OUTPUT OVERCURRENT PROTECTION Figure 62. OrFET Turn-On Green Trace: Output Voltage, 2 V/div, 20 ms/div Red Trace: GATE Signal Voltage, 2 V/div, 20 ms/div 11739-060 11739-062 Figure 60. Output Short-Circuit Protection, 130 ms Debounce on CS2, Response Set to Disable PSU and Reenable After 1 sec, Yellow Trace: Load Current, 20 A/div, 500 ms/div Green Trace: Output Voltage, 5 V/div, 500 ms/div Figure 63. OrFET Turn-On in Live Bus Green Trace: Output Voltage, 2 V/div, 20 ms/div Red Trace: GATE Signal Voltage, 2 V/div, 20 ms/div 11739-063 Figure 61. Output Short-Circuit Protection, 9.8 ms Debounce on CS2, Response Set to Disable PSU and Reenable After 1 sec, Yellow Trace: Load Current, 20 A/div, 500 ms/div Green Trace: Output Voltage, 5 V/div, 500 ms/div Figure 64. Digital Current Sharing with Load Step of 25 A, 42 A, 25 A Red and Yellow Traces: Output Currents of PSU1 and PSU2, 10 A/div, 500 ms/div Green and Blue Traces: SHAREo Pins of PSU1 and PSU2, 5 V/div, 20 ms/div Rev. 0 | Page 27 of 48 UG-589 Evaluation Board User Guide CLOSED-LOOP FREQUENCY RESPONSE A network analyzer (AP200) was used to test the bode plots of the system. Jumper J18 was replaced by a 20 Ω resistor, and a continuous noise signal of 400 mV was injected into the VS3+ pin before the voltage divider (R10 and R11 on daughter card). The operating condition was 385 V dc input and a load condition of 25 A. 80 70 180 140 PHASE 22 6 20 –2 –20 –10 –60 –18 –100 –26 –140 –34 –180 40 20 PHASE [B – A] (Degrees) 60 GAIN 50 30 100 14 60 385V DC 350V DC 10 0 0 5 10 15 20 25 LOAD (A) 11739-066 30 MAGNITUDE [B/A] (dB) 90 EFFICIENCY (%) 38 100 Figure 67. Efficiency vs. Load 100 90 80 –220 100k 10k FREQUENCY (Hz) 70 EFFICIENCY (%) 1k 11739-064 –42 100 Figure 65. Bode Plots, 25 A Load, 385 V DC Crossover Frequency = 7.36 kHz Phase Margin = 62.8° Gain Margin = 17 dB 60 50 40 30 EFFICIENCY 20 EFFICIENCY AT 25A 385V DC LIGHT LOAD ENABLED 385V DC LIGHT LOAD DISABLED 10 92.2 0 0 92.1 5 10 15 20 25 92.0 Figure 68. Efficiency vs. Load (with and Without Light Load Mode) CS1 LINEARITY 1.0 91.7 0.9 91.6 91.5 91.4 350 355 360 365 370 375 380 VIN (V DC) 385 Figure 66. Efficiency vs. VIN 390 395 400 GUI REPORTED CURRENT (A) 91.8 0.8 0.7 0.6 0.5 0.4 0.3 0.2 350V DC 385V DC 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 MEASUREMENT INPUT CURRENT (A) Figure 69. CS1 Linearity Rev. 0 | Page 28 of 48 0.9 1.0 11739-068 91.9 11739-065 EFFICIENCY (%) LOAD (A) 11739-067 92.3 Evaluation Board User Guide UG-589 ACSNS LINEARITY 12.05 410 12.04 OUTPUT VOLTAGE (V) 12.03 390 380 370 0A LOAD 1A LOAD 5A LOAD 10A LOAD 15A LOAD 20A LOAD 25A LOAD 350 340 350 355 360 365 370 375 380 385 MEASURED INPUT VOLTAGE 390 395 12.02 12.01 12.00 11.99 11.98 11.97 385V DC 350V DC 11.96 400 11.95 0 5 10 15 20 25 LOAD (A) 11739-072 360 11739-069 GUI REPORTED VOLTAGE 400 Figure 73. Output Voltage Regulation vs. Load Current Figure 70. ACSNS Linearity vs. Load CS2 LINEARITY THERMAL PERFORMANCE 30 GUI REPORTED CURRENT (A) 25 20 15 10 5 0 5 10 15 MEASURED CURRENT (A) 20 25 11739-274 0 11739-070 350V DC 385V DC Figure 71. CS2 Linearity vs. Load Figure 74. Thermal Performance at 385 V DC Input, 12 V, 25 A Output Load, No Air Flow, Soaking Time of 60 Minutes NO LOAD POWER 14 10 8 6 NO LOAD POWER (LIGHT LOAD MODE DISABLED) NO LOAD POWER (LIGHT LOAD MODE ENABLED) 4 2 0 340 350 360 370 380 390 INPUT VOLTAGE (V DC) 400 410 11739-071 STANDBY POWER (W) 12 Figure 72. No Load Power Rev. 0 | Page 29 of 48 G A T E D R IV E R S Phase2_FRwheel_DR Phase2_SR_DR Phase1_SR_DR Phase1_FRwheel_DR Phase1_switch_DR Phase2_switch_DR 1 6 1 T5 DA2320 4 3 5 2 400V rtn VSS VSS VSS 4 3 2 1 4 3 2 1 4 3 2 1 NC2 NC2 NC2 VSS 25V C404.7uF C394.7uF C364.7uF VDD OUTA INBOUTB PND INA NC1 U3 ADP3654 VDD OUTA INBOUTB PND INA NC1 U2 ADP3654 VDD OUTA INBOUTB PND INA NC1 U1 ADP3654 FIRST PHASE TP2 Vin- VSS TP8 Ph1 GATE TP14 DNI VIN- J2 Phase1_SW C5 10uF 25V 400V_IN 5 6 7 8 5 6 7 8 5 6 7 8 R221 R211 R201 R191 1 VCC+12V R7 0 R6 0 1 1 PGND 2 Phase2_FRwheel_SW VCC+12V Phase2_SR_SW 1 C67 2200pF 500VAC CSS C2 3300pF 100V R2 10 0.75W 2 R11 500 D6 D15 RED 2 1 SMAZ16 C131uF C23 0.1UF 1 2 1 VSS D7 1N4148 L1 C8 1000uF 16V TP15 VS1/CS2+ R58 10K R35 12K C4 3300pF 100V C15 10uF 25V 10uH 10A R4 10 0.75W 2 1 VS0 VS1 4 3 PGND C S 1 S E N S IN G R23 20 R17 0 D17 2.5V Zener D12 DNI CS1 Schottky MMSZ5222BT1G C20 1000pF TP22 CS1 VSS 7 6 8 5 7 6 8 5 R38 DNI T E M P E R A T U R E S E N S IN G 2 1 L2 C22 3300pF 100V R25 10 0.75W C16 10uF 25V 10uH 10A 4 3 O r F E T D R IV E R TP21 OrFET +3.3V DR_OR C14DNP R15 1 C32 DNP TP25 VS2/CS2- R29 DNP C3 3300pF 100V R3 10 0.75W R26 0 1 2W 1% 2W 1% 2W 1% R50.003 R10.003 2 2 2 AGND R16 0 DR_OR Q14 BSS123-7-F 100V 170MA 100V C191000pF 1 1 1 R8DNI n2n1 2 CS2- CS2+ C24 DNI R56 100 C12 0.1u TP30 Ph2XFR- L IN E F E E D - F O R W A R D PGND D10 1N4148 VS0 C66 10uF 25V VOUT 400V rtn C68 2200pF 500VAC C65 10uF 25V Phase2_SR_SW 6 7 8 Q6 IRFB4310ZPBF 100V 120A 1 Q3 STP12NM50 500V 11.5A TP29 T2 0197140-00R Ph2XFR+ 3 ETD29 4 1 5 400V rtn C21 0.22uF 630V connect this 400 rtn close to CT Dedicated and thick traces for YCAP POWER PACK VS2 1 Phase2_FRwheel_SW Q9 IRFB4310ZPBF 100V 120A SECOND PHASE R39 DNI GATE Q8SIR440DP 2 1 3 7 6 8 5 Q10SIR440DP 2 1 3 2 1 3 Q11 DNI RTD AGND R27 16.5k AGND RTD1 100k NTC VS1 C10 2700uF 16V OUTPUT CURRENT AND VOLTAGE SENSING, OrING FET CONTROL VS1 VS0 1 Q7 IRFB4310ZPBF 100V 120A Dedicated and thick traces for YCAP CSS R13 22K 3 4 5 6 7 8 Q5 IRFB4310ZPBF 100V 120A D8 T3 CST1-050LB MURS120 1 1 2 200V 1A Q2 STP12NM50 500V 11.5A Phase1_SR_SW VCC+12V 2 n1n2 T1 0197140-00R ETD29 1 400V rtn connect this 400 rtn close to CT C1 0.22uF 630V Phase1_SR_SW TP28 Ph1XFR- TP27 Ph1XFR+ D2 ES1J 600V Phase1_FRwheel_SW Phase1_SW VCC+12V Phase2_SW D1 ES1J 600V Q1 STP12NM50 500V 11.5A Phase1_FRwheel_SW 2 3 1 2 F1 5A 2 3 2 2 3 4 3 2 3 1 1 2 2 3 TP1 Vin+ 1 2 4 4 4 2 3 2 3 1 2 J20 1 1 R9 0 Q4 STP12NM50 500V R10 11.5A 0 1 D4 ES1J 600V ACSNS TP38 VS3- TP37 VS3+ 1 1 PGND VS3- VS3+ AGND CSS PGND R300 VOUT- J4 VOUT+ J3 T4 D9 CST1-050LB MURS120 1 1 2 200V 1A R18 22K 2 R57 DNP PGND C25 2200pF 2 2 J18 D3 ES1J 600V 1 1 2 2 3 4 3 J1 4 3 5 2 6 1 T6 DA2320 VSS TP10 Ph2 GATE TP17 DNI C6 10uF 25V Phase2_SW 11739-073 VIN+ 2 3 Rev. 0 | Page 30 of 48 2 Figure 75. Schematic—Power Stage 1 UG-589 Evaluation Board User Guide EVALUATION BOARD SCHEMATICS AND ARTWORK MAIN BOARD SCHEMATIC AGND VCC+12V VS3+ VS3+5V +3.3V VS1 VS2 GATE SR1 SR2 OUTX OUTD OUTC OUTB OUTA PGOOD2 PGOOD1 SHAREO SHAREI SDA SCL RTD FLAGIN PGOOD2 PGOOD1 PSON OUTAUX OUTD OUTC OUTB OUTA CS1 ACSNS SR1 SR2 CS2CS2+ PGND VS1 VS2 GATE VS3+ VS35V 3.3V AGND 12V J5ADP1043_DC TP7 PWMAUX TP24 SR2 TP18 SR1 TP13 PWMC TP6 PWMB TP5 PWMD R53 0 R52 0 R47 0 R43 0 R42 0 R41 0 Phase2_FRwheel_DR Phase2_SR_DR Phase1_FRwheel_DR Phase1_SR_DR Phase2_switch_DR Phase1_switch_DR PWM CONNECTIONS. PHASE 2 DISABLED IN LIGHT LOAD OUTX SR2 SR1 OUTC OUTB OUTD OUTA TP3 PWMA A DP1046A DA UGHTER CA RD CONNECTIONS AGND PGND CS2CS2+ CS1 ACSNS PSON SDA SCL RTD FLAGIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AGND J6 C31 0.1UF 1 2 2 C18 10uF D31 1N4148 1 PSON R62 100 2 VOUT 1 2 FAN CONTROL OUTX 1 2 J19 FLAGIN W H IT E D21 R37 10K C17 0.1UF AGND PGND Q13 BSS138 AGND R33 2k2 D16 1N4148 VCC+12V AGND TP9 FLAGIN C30 0.1UF VCC+12V AGND 12V EXTERNAL CONNECTOR 1 2 +12V D22 R36 2k2 GREEN +3.3V P S _ O N A N D F L A G _ IN C O N T R O L +3.3V SW1 PSON AGND AGND RED D24 R32 2k2 PGOOD2 LED INDICATORS RED D23 R31 2k2 PGOOD1 2 1 2 1 2 1 3 1 1 C29 1uF AGND C28 0.1UF R61 2 2 CURRENT SHARE SHAREI SHAREO J16 J17 1 1 C37 33p C34 33p 5 7 1 8 2 A0 SW1 SW2 C49 33pF R80 100 +3.3V 2 3 4 6 C45 33pF GND ADP1111AR-12 SET ILIM SENSE VIN U4 D27 1N4148 1 D30 1N4148 D28 1N4148 1 C26 10uF D26 1N4148 D11 MBRX130 D14 MURS120T3G 2 D29 1N4148 D25 1N4148 1 2 L3 VLCF4018T-330MR42-2 C35 100 33p 5V-12V BOOST SUPPLY FOR DRIVERS VS1 +5V R48 1 Ohm R60 C33 100 33p I2C INTERFACE AND FILTERING AGND SDA SCL +5V 1 2 1 2 1 2 1 2 2 1 2 Rev. 0 | Page 31 of 48 1 Figure 76. Schematic—Interfaces 2 SHAREO SHAREI 1 2 VS3- 1 2 ISHARE J7 C27 10uF TP11 +12V 1 2 3 4 J10 VCC+12V HDR1X4 1 2 3 4 Evaluation Board User Guide UG-589 INTERFACES SCHEMATIC 11739-074 Figure 77. Daughter Card Schematic NOTES: SHARE0 SHAREi SDA SCL RTD FLAGIN PGOOD2 PGOOD1 PSON OUTAUX OUTD OUTC OUTB OUTA CS1 ACSNS SR1 SR2 CS2- CS2+ VS1 VS2 GATE VS3+ VS3- +5V +3.3V 2 1: R3, R4, R5, R6, R7, R8, R10, R11,R20 ARE 0.1% 25ppm UNLESS OTHERWISE SPECIFIED. R3 R4 C10 C13 C16 C17 Low Side 4.99k 4.99k DNI DNI DNI DNI High Side 110k 110k DNI DNI 33pF 33pF 3 R19 = 10k 1% R33, R32 = 2.2k 1% R14, R15 = 2.2k 1% C26 = 330pF 50V X7R Short trace from pin 25 DGND to pin 2 AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 +12V ADD SHARE O/I PGOOD1/2 VCORE 4 Inverting Remote Voltage Sense Input None-Inverting Remote Voltage Sense Input OrFET Gate Drive Output OrFET Drain Sense Input Local Voltage Sense Input Power GND None Inverting Differential Current Sense Input Inverting Differential Current Sense Input Synchronous Rectifier Output Synchronous Rectifier Output AC Sense Input Primary Side Differential Current Sense Input PWM Output for Primary Side Switch PWM Output for Primary Side Switch PWM Output for Primary Side Switch PWM Output for Primary Side Switch Auxiliary PWM Output Power Supply On Input Power Good Output (Open Drain) Power Good Output (Open Drain) Flag Input Thermistor Input I2C Serial Clock Input I2C Serial Data Input and Output Analog Share Bus Feedback Pin Share Bus Output Voltage 29 C18 2200pF 100V R2 1k R1 27K C17 R4 DNI 4.99k C5 1.0uF 50V 2 5 6 8 7 R3 4.99k GND NR OUT1 OUT2 U2 ADP3303 SD ERR IN1 IN2 R6 1k R5 11k VS1 D2 1N4148 +5V C13 100pF C16 DNI CS2- +12V D1 1N4148 C10 100pF ACSNS 2 CS2+ R9 DNI 4 3 1 2 C8 0.1uF C2 DNI C1 DNI C15 1000pF C4 DNI C3 DNI R11 1k C12 4.7uF R21 5.1K +3.3V CS1 R8 1k R7 11k VS2 R10 11k D6 LED RED 8 7 6 5 4 3 2 1 C14 0.1uF VS3+ 2 PGND CS1 ACSNS CS2+ CS2- VS1 AGND VS2 C9 DNI C7 DNI VS3- 2 10k 28 2 1 32 VS3+ 9 3 RTD 28 3 C11 +3.3V U1 ADP1046A RTD PGND R13 0 Ohm 4 AGND DGND SCL SDA PSON FLAGIN PGOOD2 PGOOD1 SHAREO SHAREI 0.1uF C6 330nF 26 VCORE 30 2 1 33 PAD 31 VS3SR2 10 SR2 30 R20 RES OUTA 11 OUTA R29 2.2k 17 18 19 20 21 22 23 24 R33 2.2k 3 +3.3V R24 2.2k 2.2k 10k 29 R19 ADD OUTB 12 OUTB OUTC 13 OUTC SR1 SR1 27 VDD OUTD 14 OUTD 25 DGND GATE 16 GATE OUTAUX 15 OUTAUX 2.2k R15 R32 Analog GND J1 SDA SCL +5V R14 2.2k +3.3V SHAREi 4 3 2 1 SCL SDA PSON J7 FLAGIN PGOOD2 PGOOD1 SHARE0 11739-277 Rev. 0 | Page 32 of 48 1 UG-589 Evaluation Board User Guide DAUGHTER CARD SCHEMATIC Evaluation Board User Guide UG-589 11739-076 MAIN BOARD LAYOUT 11739-077 Figure 78. Layout, Top Silkscreen, 6.5 in × 5 in Figure 79. Layout, First Layer, 6.5 in × 5 in Rev. 0 | Page 33 of 48 Evaluation Board User Guide 11739-078 UG-589 11739-079 Figure 80. Layout, Second Layer, 6.5 in × 5 in Figure 81. Layout, Third Layer, 6.5 in × 5 in Rev. 0 | Page 34 of 48 UG-589 11739-080 Evaluation Board User Guide 11739-081 Figure 82. Layout, Bottom Layer, 6.5 in × 5 in Figure 83. Layout, Bottom Layer Silkscreen, 6.5 in × 5 in Rev. 0 | Page 35 of 48 UG-589 Evaluation Board User Guide 11739-082 DAUGHTER CARD LAYOUT 11739-083 Figure 84. Top Layer, 1.5 in × 1.08 in Figure 85. Ground Layer, 1.5 in × 1.08 in Rev. 0 | Page 36 of 48 UG-589 11739-084 Evaluation Board User Guide 11739-085 Figure 86. Power Layer, 1.5 in × 1.08 in Figure 87. Bottom Layer, 1.5 in × 1.08 in Rev. 0 | Page 37 of 48 UG-589 Evaluation Board User Guide BILL OF MATERIALS Table 6. Main Board Qty 2 4 Reference Designator C1, C21 C2, C3, C4, C22 7 1 C5, C6, C15, C16, C18, C26, C27 C8 3 1 C9, C13, C29 C10 2 C12, C17 1 1 C14 C19 1 4 1 2 3 3 3 1 1 2 4 1 3 3 1 1 1 1 1 3 7 1 4 1 C20 C23, C24, C32, C30 C25 C28, C31 C33, C34, C35 C36, C39, C40 C37, C45, C49 C65 C66 C67, C68 D1 to D4 D6 D7, D10, D16 D8, D9, D14 D11 D12 D17 D21 D22 D23, D24, D15 D25 to D31 F1 J1 to J4 J5 2 J6, J7 1 J10 3 J16 to J18 1 J19 3 J20 to J22 2 1 4 L1, L2 L3 Q1 to Q4 Description Capacitor metal polypro, 0.22 µF, 630 V, 3% SMD capacitor ceramic, 3300 pF, 100 V, 10%, X7R Capacitor ceramic 10 µF, 25 V, ±20%, X5R Manufacturer Panasonic AVX Corp Mfg Part No ECW-F6224HL 12101C332KAT2A Package Polypropylene 1210 Panasonic ECJ-4YB1E106M 1210 Capacitor 1000 µF, 16 V, ±20%, elect KZE red Capacitor ceramic 1 µF, 25 V, ±10%, X7R Capacitor 2700 µF, 16 V, ±20%, elect KZE radial SMD Capacitor ceramic, 0.1 µF, 50 V, 10%, X7R DNI Capacitor ceramic 1000 pF, 100 V, ±20%, X2Y SMD capacitor 1000 pF, 10%, 100 V, X7R Capacitor ceramic 100 nF, 50 V, 10%, X7R Capacitor ceramic 2200 pF, 50 V, 10%, X7R Capacitor ceramic 0.1 µF, 50 V, 10%, X7R Capacitor ceramic 33 pF, 50 V, ±5%, NP0 Capacitor ceramic 4.7 µF, 25 V, 10%, X5R Capacitor ceramic 33 pF, 50 V, ±5%, NP0 Capacitor ceramic 10 µF, 25 V, ±20%, X5R Capacitor ceramic 10 µF, 25 V, ±20%, X5R Capacitor ceramic 2200 pF, 500 V ac SMD diode fast REC, 1 A, 600 V Diode Zener 16 V, 1 W, 5% SMD diode switch, 100 V, 400 mW SMD diode super fast 200 V, 1 A SMD diode Schottky 30 V, 1 A SMD diode Schottky 10 V, 570 mW, DNI SMD diode Zener 2.5 V, 500 mW SMD LED white clear SMD LED green clear SMD LED super red clear SMD diode switch 100 V, 400 mW Holder PC fuse 5 mm low profile Connector jack banana UNINS panel MOU Connector RECEPT 30-position, 0.100 vertical dual Connector header 2-position, 3.96 mm vertical tin Connector header 4-position SGL PCB 30GOLD Connector header breakaway, 0.100, 2-position STR Connector header 2-position, 3.96 mm vertical tin Connector header breakaway, 0.100, 2-position straight Inductor 10 µH Power inductor 33 µH, 0.42 A MOSFET N-channel 500 V, 12 A United Chemicon EKZE160ELL102MJ20S Radial can Murata United Chemicon GCM21BR71E105KA56L EKZE160ELL272MK30S 0805 Radial can Murata GRM21BR71H104KA01L 0805 Johnson 101X18N102MV4E 1206 AVR Murata AVX Corp Murata Panasonic TDK Panasonic Panasonic Panasonic Vishay Any Diodes, Inc Diodes, Inc Diodes, Inc Micro Commercial Diodes, Inc On Semi Lumex Opto Chicago lighting Chicago lighting Diodes, Inc Keystone Emerson TE Connectivity 08051C102KAT2A GRM21BR71H104KA01L 08055C222KAT2A GRM21BR71H104KA01L ECJ-2VC1H330J C3225X7R1E475K ECJ-2VC1H330J ECJ-4YB1E106M ECJ-4YB1E106M VY1222M47Y5UQ63V0 ES1J-TP SMAZ16-13-F 1N4148W-7-F MURS120-13-F MBRX130-TP ZLLS410TA MMSZ5222BT1G SML-LX1206UWW-TR CMD15-21VGC/TR8 CMD15-21SRC/TR8 1N4148W-7-F 4527 108-0740-001 1-534206-5 0805 0805 0805 0805 0805 1210 0805 1210 1210 VY1 DO214AC MSB-403 SOD123 DO-2144AA SOD-123 SOD323 MSB-403 1206 1206 1206 SOD123 Fuseholder Banana jack F-socket-dual Molex 09-65-2028 FCI 69167-104HLF Header male TE Connectivity 4-102973-0-01 Header Molex 09-65-2028 TE Connectivity 4-102973-0-01 Header Precision Inc Coilcraft ST Microelectronics 019-7129-00R-Proto02 VLCF4018T-330MR42-2 STP12NM50 901 SMT TO-220 Rev. 0 | Page 38 of 48 Evaluation Board User Guide UG-589 Qty 4 Reference Designator Q5 to Q7, Q9 Description MOSFET N-channel 100 V, 120 A 3 1 1 1 1 2 Q8, Q10 Q11 Q13 Q14 RTD1 R1, R5 SMD MOSFET N-channel 20 V, 60 A DNI MOSFET N-channel 50 V, 220 mA SMD MOSFET N-channel 100 V, 170 mA Thermistor NTC 100 kΩ, 5%, RAD SMD resistor 0.003 Ω, 2 W, 1% 3 R2, R3, R4 SMD resistor 10.0 Ω, ¾ W, 5% 1 R5 SMD resistor 0.003 Ω, 2 W, 1% 2 1 2 1 2 4 5 2 1 1 4 1 2 13 R6, R7 R8 R9, R10 R11 R13, R18 R16, R17, R26, R30 R19 to R22, R15 R23, R27 R25 R29 R31, R32, R33, R36 R35 R37, R58 R30, R38 to R47, R52, R53 R48 R56, R57 R60, R61, R80 R62 SW1 TP1 to TP3 TP5 to TP11 TP13 to TP15 TP17, TP18, TP21 to T22 TP24, TP25, TP27 to T30 TP37, TP38 T1, T2 T3, T4 T5, T6 U1, U2, U3 U4 1 2 3 1 1 3 7 3 4 6 2 2 2 2 3 1 Manufacturer International Rectifier Vishay Mfg Part No IRFB4310ZPBF-ND Package TO-220 SIR440DP-T1-GE3 8-SOIC BSS138 BSS123-7-F B57891M0104J000 CSNL2512FT3L00 SOT-23 SOT23 B57891 2512 RMCF2010JT10R0 2010 CSNL2512FT3L00 2512 Resistor 0.0 Ω,¼ W, SMD DNI Resistor 0.0 Ω, ¼ W, SMD SMD resistor 500.0 Ω, 5% SMD resistor 22.0 kΩ, 1/8 W, 1% SMD resistor 0.0 Ω, 1/8 W, 5% SMD resistor 1.00 Ω, 1/8 W, 1% SMD resistor 20.0 Ω, 1/8 W, 1% SMD resistor 10.0 Ω, ¾ W, 5% Fairchild Diodes, Inc EPCOS Stackpole Electronics, Inc Stackpole Electronics, Inc Stackpole Electronics, Inc Any DNI Any Any Any Any Any Any Any Any DNI Any Any Any Any Any Any Any 1206 2512 1206 SMD resistor 2.20 kΩ, 1/8 W, 1% Resistor 12.0 k Ω, 1/8 W, 1% SMD SMD resistor 10.0 k Ω, 1/8 W, 1% SMD resistor 0.0 Ω, 1/8 W, 5% Any Any Any Any Any Any Any Any 0805 0805 0805 0805 SMD resistor 1.00 Ω, 1/8 W, 1% 0805 SMD resistor 100 Ω, 1/8 W, 1% Resistor 100 Ω, 1/8 W, 1% SMD SMD resistor 100 Ω, 1/8 W, 1% SW slide SPDT 30 V, 0.2 A PC mount Test point PC mini 0.040"D red Test point PC mini 0.040"D red Test point PC mini 0.040"D red Test point PC mini 0.040"D red Test point PC mini 0.040"D red Test point PC mini 0.040"D red Power switch mode transformers Current sensor Transformer gate drive High speed dual 4 A MOSFET driver IC multiconfiguration 12 V, 0.2 A Any Any Any Any E-Switch Keystone Keystone Keystone Keystone Keystone Keystone Precision Inc Coilcraft Coilcraft Analog Devices Analog Devices Any Any Any Any EG1218 5010 5010 5010 5010 5010 5010 0197140-00R CST1-050LB DA2320-ALB ADP3654A ADP1111ARZ-12 0805 0805 0805 0805 Slide-Sw TP-70 TP-70 TP-70 TP-70 TP-70 TP-70 ETD29 CST1 DA2320 8-lead SOIC 8-lead SOIC Rev. 0 | Page 39 of 48 0805 0805 0805 2010 UG-589 Evaluation Board User Guide Table 7. Daughter Card Qty 1 1 3 2 1 1 2 Reference C5 C6 C8, C11, C14 C10, C13 C12 C15 D1, D2 Part Description Capacitor ceramic 1.0 µF, 50 V, 10%, X7R Capacitor ceramic 330 pF, 10%, 100 V, X7R Capacitor ceramic 0.1 µF, 10%, 50 V, X7R Capacitor ceramic 100 pF, 10%, 100 V, X7R Capacitor ceramic 4.7 µF, ±10%, 10 V, X7R Capacitor ceramic 1000 pF, 10%, 100V, X7R Diode SW 150 mA, 100 V, 1N4148 1 1 D6 J1 1 J7 1 1 2 3 3 1 6 R1 R2 R3, R4 R5, R7, R10 R6, R8, R11 R13 R14, R15, R24, R29, R32, R33 R19, R20 R21 U1 U2 C1, C2, C3, C4, C7, C9, C16, C17, C18 LED super red clear 75 mA, 1.7 V, SMD Connector header female 30-position 0.1" DL tin, CON30 Connector header 4-position SGL PCB 30 gold, HEADER4X1 Resistor 27.0 kΩ, 1/10 W, 1%, SMD Resistor 1.00 kΩ, 1/8 W, 1%, SMD Resistor 4.99 kΩ, 1/10 W, 0.1%, ±25 ppm, SMD Resistor 11.0 kΩ, 1/10 W, 1%, ±25 ppm, SMD Resistor 1.00 kΩ, 1/10 W, 1%, ±25 ppm, SMD Resistor 0.0 Ω, 1/8 W, 5%, SMD Resistor 2.20 kΩ, 1/8 W, SMD 2 1 1 1 9 Resistor 10 kΩ, 1/8 W, 0.1%, SMD Resistor 5.10 kΩ, 1/8 W, SMD ADP1046A secondary side power supply controller ADP3303 IC LDO linear regulator 200 mA, 3.3 V DNI Rev. 0 | Page 40 of 48 Manufacture Murata AVX AVX Mfg Part No GRM32RR71H105KA01L 08051C331KAT2A 08055C104KAT2A TY TDK Micro Commercial Chicago Lighting Sullins Connector FCI LMK212B7475KG-T C2012X7R1A475M 1N4448W-TP Package 1210 0805 0805 0805 0805 0805 SOD-123 CMD15-21SRC/TR8 PPTC152LFBN-RC 1206 Fmal Socket 69167-104HLF Header 4POS Any Any Any Any Any Any Any Any Any Any Any Any Any Any 0805 0805 0805 0805 0805 0805 0805 Any Any Analog Devices Analog Devices Any Any ADP1046A ADP3303ARZ-3.3 0805 0805 32-lead LFCSP SOIC-8 Evaluation Board User Guide UG-589 APPENDIX I—TRANSFORMER SPECIFICATIONS Table 8. Transformer Specifications Min Typ Max Unit 4.25 7 Notes ETD 29 horizontal, 3F3 or equivalent Pin 1 and Pin 3 Pin 1 and Pin 3 with all other windings shorted Pin 1 and Pin 3 with all other windings open mH µH kHz 850 12, 13, 14 1 44T SPLIT PRIMARY 2 × 28AWG 4T, COPPER FOIL, 10mil 3 11739-086 Parameter Core and Bobbin Primary Inductance Leakage Inductance Resonant Frequency 8, 9, 10 Figure 88. Transformer Electrical Diagram 3 2 8, 9, 10 12, 13, 14 2 11739-087 1 Figure 89. Transformer Construction Diagram 13 12 11 10 9 8 7 32mm MAX 38mm MAX 5.08mm 25.4mm Figure 90. Transformer Bobbin Diagram Rev. 0 | Page 41 of 48 2 3 4 35mm MAX 5 6 11739 -088 1 UG-589 Evaluation Board User Guide APPENDIX II—OUTPUT INDUCTOR SPECIFICATIONS 4, 2 3, 1 11739-089 18T, 16AWG EQUIVALENT LITZ WIRE Figure 91. Output Inductor Electrical Diagram Table 9. Output Inductor Specifications Parameter Core Permeability (µo) Inductance DC Resistance Min 60 6.5 Typ Max Unit Notes 77351A7, KoolMu, Magnetics, Inc. 10 10 16 µH mΩ Maximum at no load, typical at full load Rev. 0 | Page 42 of 48 Evaluation Board User Guide UG-589 APPENDIX III—REGISTER FILE (ADP1046A_I2SF_032011.46R) Table 10. Register Address 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 Programmed Setting 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x61 0x03 0x33 0x30 0x03 0x20 0x80 0x45 0x23 0x00 0xE6 0x00 0x3AFC 0xC7EC 0xA0BC 0xA098 0xA000 0x5644 0x00 0x5C34 0x00 0x00 0x00 0x54 0x00 0x07 0x84 0xAD 0x00 0x00 0x00 0x6B 0xE3 0x46 0x04 0xF1 0x82 0x82 0x5A 0x26 0xA0 0x1C 0xA0 Name Fault Register 1 Fault Register 2 Fault Register 3 Fault Register 4 Latched Fault Register 1 Latched Fault Register 2 Latched Fault Register 3 Latched Fault Register 4 Fault Configuration Register 1 Fault Configuration Register 2 Fault Configuration Register 3 Fault Configuration Register 4 Fault Configuration Register 5 Fault Configuration Register 6 Flag configuration Soft start flag blank First Flag ID RTD current settings HF ADC reading CS1 value ACSNS value VS1 voltage value VS2 voltage value VS3 voltage value CS2 value CS2 × VS3 value RTD temperature value Read temperature RTD offset trim MSB Share bus value Modulation value Line impedance value RTD offset trim setting (LSB) CS1 gain trim CS1 accurate OCP limit CS2 gain trim CS2 analog offset trim CS2 digital offset trim CS2 accurate OCP limit CS1/CS2 fast OCP settings Volt-second balance gain setting Share bus bandwidth Share bus setting Temperature gain trim PSON/soft start settings PGOOD debounce and pin polarity setting Modulation limit OTP threshold OrFET VS3 voltage setting Rev. 0 | Page 43 of 48 UG-589 Register Address 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 Evaluation Board User Guide Programmed Setting 0x5A 0x0B 0x28 0xFF 0x07 0xDD 0x00 0x00 0x00 0x45 0x00 0x00 0x00 0x9B 0x1B 0x00 0x01 0x00 0x18 0x00 0x00 0x00 0x18 0x02 0x88 0x51 0xC0 0x2A 0x10 0x2A 0x18 0x2A 0x00 0x2A 0x18 0x2C 0x88 0x27 0x80 0x00 0x00 0x0A 0x08 0x00 0x7F 0xD2 0x22 0xF2 0xCA 0x3D 0x22 0xF2 0xCA Name VS1 overvoltage limit VS3 overvoltage limit VS1 undervoltage limit Line impedance limit Load line impedance Fast OVP comparator settings VS1 trim VS2 trim VS3 trim Light load disable setting Silicon revision ID Manufacturer ID Device ID OUTAUX switching frequency setting PWM switching frequency setting PWM1 positive edge timing PWM1 positive edge setting PWM1 negative edge timing PWM1 negative edge setting PWM2 positive edge timing PWM2 positive edge setting PWM2 negative edge timing PWM2 negative edge setting PWM3 positive edge timing PWM3 positive edge setting PWM3 negative edge timing PWM3 negative edge setting PWM4 positive edge timing PWM4 positive edge setting PWM4 negative edge timing PWM4 negative edge setting SR1 positive edge timing SR1 positive edge setting SR1 negative edge timing SR1 falling edge setting SR2 rising edge Timing SR2 rising edge setting SR2 falling edge timing SR2 falling edge setting PWM OUTAUX rising edge timing PWM OUTAUX rising edge setting PWM OUTAUX falling edge timing PWM OUTAUX falling edge setting PWM and SRx pin disable setting ACSNS gain trim Soft start and output voltage slew rate setting Normal mode digital filter LF gain setting Normal mode digital filter zero setting Normal mode digital filter pole setting Normal mode digital filter HF gain setting Light load digital filter LF gain setting Light load digital filter zero setting Light load digital filter pole setting Rev. 0 | Page 44 of 48 Evaluation Board User Guide Register Address 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Programmed Setting 0x3D 0x07 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x00 0x22 0xF2 0xCA 0x3D 0x04 0x30 0x02 0x00 0x00 0x0F 0x1F 0x60 0x34 0x00 0x00 UG-589 Name Light load digital filter HF gain setting Adaptive dead time threshold Dead Time 1 Dead Time 2 Dead Time 3 Dead Time 4 Dead Time 5 Dead Time 6 Dead Time 7 Dead time configuration Soft start digital filter LF gain setting Soft start digital filter zero setting Soft start digital filter pole setting Soft start digital filter HF gain setting Voltage line feedforward settings Volt-second balance OUTA/OUTB settings Volt-second balance OUTC/OUTD settings Volt-second balance SR1/SR2 Settings SR delay compensation Filter transitions PGOOD1 masking register PGOOD2 masking register Light load mode threshold settings Reserved GO byte Rev. 0 | Page 45 of 48 UG-589 Evaluation Board User Guide APPENDIX IV—BOARD FILE (ADP1046A_I2SF_032011.46B) Input Voltage = 385 V N1 = 44 N2 = 4 R (CS2) = 1.75 mOhm /* use 0.85mOhm for high side sensing with OrFET RDS_ON I (load) = 25 A R1 = 11 KOhm R2 = 1 KOhm C3 = 1 uF C4 = 1 uF N1 (CS1) = 1 N2 (CS1) = 50 R (CS1) = 20 Ohm ESR (L1) = 8 mOhm L1 = 10 uH C1 = 2700 uF ESR (C1) = 16 mOhm ESR (L2) = 10 mOhm L2 = 0 uH C2 = 1000 uF ESR (C2) = 23 mOhm R (Normal-Mode) (Load) = 0.48 Ohm R (Light-Load-Mode) (Load) = 2 Ohm Cap Across R1 & R2 = 0 "(1 = Yes: 0 = No)" Topology = 3 (0 = Full Bridge: 1 = Half Bridge: 2 = Two Switch Forward: 3 = Interleaved Two Switch Forward: 4 = Active Clamp Forward: 5 = Resonant Mode: 6 = Custom) Switches / Diodes = 0 (0 = Switches: 1 = Diodes) High Side / Low Side Sense (CS2) = 0 (1 = High-Side: 0 = Low-Side Sense) Second LC Stage = 1 (1 = Yes: 0 = No) CS1 Input Type = 0 (1 = AC: 0 = DC) R3 = 0 KOhm R4 = 0 KOhm PWM Main = 0 (0 = OUTA: 1 = OUTB: 2 = OUTC: 3 = OUTD: 4 = SR1: 5 = SR2: 6 = OUTAUX) C5 = 0 uF C6 = 0 uF R6 = 27 KOhm R7 = 1 KOhm Rev. 0 | Page 46 of 48 Evaluation Board User Guide UG-589 RELATED LINKS Resource ADP3654 ADP1111 ADP1046A ADP3303 Description Product Page, High Speed, Dual, 4 A MOSFET Driver Product Page, Micropower, Step-Up/Step-Down SW Regulator; Adjustable and Fixed 3.3 V, 5 V, 12 V Product Page, High Speed Converter Evaluation Platform (FPGA-based data capture kit) Product Page, High Accuracy anyCAP® 200 mA Low Dropout Linear Regulator Rev. 0 | Page 47 of 48 UG-589 Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11739-0-8/13(0) Rev. 0 | Page 48 of 48