ETC RTD2120

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Realtek
RTD2120
RTD2120
8051 Embedded Micro-Controller for Monitor
Fully Technology
Revision
Version 1.01
Last updated: 2005/11/30
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Realtek
RTD2120
Overview
This chip is the micro-processor of LCD monitor. It uses the design ware DW8051 of Synopsys
as the 8051 core of this chip and is compatible with other industry 8051 series. Also, 96Kbyte
FLASH with 8 bit bus is embedded in this chip which is licensed from TSMC 0.18um e-FLASH
process. Here we use the package of PLCC44/LQFP48 if we would like to have a discrete MCU
controller or we make a multi-chip package with our LCD monitor controller to form one chip
package to save the cost of package and PCB material.
Features
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Operating voltage range : 3.0V to 3.6V
8051 core, CPU operating frequency up to 50MHz
4 clocks per machine cycle
256-byte internal RAM
512-byte external data RAM, including 256-byte DDC RAM(128-byte x 2) and 256-byte
general purpose RAM
96K-byte flash memory, 64k for program and 32k for saving parameter
Two DDC ports compliant with VESA DDC1/2B/2Bi/CI
Three channels of PWM DAC with programable frequency from 100K to 100Hz
Watchdog timer with programmable interval
Three 16-bit counters/timers (T0, T1, and T2)
One PLL to provide programmable operating frequency and clock output, 2 clock output
ports
One full-duplex serial port
Six interrupt sources with 2 external interrupts
Four channels of 6-bit ADC
Hardware In System Programming(ISP) capability, no boot code required
Built-in Low voltage reset circuit
Embedded 1.8V regulator
Code protection
Available in 44-pin PLCC or 48-pin LQFP package
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RTD2120
Pin Configurations
P5.4/PWM4
P5.3/PWM3
P5.2/PWM2
P5.1/PWM1
P5.0/PWM0
NC
VCC
P1.0/T2
P1.1
P1.2
P1.3
6
5
4
3
2
1
44
43
42
41
40
P5.5/PWM5
7
39
P1.4
DSCL/P5.6
8
38
P1.5
DSDA/P5.7
9
37
P1.6
RST
10
36
P1.7
35
NC
34
NC
33
NC
ASCL/P3.0/RXD
NC
ASDA/P3.1/TXD
RTD2120S
44-PIN
PLCC
11
12
13
P3.2/INT0
14
32
VSYNC
P3.3/INT1
15
31
P6.7
P3.4/T0
16
30
P6.6/CLKO1
P3.5/T1
17
29
P6.5
18
19
20
21
22
23
24
25
26
27
28
P7.6/CLKO2
P7.7
XO
XI
VSS
NC
P6.0/ADC0
P6.1/ADC1
P6.2/ADC2
P6.3/ADC3
P6.4
P5.4/PWM4
P5.3/PWM3
P5.2/PWM2
P5.1/PWM1
P5.0/PWM0
NC
NC
VCC
P1.0/T2
P1.1
P1.2
P1.3
48
47
46
45
44
43
42
41
40
39
38
37
P5.5/PWM5
1
36
P1.4
DSCL/P5.6
2
35
P1.5
DSDA/P5.7
3
34
P1.6
RST
4
33
P1.7
32
NC
31
NC
30
NC
8
29
NC
P3.2/INT0
9
28
VSYNC
P3.3/INT1
10
27
P6.7
P3.4/T0
11
26
P6.6/CLKO1
P3.5/T1
12
25
P6.5
ASCL/P3.0/RXD
5
NC
6
NC
7
ASDA/P3.1/TXD
19
20
21
NC
NC
P6.0/ADC0
P6.1/ADC1
P6.4
18
VSS
24
17
XI
P6.3/ADC3
16
XO
23
15
P7.7
P6.2/ADC2
14
P7.6/CLKO2
22
13
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RTD2120L
48-PIN
LQFP
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Realtek
RTD2120
Block Diagram
Internal RAM
256 byt`e
DDC_RAM1 DDC_RAM2
128 byte
128 byte
TSMC FLASH
96K byte
F900-F97F
F980-F9FF
00-FF
IRAM_bus
Watch dog
timer
Routing
Box
FLASH/ISP
interface
I2C slave 1
Timer 2
I2C slave 2
Interrupt
Controller
Timer 0
MEM_bus
XFR
register
Serial
port 0
Timer 1
External RAM
Interface
DW8051_core
GPIO
External RAM
256 byte
F800-F8FF
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FF00
-FFFF
PWM
PWM
PWM
generator
generator
generator
6 bit ADC
6 bit ADC
6 bit ADC
6 bit ADC
PLL
(clock gen.)
XTAL
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RTD2120
Pin Description
Pin No.
Name
I/O
Description
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Input
General purpose I/O /
PWM0 output
General purpose I/O /
PWM1 output
General purpose I/O /
PWM2 output
General purpose I/O /
PWM3 output
General purpose I/O /
PWM4 output
General purpose I/O /
PWM5 output
General purpose I/O /
DVI DDC SCL
General purpose I/O /
DVI DDC SDA
High active RESET
2
44
P5.0/PWM0
I/O
3
45
P5.1/PWM1
I/O
--
1(P5.1)
4
46
P5.2/PWM2
I/O
--
1(P5.2)
5
47
P5.3/PWM3
I/O
--
1(P5.3)
6
48
P5.4/PWM4
I/O
--
1(P5.4)
7
1
P5.5/PWM5
I/O
--
1(P5.5)
8
2
P5.6/DSCL
I/O
--
1(P5.6)
9
3
P5.7/DSDA
I/O
--
1(P5.7)
10
4
RST
I
Down
0
11
5
ASCL/P3.0/RXD
I/O
--
1(ASCL)
Open
Drain
13
8
ASDA/P3.1/TXD
I/O
--
14
9
P3.2/INT0
I/O
--
15
10
P3.3/INT1
I/O
--
16
11
P3.4/T0
I/O
--
17
12
P3.5/T1
I/O
--
18
13
P7.6/CLKO2
I/O
Up
19
14
P7.7
I/O
Up
20
15
XO
O
--
--
--
Crystal out
21
16
XI
I
--
--
--
Crystal in
22
17
VSS
--
--
--
--
Ground
PLCC LQFP
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Default
output
value
1(P5.0)
Pin Type
Internal
Pull
Up/Down
--
ADC DDC SCL /
General purpose I/O /
RXD
1(ASDA)
Open
ADC DDC SDA /
General purpose I/O /
Drain
TXD
1(P3.2)
Standard General purpose I/O /
8051
External interrupt 0
1(P3.3)
Standard General purpose I/O /
External interrupt 1
8051
1(P3.4)
Standard General purpose I/O /
8051
Timer 0
1(P3.5)
Standard General purpose I/O /
8051
Timer 1
1
Push-Pull General purpose I/O /
Clock out 2
1
Push-Pull General purpose I/O
Realtek
Pin No.
PLCC LQFP
RTD2120
I/O
Description
24
20
P6.0/ADC0
I/O
25
21
P6.1/ADC1
I/O
Up
1(P6.1)
26
22
P6.2/ADC2
I/O
Up
1(P6.2)
27
23
P6.3/ADC3
I/O
Up
1(P6.3)
28
24
P6.4
I/O
Up
1
Push-Pull General purpose I/O /
ADC 0 input
Push-Pull General purpose I/O /
ADC 1 input
Push-Pull General purpose I/O /
ADC 2 input
Push-Pull General purpose I/O /
ADC 3 input
Push-Pull General purpose I/O
29
25
P6.5
I/O
Up
1
Push-Pull
30
26
P6.6/CLKO1
I/O
Up
1(P6.6)
31
27
P6.7
I/O
Up
1
32
28
VSYNC
I
Down
0
36
33
P1.7
I/O
--
1
37
34
P1.6
I/O
--
1
38
35
P1.5
I/O
--
1
39
36
P1.4
I/O
--
1
40
37
P1.3
I/O
--
1
41
38
P1.2
I/O
--
1
42
39
P1.1
I/O
--
1
43
40
P1.0/ET2
I/O
--
1(P1.0)
44
41
VCC
--
--
--
6
Default
output
value
1(P6.0)
Pin Type
Internal
Pull
Up/Down
Up
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Name
General purpose I/O
Push-Pull General purpose I/O /
Clock out 1
Push-Pull General purpose I/O
Input
VSYNC input
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O /
External Timer 2
8051/
Push-Pull
-Power
Realtek
RTD2120
DW8051 micro-processor
The DW8051 contained in RTD2120 is compatible with industry standard 803x/805x and
provides the following design features and enhancements to the standard 8051 microcontroller:
1. High speed architecture
Compared to standard 8051, the DW8051 processor core provides increased performance by
executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard
8051. The shortened bus timing improves the instruction execution rate for most instructions by a
factor of three over the standard 8051 architectures. The average speed improvement for the entire
instruction set is approximately 2.5X.
2. Stretch Memory Cycles
The stretch memory cycle feature enables application software to adjust the speed of data
memory access. The DW8051 can execute the MOVX instruction in as little as 2 instruction cycles.
However, it is sometimes desirable to stretch this value; for example, to access slow memory or slow
memory-mapped peripherals such as UARTs or LCDs.
The three LSBs of the Clock Control Register (at SFR location 8Eh) control the stretch value.
You can use stretch values between zero and seven. A stretch value of zero adds zero instruction
cycles, resulting in MOVX instructions executing in two instruction cycles. A stretch value of seven
adds seven instruction cycles, resulting in MOVX instructions executing in nine instruction cycles.
The stretch value can be changed dynamically under program control.
By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory
access, the software must set the stretch value to zero. The stretch value affects only data memory
access. The only way to reduce the speed of program memory (ROM) access is to use a slower clock.
3. Dual Data Pointers
The DW8051 employs dual data pointers to accelerate data memory block moves. The standard
8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The
DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h. It is not
necessary to modify code to use DPTR0.
The DW8051 adds a second data pointer (DPTR1) at SFR locations 84h and 85h. The SEL bit in
the DPTR Select register, DPS (SFR 86h), selects the active pointer. When SEL = 0, instructions that
use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use
DPL1 and DPH1. SEL is the bit 0 of SFR location 86h. No other bits of SFR location 86h are used.
All DPTR-related instructions use the currently selected data pointer. To switch the active
pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).
This requires only one instruction to switch from a source address to a destination address, saving
application code from having to save source and destination addresses when doing a block move.
Using dual data pointers provides significantly increased efficiency when moving large blocks of
data.
4. Timer Rate Control
One important difference exists between the RTD2120 and 80C32 regarding timers. The original
80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud
rates(depending on the mode). The RTD2120 architecture normally runs using 4 clocks per cycle.
However, in the area of timers, it will default to a 12 clock per cycle scheme on a reset. This allows
existing code with real–time dependencies such as baud rates to operate properly. If an application
needs higher speed timers or serial baud rates, the timers can be set to run at the 4 clock rate.
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RTD2120
The Clock Control register (CKCON – 8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control
bit is set to a zero, the device uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer zero. Note that
unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls
are independent.
Memory Organization
Internal Data memory
l 256 bytes of internal RAM
l 128 bytes of Special Function Register (SFR)
External Data memory
l 128 bytes of External Special Function Register (XFR)
l 256 bytes of DDCRAM(128-bytex2)
l 256 bytes of general purpose RAM
l 32k bytes of flash for EDID data and other parameters
External Program memory
l 64k bytes of flash for program memory
l The program content can not be read out unless user mass erase the flash first.
External Data Memory External Program Memory
Internal Data Memory
FF
FFFF
FFFF
Internal RAM
SFR
Indirect addressing
Direct addressing
XFR
FF00
80
7F
Unused
Internal RAM
Direct/Indirect
addressing
00
F9FF
F900
F8FF
F800
DDC_RAM1&2
flash 0~64K
General Purpose RAM
Unused
7FFF
flash 64~96K
0000
0000
Reset
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There are five reset sources in RTD2120, as described below:
RST pin
The external reset is high active and its pulse width must be larger than 8 clock cycles. The RST
pin can reset the whole chip of RTD2120.
Low voltage reset(LVR) and power on reset(POR)
The LVR and POR monitor the power status of RTD2120. The same as external reset, the LVR
and POR will reset the whole chip of RTD2120 when triggered.
Software reset
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RTD2120
To activate software reset, set FF39[1](SOF_RST). When software reset is triggered, it will reset
all modules except debug mode.
Watchdog timer(WDT)
The watchdog timer generates reset when it is overflowed. The watchdog timer resets almost the
same modules as software reset except itself(watchdog timer module).
In System Programing(ISP) reset
ISP reset will generate when entering ISP mode. Compared to Watchdog timer reset, ISP mode
resets almost the same modules as Watchdog timer except itself(ISP module).
Debug mode
module
RST pin
O
LVR & POR
O
Software reset
x
WDT reset
x
ISP reset
x
Note: O = Reset , x = No effect
Watchdog timer
module
O
O
O
x
x
CPU
O
O
O
O
O
ISP module and
other modules
O
O
O
O
x
Interrupt
Six interrupts are provided in RTD2120. Four of these are generated automatically by internal
operation: timer 0, timer 1, timer 2 and the serial port interrupt. The other two interrupts are triggered
by external pins: INT0 and INT1. Moreover, the DDC and IIC interrupts are connected to DW8051
INT 1 source as the following figure.
PIN_INT1_EN
pin INT1
A_WR_I
AWRI_EN
D_WR_I
DWRI_EN
128VS_I
VSI_EN
STOP_I
STOPI_EN
D_OUT_I
DOLI_EN
D_IN_I
DILI_EN
SUB_I
SUBI_EN
SLV_I
SLVI_EN
to DW8051 INT1
Timer/Counter
RTD2120 has three timers/counters: T0, T1 andT2. T0 and T1 are fully compatible to
timer/counter in standard 8051’s. Like timer2 in 8052, T2 of RTD2120 has three operating modes: 16bit timer/counter with capture, 16-bit auto-reload timer/counter and Baud rate generator. However, T2
of RTD2120 does not support “Timer2 output enable(T2OE)” and “downcount enable(DCEN)”. The
SFRs associated with Timer2 are listed below.
Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
T2CON TF2
EXF2
RCLK TCLK
EXEN2 TR2
C/T2
CP/RL2 C8h
RCAP2L
CAh
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RTD2120
RCAP2H
TL2
TH2
CBh
CCh
CDh
1. 16-bit timer/counter with capture
The Timer 2 capture mode is the same as the 16-bit timer/counter with the addition of the capture
registers and control signals. If EXEN2 = 0, Timer2 is a 16-bit timer/counter . The C/T2 bit determines
whether the 16-bit counter counts osc cycles (divided by 4 or 12), or high-to-low transitions on the
P1.0 pin. The TR2 bit enables the counter. When the count increments from FFFFh, the TF2 flag is set.
The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-low
transition on P1.1 when EXEN2 = 1 causes the Timer 2 value to be loaded into the capture registers
(RCAP2L and RCAP2H).
2. 16-bit timer/counter with auto-reload
When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode. Control of counter input is the
same as for the other 16-bit counter modes. When the count increments from FFFFh, Timer 2 sets the
TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting
value into the RCAP2L and RCAP2H registers. When Timer 2 is in auto-reload mode, a reload can be
forced by a high-to-low transition on the P1.1 pin, if enabled by EXEN2 = 1.
3. Baud rate generator
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in
serial mode 1 or 3. In baud rate generator mode, Timer 2 functions in auto-reload mode. However,
instead of setting the TF2 flag, the counter overflow generates a shift clock for the serial port function.
As in normal auto-reload mode, the overflow also causes the preloaded start value in the RCAP2L and
RCAP2H registers to be reloaded into the TL2 and TH2 registers. When either TCLK = 1 or RCLK =
1, Timer 2 is forced into auto-reload operation, regardless of the state of the CP/RL2 bit. When
operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode, a Timer 2 interrupt
can only be generated by a high-to-low transition on the P1.1 pin setting the EXF2 bit, and only if
enabled by EXEN2 = 1.
The counter time base in baud rate generator mode is osc/2. To use an external clock source,
set C/T2 to 1 and apply the desired clock source to the P1.0 pin.
Special Function Registers(SFR)
Register
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
Bit 7
Bit 6
0
0
SMOD0
TF1
TR1
GATE C/T
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Bit 5
0
1
TF0
M1
Bit 4
0
1
TR0
M0
Bit 3
0
GF1
IE1
GATE
10
Bit 2
0
GF0
IT1
C/T
Bit 1
0
STOP
IE0
M1
Bit 0
SEL
IDLE
IT0
M0
Reset
Value
(Hex)
07
00
00
00
00
00
30
00
00
00
Addr
(Hex)
81
82
83
84
85
86
87
88
89
8A
Realtek
RTD2120
Register
TL1
TH0
TH1
CKCON
SPC_FNC
P1_W
MPAGE
P1_R
SCON0
SBUF0
P2
IE
P3_W
P3_R
IP
T2CON
RCAP2L
RCAP2H
TL2
TH2
PSW
ACC
B
Bit 7
Bit 6
Bit 5
Bit 4
0
P1.7
0
P1.6
T2M
0
P1.5
T1M
0
P1.4
P1.7
SM0
P1.6
SM1
P1.5
SM2
P1.4
REN
P2.7
EA
P3.7
P3.7
1
TF2
P2.6
0
P3.6
P3.6
0
EXF2
P2.5
ET2
P3.5
P3.5
PT2
RCLK
P2.4
ES0
P3.4
P3.4
PS0
TCLK
CY
AC
F0
RS1
Reset
Bit 3
Bit 2
Bit 1
Bit 0 Value
(Hex)
00
00
00
T0M
MD2
MD1
MD0
01
0
0
0
WRS
00
P1.3
P1.2
P1.1
P1.0
FF
00
P1.3
P1.2
P1.1
P1.0
FF
TB8
RB8
TI
RI
00
00
P2.3
P2.2
P2.1
P2.0
00
ET1
EX1
ET0
EX0
00
P3.3
P3.2
P3.1
P3.0
FF
P3.3
P3.2
P3.1
P3.0
FF
PT1
PX1
PT0
PX0
80
EXEN2 TR2
C/T2
CP/RL2 00
00
00
00
00
RS0
OV
F1
P
00
00
00
External Special Function Registers(XFR)
Pin Share
Register::Pin_share0
Name
Bits
0xFF00
Read/Write
Reset State
Reserved
IIC2E
7
6
-R/W
0
1
PWM5E
5
R/W
0
PWM4E
4
R/W
0
PWM3E
3
R/W
0
PWM2E
2
R/W
0
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Comments
Reserved
0: Pin “P5.6/DSCL“ is P5.6, Pin
“P5.7/DSDA“ is P5.7
1: Pin “P5.6/DSCL“ is DSCL, Pin
“P5.7/DSDA“ is DSDA
0: Pin “P5.5/PWM5“ is P5.5
1: Pin “P5.5/PWM5“ is PWM5
0: Pin “P5.4/PWM4“ is P5.4
1: Pin “P5.4/PWM4“ is PWM4
0: Pin “P5.3/PWM3“ is P5.3
1: Pin “P5.3/PWM3“ is PWM3
0: Pin “P5.2/PWM2“ is P5.2
1: Pin “P5.2/PWM2“ is PWM2
11
Addr
(Hex)
8B
8C
8D
8E
8F
90
92
93
98
99
A0
A8
B0
B3
B8
C8
CA
CB
CC
CD
D0
E0
F0
Realtek
RTD2120
PWM1E
1
R/W
0
PWM0E
0
R/W
0
0: Pin “P5.1/PWM1“ is P5.1
1: Pin “P5.1/PWM1“ is PWM1
0: Pin “P5.0/PWM0“ is P5.0
1: Pin “P5.0/PWM0“ is PWM0
Register::Pin_share1
Name
Bits
0xFF01
Read/Write
Reset State
A_DDC_PIN_
SEL
7
R/W
0
D_DDC_PIN_
SEL
6
R/W
1
Reserved
PIN_INT1_E
N
5:3
2
-R/W
0
1
CLKO2E
1
R/W
1
IIC1E
0
R/W
1
0: ADC DDC ports are connected to
ASDA/ASCL
1: ADC DDC ports are connected to
DSDA/DSCL
0: DVI DDC ports are connected to
ASDA/ASCL
1: DVI DDC ports are connected to
DSDA/DSCL
Reserved
Pin “P3.3/INT1” connect to 8051 INT1
enable
0: disable
1: enable
when Pin “P3.3/INT1” is used as GPIO, this
bit must be 0.
0: Pin “P7.6/CLKO2“ is P7.6
1: Pin “P7.6/CLKO2“ is CLKO2
0: Pin “ASCL/P3.0/Rxd“ is P3.0/RXD, Pin
“ASDA/P3.1/Txd“ is P3.1/TXD
1: Pin “ASCL/P3.0/Rxd“ is ASCL, Pin
“ASDA/P3.1/Txd“ is ASDA
Register::Pin_share2
Name
0xFF02
Read/Write
Reset State
7:5
4
-R/W
0
0
ADC3E
3
R/W
0
ADC2E
2
R/W
0
ADC1E
1
R/W
0
ADC0E
0
R/W
0
Reserved
CLKO1E
Bits
Comments
Comments
Reserved
0: Pin “P6.6/CLKO1“ is P6.6
1: Pin “P6.6/CLKO1“ is CLKO1
0: Pin “P6.3/ADC3“ is P6.3
1: Pin “P6.3/ADC3“ is ADC3
0: Pin “P6.2/ADC2“ is P6.2
1: Pin “P6.2/ADC2“ is ADC2
0: Pin “P6.1/ADC1“ is P6.1
1: Pin “P6.1/ADC1“ is ADC1
0: Pin “P6.0/ADC0“ is P6.0
1: Pin “P6.0/ADC0“ is ADC0
I/O port
l
Each I/O pin of RTD2120 can drive/sink 4mA and the internal
drive/sink 10uA.
confidential
12
pull up/down circuit can
Realtek
l
RTD2120
All pins have 5V tolerance except four ADC pins: “P6.0/ADC0”, “P6.1/ADC1”, “P6.2/ADC2”
and ”P6.3/ADC3”.
Register::Port5_output_enable
Name
Bits
0xFF03
Read/Write
Reset State
P57OE
7
R/W
0
P56OE
6
R/W
0
P55OE
5
R/W
0
P54OE
4
R/W
0
P53OE
3
R/W
0
P52OE
2
R/W
0
P51OE
1
R/W
0
P50OE
0
R/W
0
0: P5.7 is input pin
1: P5.7 is output pin
0: P5.6 is input pin
1: P5.6 is output pin
0: P5.5 is input pin
1: P5.5 is output pin
0: P5.4 is input pin
1: P5.4 is output pin
0: P5.3 is input pin
1: P5.3 is output pin
0: P5.2 is input pin
1: P5.2 is output pin
0: P5.1 is input pin
1: P5.1 is output pin
0: P5.0 is input pin
1: P5.0 is output pin
Register::Port6_output_enable
Name
Bits
0xFF04
Read/Write
Reset State
P67OE
7
R/W
0
P66OE
6
R/W
0
P65OE
5
R/W
0
P64OE
4
R/W
0
P63OE
3
R/W
0
P62OE
2
R/W
0
P61OE
1
R/W
0
P60OE
0
R/W
0
P77OE
confidential
Bits
7
Comments
0: P6.7 is input pin
1: P6.7 is output pin
0: P6.6 is input pin
1: P6.6 is output pin
0: P6.5 is input pin
1: P6.5 is output pin
0: P6.4 is input pin
1: P6.4 is output pin
0: P6.3 is input pin
1: P6.3 is output pin
0: P6.2 is input pin
1: P6.2 is output pin
0: P6.1 is input pin
1: P6.1 is output pin
0: P6.0 is input pin
1: P6.0 is output pin
Register::Port7_output_enable
Name
Comments
0xFF05
Read/Write
Reset State
R/W
0
Comments
0: P7.7 is input pin
1: P7.7 is output pin
13
Realtek
RTD2120
P76OE
Reserved
6
R/W
0
5:0
--
0
0: P7.6 is input pin
1: P7.6 is output pin
Reserved
Register::Port1_pad_type
Name
Bits
0xFF09
Read/Write
Reset State
P17_PPO
7
R/W
0
P16_PPO
6
R/W
0
P15_PPO
5
R/W
0
P14_PPO
4
R/W
0
P13_PPO
3
R/W
0
P12_PPO
2
R/W
0
P11_PPO
1
R/W
0
P10_PPO
0
R/W
0
Comments
0:P1.7 is standar 8051 I/O
1:P1.7 is Push-Pull output
0:P1.6 is standar 8051 I/O
1:P1.6 is Push-Pull output
0:P1.5 is standar 8051 I/O
1:P1.5 is Push-Pull output
0:P1.4 is standar 8051 I/O
1:P1.4 is Push-Pull output
0:P1.3 is standar 8051 I/O
1:P1.3 is Push-Pull output
0:P1.2 is standar 8051 I/O
1:P1.2 is Push-Pull output
0:P1.1 is standar 8051 I/O
1:P1.1 is Push-Pull output
0:P1.0 is standar 8051 I/O
1:P1.0 is Push-Pull output
Register::Port50_pin_reg
Name
Bits
Reserved
P50
0xFF50
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.0
Register::Port51_pin_reg
Name
Bits
Reserved
P51
0xFF51
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.1
Register::Port52_pin_reg
Name
Reserved
P52
confidential
Bits
7:1
0
0xFF52
Read/Write
Reset State
-R/W
0
1
Comments
Reserved
Input/output value of P5.2
14
Realtek
RTD2120
Register::Port53_pin_reg
Name
Bits
Reserved
P53
0xFF53
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.3
Register::Port54_pin_reg
Name
Bits
Reserved
P54
0xFF54
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.4
Register::Port55_pin_reg
Name
Bits
Reserved
P55
0xFF55
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.5
Register::Port56_pin_reg
Name
Bits
Reserved
P56
0xFF56
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.6
Register::Port57_pin_reg
Name
Bits
Reserved
P57
0xFF57
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P5.7
Register::Port60_pin_reg
Name
Reserved
P60
confidential
Bits
7:1
0
0xFF58
Read/Write
Reset State
-R/W
0
1
Comments
Reserved
Input/output value of P6.0
15
Realtek
RTD2120
Register::Port61_pin_reg
Name
Bits
Reserved
P61
0xFF59
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.1
Register::Port62_pin_reg
Name
Bits
Reserved
P62
0xFF5A
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.2
Register::Port63_pin_reg
Name
Bits
Reserved
P63
0xFF5B
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.3
Register::Port64_pin_reg
Name
Bits
Reserved
P64
0xFF5C
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.4
Register::Port65_pin_reg
Name
Bits
Reserved
P65
0xFF5D
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.5
Register::Port66_pin_reg
Name
Reserved
P66
confidential
Bits
7:1
0
0xFF5E
Read/Write
Reset State
-R/W
0
1
Comments
Reserved
Input/output value of P6.6
16
Realtek
RTD2120
Register::Port67_pin_reg
Name
Bits
Reserved
P67
0xFF5F
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P6.7
Register::Port76_pin_reg
Name
Bits
Reserved
P76
0xFF60
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P7.6
Register::Port77_pin_reg
Name
Bits
Reserved
P77
0xFF61
Read/Write
Reset State
-R/W
0
1
7:1
0
Comments
Reserved
Input/output value of P7.7
Low Voltage Reset & Power on Reset
When the voltage level of power supply is below VLT, the low voltage reset(LVR) generates a chip
reset signal. After the power supply is above VUT(2.6V), LVR remain in reset state for 65536 X’tal
cycle(tPOR) to guarantee the chip exit reset condition.
VCC
VUT
VLT
VSS
tPOR
INTERNAL RESET
Register::LVR_control
Name
confidential
Bits
Read/Write
0xFF0A
Reset State
17
Comments
Realtek
RTD2120
VLT
7:6
R/W
0
low_threshold_voltage
00:1.8V
01:2.0V
10:2.2V
11:2.4V
reserved
5:0
--
00
reserved
A/D Converter
RTD2120 has embedded 4 channels of analog-to-digital converter. The ADCs convert analog
input voltage on the four A/D input pins to four 6-bit digital data stored in XFRs (FF0C~FF0F)
sequentially.
The ADC conversion range is from GND to VDD and the conversion is linear and monotonic with no
missing codes. To start A/D conversion, set STRT_ADC(FF0B[7]) = 1 and the conversion will be
complete in less than 12 us for 4 channels.
Register::ADC_control
Name
Bits
0xFF0B
Read/Write
Reset State
STRT_ADC
7
R/W
0
ADC_TEST
6
R/W
0
reserved
BIAS_ADJ
5:3
2:1
R/W
R/W
0
1
0
R/W
0
CK_SEL
Comments
Write 1 to start the A/D conversion. Auto
clear when A/D Conversion has been
completed.
0:A/D Conversion has been completed
1:A/D Conversion is not completed yet
0: Normal operation
1: ADC test mode
Reserved
ADC bias current adjust
00: 15u
01: 20u
10: 25u
11: 30u
Inverse ADC input clock pos/neg
0: pos
1: neg
Register::ADC0_convert_result
Name
Bits
ADC0_CONV
_DATA
reserved
0xFF0C
Read/Write
Reset State
7:2
R
00
1:0
--
00
Converted data of ADC0
Register::ADC1_convert_result
confidential
Comments
0xFF0D
18
Realtek
Name
RTD2120
Bits
ADC1_CONV
_DATA
reserved
Read/Write
Reset State
7:2
R
00
1:0
--
00
Comments
Converted data of ADC1
Register::ADC2_convert_result
Name
Bits
ADC2_CONV
_DATA
reserved
0xFF0E
Read/Write
Reset State
7:2
R
00
1:0
--
00
Comments
Converted data of ADC2
Register::ADC3_convert_result
Name
Bits
ADC3_CONV
_DATA
reserved
0xFF0F
Read/Write
Reset State
7:2
R
00
1:0
--
00
Comments
Converted data of ADC3
PLL
RTD2120 contains a PLL to make the whole chip operate at higher or lower speed for different
demands. After reset, RTD2120 uses crystal frequency as the system clock. User can program the PLL
to operate at the desired frequency and select system clock to PLL output by setting MCU_CLK_SEL.
RTD2120 will switch system clock to PLL output only when PLL is stable. Moreover, the divider is
glitch free so user can modify its value at any time.For normal operation, user must choose the crystal
whose frequency is between 11M and 27MHz . Besides, VCO frequency must be programmed
between 40M and 80MHz.
Note: Fvco = Xtal *(M/N) , where M=M_code+1, N=N_code+1.
MCU_CLK_SEL
DIV
Crystal
11M~27MHz
N
PFD
PUMP
VCO
40M~80MHz
M
confidential
19
MCU_CLK
Realtek
RTD2120
Register::PLL_control
Name
Bits
PLL_TEST
0xFF10
Read/Write
Reset State
7
R/W
0
DVSET
6:5
R/W
2
reserved
WD_RST
4:3
2
-R/W
0
0
WD_SET
1
R/W
0
PWDN_PLL
0
R/W
1
Comments
0: normal operation
1: test mode
Test mode vctrl set
11(0.8v)
10(1.0v)
01(1.2v)
00(1.4v)
0: No effect
1: Watchdog reset
0: No effect
1: Watchdog set
0: normal operation
1: power down PLL
Register::PLL_filter_control
Name
Bits
0xFF11
Read/Write
Reset State
reserved
VR
7:4
3:2
-R/W
0
0
PLL_IP
1:0
R/W
2
Comments
Loop filter resister
00: 16.32k
01: 19.12k
10: 21.92k
11: 24.72k
Charge Pump current
Ich=5u+bit[1]*10u+ bit[0]*5u
Register::PLL_M_N_DIV
Name
Bits
M_CODE
N_CODE
DIV
0xFF12
Read/Write
Reset State
R/W
R/W
R/W
1
0
0
7:4
3:2
1:0
Comments
Actual M = M_CODE+1
Actual N = N_CODE+1
Divider value
00:1
01:1/2
10:1/4
11:1/8
3.3V to 1.8V Regulator
max
typ
min
Input voltage(V)
Output current(mA)
confidential
2
80
20
Realtek
RTD2120
Register::regulator_control
Name
Bits
0xFF13
Read/Write
Reset State
reserved
VBG
7:5
4:3
-R/W
0
1
V_SEL
2:0
R/W
4
Comments
bandgap voltage select
00: 1.14v
01: 1.20v
10: 1.27v
11: 1.34v
Regulator 1.8v voltage select
000: 2.22
001: 2.12
010: 2.0
011: 1.9
100: 1.8
101: 1.7
110: 1.6
111: 1.5
DDC
RTD2120 has two DDC ports for both D-sub and DVI interface. The external master can access
DDC_RAM1(F900~F97F) through pin ASDL and ASDA by ADC DDC channel or DDC_RAM2
(F980~F9FF) through pin DSDL and DSDA by DVI DDC channel. Besides, the DDC_RAM1 and
DDC_RAM2 can be combined together to form a 256-bytes DDC_RAM for just ADC/DVI DDC
slave by setting DDCRAM_SIZ (FF26[1:0]).
The DDC of RTD2120 is compliant with VESA DDC standard. Both DDC slaves are in DDC1
mode after reset. When a high to low transition is detected on ASCL/DSCL pin, the DDC slave will
enter DDC2 transition mode. The DDC slave can revert to DDC1 mode if the SCL signal keeps
unchanged for 128 VSYNC periods in DDC2 transition mode and RVT_A_DDC1_EN /
RVT_D_DDC1_EN = 1. In DDC2 transition mode, the DDC slave will lock in DDC2 mode if a valid
control byte is received. Furthermore, user can force the DDC slave to operate DDC2 mode by setting
A_DDC2 / D_DDC2 = 1.
(Refers to the VESA “Display Data Channel Standard” for detailed)
Register::ADC_DDC_enable
Name
Bits
Read/Write
Reset State
A_DDC_ADD
R
7:5
R/W
0
reserved
A_DDC_W_S
TA
4
3
-R/W
0
0
A_DDCRAM
_W_EN
2
R/W
0
confidential
0xFF20
Comments
ADC DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is “A”)
Reserved
ADC DDC Write Status (for external DDC
access only)
It is cleared after write.
ADC DDC SRAM Write Enable (for
external DDC access only)
21
Realtek
RTD2120
A_DBN_EN
1
R/W
1
A_DDC_EN
0
R/W
0
0: Disable
1: Enable
ADC DDC De-bounce Enable
0: Disable
1: Enable (with crystal/4)
ADC DDC Channel Enable Bit
0: MCU access Enable
1: DDC channel Enable
Register::ADC_DDC_control
Name
Bits
0xFF21
Read/Write
Reset State
A_DBN_CLK
_SEL
7:6
R/W
0
A_STOP_DB
N_SEL
5:4
R/W
0
A_SYS_CK_S
EL
3
R/W
0
A_DDC2
2
R/W
0
RST_A_DDC
1
R/W
0
RVT_A_DDC
1_EN
0
R/W
0
Comments
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
De-bounce sda stage
0X: latch one stage
10: latch two stage
11: latch three stage
De-bounce reference clock
0: crystal clock
1: PLL clock
Force to ADC DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
Reset ADC DDC circuit
0: Normal operation
1: reset (auto cleared)
ADC DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
0: Disable
1: Enable
Register::DVI_DDC_enable
Name
Bits
0xFF23
Read/Write
Reset State
D_DDC_ADD
R
7:5
R/W
0
reserved
D_DDC_W_S
TA
4
3
-R/W
0
0
D_DDCRAM
_W_EN
2
R/W
0
D_DBN_EN
1
R/W
1
confidential
Comments
DVI DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is “A”)
Reserved
DVI DDC External Write Status (for external
DDC access only)
It is cleared after write.
DVI DDC External Write Enable (for
external DDC access only)
0: Disable
1: Enable
DVI DDC Debounce Enable
0: Disable
1: Enable (with crystal/4)
22
Realtek
RTD2120
D_DDC_EN
0
R/W
0
DVI DDC Channel Enable Switch
0: MCU access Enable
1: External DDC access Enable
Register::DVI_DDC_control
Name
Bits
0xFF24
Read/Write
Reset State
D_DBN_CLK
_SEL
7:6
R/W
0
D_STOP_DB
N_SEL
5:4
R/W
0
D_SYS_CK_S
EL
3
R/W
0
D_DDC2
2
R/W
0
RST_D_DDC
1
R/W
0
RVT_D_DDC
1_EN
0
R/W
0
Comments
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
De-bounce sda stage
0X: latch one stage
10: latch two stage
11: latch three stage
De-bounce reference clock
0: crystal clock
1: PLL clock
Force to DVI DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
Reset DVI DDC circuit
0: Normal operation
1: reset (auto cleared)
DVI DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
0: Disable
1: Enable
Register::DDCRAM_partition
Name
Bits
0xFF26
Read/Write
Reset State
reserved
VS_CON
7:3
2
-R/W
00
0
DDCRAM_SI
Z
1:0
R/W
0
Comments
Reserved
0: VSYNC signal is connected to ADC DDC
1: VSYNC signal is connected to DVI DDC
0x:ADC DDCRAM=128 byte, DVI
DDCRAM=128 byte
10:ADC DDCRAM=0 byte, DVI
DDCRAM=256 byte
11:ADC DDCRAM=256 byte, DVI
DDCRAM=0 byte
IIC Interface
Register::IIC_set_slave
confidential
0xFF27
23
Realtek
Name
RTD2120
Bits
IIC_ADDR
CH_SEL
Read/Write
Reset State
R/W
R/W
37
0
7:1
0
Comments
IIC Slave Address to decode
Channel Select
0: from ADC DDC
1: from DVI DDC
Register::IIC_sub_in
Name
Bits
IIC_SUB_AD
DR
0xFF28
Read/Write
Reset State
R
00
7:0
Comments
IIC Sub-Address Received
Register::IIC_data_in
Name
Bits
IIC_D_IN
0xFF29
Read/Write
Reset State
R
00
7:0
Comments
IIC data received
Register::IIC_data_out
Name
Bits
IIC_D_OUT
7:0
0xFF2A
Read/Write
Reset State
W
00
Comments
IIC data to be transmitted
Register::IIC_status
Name
Bits
0xFF2B
Read/Write
Reset State
A_WR_I
7
R/W
0
D_WR_I
6
R/W
0
128VS_I
5
R/W
0
STOP_I
4
R/W
0
D_OUT_I
3
R
0
D_IN_I
2
R
0
SUB_I
1
R/W
0
confidential
Comments
If ADC DDC detects a STOP condition in
write mode, this bit is set to “1” . Write 0 to
clear.
If DVI DDC detects a STOP condition in
write mode, this bit is set to “1” . Write 0 to
clear.
In DDC2 Transition mode, SCL idle for 128
VSYNC. Write 0 to clear.
If IIC detects a STOP condition(slave
address must match), this bit is set to “1” .
Write 0 to clear.
If IIC_DATA_OUT loaded to serial-outbyte, this bit is set to “1”. Write IIC_data_out
(FF2A) to clear.
If IIC_DATA_IN latched, this bit is set to
“1” . Read IIC_data_in (FF29) to clear.
If IIC_SUB latched, this bit is set to “1”
Write 0 to clear.
24
Realtek
RTD2120
SLV_I
0
R/W
0
If IIC_SLAVE latched, this bit is set to “1”
Write 0 to clear.
Register::IIC_IRQ_control
Name
Bits
0xFF2C
Read/Write
Reset State
AWI_EN
7
R/W
0
DWI_EN
6
R/W
0
128VSI_EN
5
R/W
0
STOPI_EN
4
R/W
0
DOI_EN
3
R/W
0
DII_EN
2
R/W
0
SUBI_EN
1
R/W
0
SLVI_EN
0
R/W
0
Comments
0: Disable the A_WR_I signal as an
interrupt source
1: Enable the A_WR_I signal as an interrupt
source
0: Disable the D_WR_I signal as an interrupt
source
1: Enable the D_WR_I signal as an interrupt
source
0: Disable the 128VS_I signal as an interrupt
source
1: Enable the 128VS_I signal as an interrupt
source
0: Disable the STOP_I signal as an interrupt
source
1: Enable the STOP_I signal as an interrupt
source
0: Disable the D_OUT_I signal as an
interrupt source
1: Enable the D_OUT_I signal as an
interrupt source
0: Disable the D_IN_I signal as an interrupt
source
1: Enable the D_IN_I signal as an interrupt
source
0: Disable the SUB_I signal as an interrupt
source
1: Enable the SUB_I signal as an interrupt
source
0: Disable the SLV_I signal as an interrupt
source
1: Enable the SLV_I signal as an interrupt
source
PWM
RTD2120 supports 3 channels of PWM DAC. The resolution of each PWM is 8-bit. PWM0,
PWM1and PWM2 are connected to DA0, DA1and DA2 respectively. Meanwhile, they can also be
connected to DA3, DA4 and DA5 which are programed via PWM_source_select register.
confidential
25
Realtek
RTD2120
PWM clock generator
OSC
1/2M
first stage
output
1/(N+1)
PLL
Register::PWM_clock_control
Name
Bits
0xFF30
Read/Write
Reset State
PWM_EN
7
R/W
0
PWM0_CK
6
R/W
0
PWM1_CK
5
R/W
0
PWM2_CK
4
R/W
0
PWM_CK_SE
L
3
R/W
0
2
1:0
-R/W
0
0
reserved
PWM_M
Comments
0: Disable PWM output
1: Enable PWM output
0: Select first stage output
1: Select second stage output
0: Select first stage output
1: Select second stage output
0: Select first stage output
1: Select second stage output
PWM clock generator input source
0: Crystal
1: PLL output
Reserved
PWM clock first stage divider
Register::PWM_divider_N
Name
Bits
PWM_N
7:0
0xFF31
Read/Write
Reset State
R/W
0
Comments
PWM clock Second stage divider
Register::PWM0_duty_width
Name
Bits
PWM0_DUT
7:0
0xFF32
Read/Write
Reset State
R/W
0
Comments
PWM0 duty width
Register::PWM1_duty_width
Name
PWM1_ DUT
confidential
Bits
7:0
second stage
output
0xFF33
Read/Write
Reset State
R/W
0
Comments
PWM1 duty width
26
Realtek
RTD2120
Register::PWM2_duty_width
Name
Bits
PWM2_ DUT
0xFF34
Read/Write
Reset State
R/W
0
7:0
Comments
PWM2 duty width
Register::PWM_source_select
Name
Bits
0xFF35
Read/Write
Reset State
reserved
PWM5_SEL
7:6
5:4
-R/W
0
2
PWM4_SEL
3:2
R/W
1
PWM3_SEL
1:0
R/W
0
Comments
Reserved
00: PWM5 is the same as PWM0
01: PWM5 is the same as PWM1
1x: PWM5 is the same as PWM2
00: PWM4 is the same as PWM0
01: PWM4 is the same as PWM1
1x: PWM4 is the same as PWM2
00: PWM3 is the same as PWM0
01: PWM3 is the same as PWM1
1x: PWM3 is the same as PWM2
Watchdog Timer
The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of
overflow is about 0.25 sec to 2 sec(assume crystal is 12MHz) and can be programmed via register
CNT1.
EN_WDT
WDT reset
CNT1
N
OSC
CNT2
3*28
CNT3
212
BY_CNT3
BY_CNT2
Register::WATCHDOG_timer
Name
Bits
0xFF36
Read/Write
Reset State
WDT_EN
7
R/W
0
CLR_WDT
6
W
0
BY_CNT2
5
R/W
0
BY_CNT3
4
R/W
0
confidential
Comments
0: Disable watchdog timer
1: Enable watchdog timer
0: No effect
1: Clear all counters of watchdog
Signal bypass counter2
0: signal pass through counter2
1: bypass
Signal bypass counter3
27
Realtek
reserved
CNT1
l
RTD2120
3
2:0
-R/W
0: signal pass through counter3
1: bypass
Reserved
The number N of counter1
000~111: 1~8
0
0
When ISP mode is enabled, watchdog will be disabled by hardware.
In System Programming
User can program the embedded 96K flash of RTD2120 by internal hardware without removing
RTD2120 from the system. RTD2120 utilizes DDC channel (ADC/DVI DDC) to communicate with
IIC host for ISP function. The ISP protocol is mainly compatible with DDC protocol. However, one
significant difference is that the LSB of 7-bit ISP address is the address auto increase bit. Thus, we can
improve the flash program speed.
Register::ISP_slave_address
Name
Bits
0xFF37
Read/Write
Reset State
ISP_ADDR
ISP_ADDR_I
NC_A
7:2
1
R/W
R
25
1
ISP_ADDR_I
NC_D
0
R
1
ISP slave address
Received LSB of ISP slave address of ADC
DDC channel
0: address is nonincrease
1: address is auto-increase
Received LSB of ISP slave address of DVI
DDC channel
0: address is nonincrease
1: address is auto-increase
Register::option
Name
Bits
Comments
0xFF38
Read/Write
Reset State
PORT_PIN_R
EG
7
R/W
1
reserved
MCU_CLK_S
EL
6:2
1
-R/W
0
0
CKOUT_SEL
0
R/W
0
Comments
port_pin_reg_n enable
0: port_pin_reg_n signal is disabled
1: port_pin_reg_n signal is enabled
Reserved
CPU clock source select
0: CPU clock is from Crystal divided by DIV
1: CPU clock is from PLL divided by DIV
CLKO1 & CLKO2 select
0: Select Crystal output
1: Select PLL output
Register::flash_page_erase_control
Name
confidential
Bits
Read/Write
0xFF39
Reset State
28
Comments
Realtek
PAGE_ADDR
reserved
SOF_RST
RTD2120
7:3
2
1
R/W
-R/W
00
0
0
0
R/W
0
STR_P_ERS
Flash page address from 64K to 96K
Reserved
Software reset for debug mode
0: No effect
1: reset RTD2120
Start page erase
0: page erase complete
1: write 1 to start page erase
Register::RAM_test
Name
Bits
0xFF3A
Read/Write
Reset State
reserved
EXT_RAM_B
IST
7:4
3
-R/W
0
0
EXT_RAM_S
TA
2
R
0
INT_RAM_BI
ST
1
R/W
0
INT_RAM_S
TA
0
R
0
confidential
Comments
Reserved
Start BIST function for MCU external RAM
(512 bytes)
0: finished and clear
1: start
Test result about MCU external RAM
0: fail
1: ok
Start BIST function for MCU internal RAM
(256 bytes)
0: finished and clear
1: start
Test result about MCU internal RAM
0: fail
1: ok
29
Realtek
RTD2120
Memory map of XFR
Register name Addr
Pin_share0
FF00
Pin_share1
FF01
Pin_share2
FF02
Port5_output_enabl
FF03
e
Port6_output_enabl
FF04
e
Port7_output_enabl
FF05
e
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IIC2E
PWM5E
PWM4E
PWM3E
PWM2E
PWM1E
PWM0E
CLKO1E
ADC3E
ADC2E
ADC1E
ADC0E
P56OE
P55OE
P54OE
P53OE
P52OE
P51OE
P50OE
P67OE
P66OE
P65OE
P64OE
P63OE
P62OE
P61OE
P60OE
P77OE
P76OE
FF09
LVR_control
FF0A
VLT
ADC_control
FF0B
STRT_AD ADC_TES
C
T
P17_PPO P16_PPO P15_PPO P14_PPO P13_PPO P12_PPO P11_PPO P10_PPO
FF0C
ADC0_CONV_DATA
FF0D
ADC1_CONV_DATA
FF0E
ADC2_CONV_DATA
FF0F
ADC3_CONV_DATA
PLL_control
FF10
PLL_filter_control
FF11
PLL_M_N_DIV
FF12
Regulator_control
FF13
ADC_DDC_enable FF20
PLL_TES
T
DVSET
M_CODE
BIAS_ADJ
CK_SEL
WD_RST WD_SET
PWDN_P
LL
VR
PLL_IP
N_CODE
DIV
VBG
V_SEL
A_DDCR
A_DDC_
AM_W_E
W_STA
N
A_SYS_C
A_DBN_CLK_SEL A_STOP_DBN_SEL
A_DDC2
K_SEL
D_DDCR
D_DDC_
D_DDC_ADDR
AM_W_E
W_STA
N
D_SYS_C
D_DBN_CLK_SEL D_STOP_DBN_SEL
D_DDC2
K_SEL
A_DDC_ADDR
ADC_DDC_contro
l
FF21
DVI_DDC_enable
FF23
DVI_DDC_control
FF24
DDCRAM_partitio
n
FF26
IIC_set_slave
FF27
IIC_sub_in
FF28
IIC_SUB_ADDR
IIC_data_in
FF29
IIC_D_IN
IIC_data_out
FF2A
IIC_D_OUT
confidential
IIC1E
P57OE
Port1_pad_type
ADC0_convert_res
ult
ADC1_convert_res
ult
ADC2_convert_res
ult
ADC3_convert_res
ult
PIN_INT1
CLKO2E
_EN
A_DDC_P D_DDC_P
IN_SEL IN_SEL
VS_CON
IIC_ADDR
30
A_DBN_E A_DDC_E
N
N
RST_A_D RVT_A_D
DC
DC1_EN
D_DBN_E D_DDC_E
N
N
RST_D_D RVT_D_D
DC
DC1_EN
DDCRAM_SIZ
CH_SEL
Realtek
RTD2120
Register name Addr
IIC_status
FF2B
IIC_IRQ_control
FF2C
PWM_clock_contr
ol
FF30
PWM_divider_N
FF31
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
A_WR_I
D_WR_I
128VS_I
STOP_I
D_OUT_I
D_IN_I
SUB_I
SLV_I
128VSI_E STOPI_E
DOI_EN
N
N
PWM0_C PWM1_C PWM2_C PWM_CK
PWM_EN
K
K
K
_SEL
AWI_EN DWI_EN
PWM0_DUT
PWM1_duty_width FF33
PWM1_DUT
PWM2_duty_width FF34
PWM2_DUT
FF35
FF36
ISP_slave_address
FF37
option
FF38
Flash_page_erase_
control
FF39
RAM_test
FF3A
confidential
SUBI_EN SLVI_EN
PWM_M
PWM_N
PWM0_duty_width FF32
PWM_source_sele
ct
WATCHDOG_tim
er
DII_EN
PWM5_SEL
WDT_EN
CLR_WD
BY_CNT2 BY_CNT3
T
ISP_ADDR
PORT_PI
N_REG
PAGE_ADDR
31
PWM4_SEL
PWM3_SEL
CNT1
ISP_ADD ISP_ADD
R_INC_A R_INC_D
MCU_CL CKOUT_
SEL
K_SEL
STR_P_E
SOF_RST
RS
EXT_RA EXT_RA INT_RAM INT_RAM
M_BIST M_STA
_BIST
_STA
Realtek
RTD2120
Electric Specification
DC Characteristics
Table 1 Absolute Maximum Ratings
PARAMETER
Voltage on VDD
Voltage on Input (5V tolerant)
Voltage on Output or I/O or NC
Electrostatic Discharge
Latch-Up
Ambient Operating Temperature
Storage temperature (plastic)
SYMBOL
VVDD
VIN1
V IO
VESD
ILA
TA
T STG
MIN
-1
-1
-1
TYP
MAX
4.6
5.5
4.6
±3.5
±100
70
125
UNITS
V
V
V
kV
mA
ºC
ºC
TYP
3.3
MAX
3.6
UNITS
V
mA
mA
V
V
V
V
Ω
Ω
μA
μA
0
-55
Table 2 DC Characteristics/Operating Condition
(0℃<TA<70℃; VDD = 3.3V ± 0.3V)
PARAMETER
Supply Voltage
Supply Current
Supply Current(Power Saving)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
I/O Pull-up resistance
I/O Pull-down resistance
Input Leakage Current(VI=VCC or GND)
Output Leakage Current(VO=VCC or GND)
confidential
SYMBOL
VDD
IVDD
I VDD
VOH
VOL
VIH
VIL
RPU
RPD
ILI
ILO
32
MIN
3.0
2.4
GND
2.0
100
50
-10
-20
VDD
0.5
0.8
300
150
+10
+20
Realtek
RTD2120
Mechanical Specification
48 Pin LQFP
L
L1
MILLIMETER
SYMBOL
MIN.
TYPICAL
A
INCH
MAX.
MIN.
TYPICAL
1.60
A1
0.05
A2
1.35
c
0.09
D
1.40
MAX
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
0.063
0.15
0.002
1.45
0.053
0.20
0.004
9.00 BSC
0.006
0.055
LEADFRAME MATERIAL
0.057
0.008
APPROVE
0.354 BSC
CHECK
DOC. NO.
VERSION
02
DWG NO
PKGC-065
D1
7.00 BSC
0.276 BSC
D2
5.50
0.217
DATE
E
9.00 BSC
0.354 BSC
REALTEK SEMICONDUCTOR CORP.
E1
7.00BSC
0.276 BSC
E2
b
5.50
0.17
e
0.20
0.217
0.27
0.007
0.50 BSC
0.008
0.011
0.0196 BSC
TH
0o
3.5o
7o
0o
3.5o
7o
L
0.45
0.60
0.75
0.018
0.0236
0.030
L1
confidential
1.00
0.0393
33
Realtek
RTD2120
44 Pin PLCC
Symbol
Dimension in inch
Min
Dimension in mm
Typ
Max
Min
Typ
－
－
Max
Note:
A
－
－
0.185
A1
0.020
－
－
0.51
A2
0.140
0.150
0.160
3.56
3.81
4.06
b1
0.020
0.028
0.036
0.51
0.71
0.91
b
0.014
0.018
0.022
0.36
0.46
0.56
3.Controlling dimension: Inch
4.General appearance spec. should be based
－
4.70
1.Dimension D & E do not include interlead
flash.
－
2.Dimension b1 does not include dambar
protrusion/intrusion.
c
0.006
0.010
0.014
0.15
0.25
0.36
D
0.646
0.653
0.660
16.41
16.59
16.74
E
0.646
0.653
0.660
16.41
16.59
16.74
TITLE : 44L PLCC (0.653" X 0.653")
LEADFRAME MATERIAL:
0.05 BSC
e
on final visual inspection spec.
1.27 BSC
PACKAGE OUTLINE DRAWING
GD
0.590
0.610
0.630
14.98
15.49
16.00
GE
0.590
0.610
0.630
14.98
15.49
16.00
HD
0.675
0.690
0.715
17.15
17.53
18.16
VERSION
1
HE
0.675
0.690
0.715
17.15
17.53
18.16
PAGE
17 OF 22
L
0.085
0.100
0.115
2.54
2.92
y
－
－
0.004
θ
0°
－
10°
confidential
2.16
－
0°
－
0.10
－
10°
APPROVE
CHECK
DOC. NO.
Albert Chang
DWG NO.
DATE
REALTEK SEMI-CONDUCTOR CO., LTD
34
510-ASS-P004
L044 - 1
MAR. 08.2005
Realtek
RTD2120
Ordering Information:
The available RTD2120 related products are listed below:
Part No.
RTD2120L
RTD2120S
RTD2120L-LF
RTD2120S-LF
confidential
Flash Size
96K byte
96K byte
96K byte
96K byte
Package Type
48 LQFP
44 PLCC
48 LQFP (lead free)
44 PLCC (lead free)
35