AN-1111 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Options for Minimizing Power Consumption When Using the ADuCM360/ADuCM361 By Mike Looney INTRODUCTION The ADuCM360 is a 32-bit ARM® Cortex™-M3-based microcontroller that integrates dual 24-bit sigma delta (Σ-Δ) analog-to-digital converters (ADCs), each with a fully programmable instrumentation amplifier on the front end. The ADuCM361 contains all of the features of the ADuCM360 except that it has a single 24-bit sigma delta ADC (ADC1). This application note describes many of the operational modes and clock options for these devices and details the power savings for each configuration. These microcontrollers target a wide range of applications including industrial control and instrumentation applications. In many of the target applications, reducing power consumption in the application is of the utmost importance. For example, for battery-powered applications, the lifetime of the battery can be extended by using the many operating modes and clock options on the ADuCM360/ADuCM361. In addition, in 4 mA to 20 mA loop-based applications where ADC performance is important, the ADuCM360/ADuCM361 ensure that the overall power consumption of the sensor module remains below 3.2 mA. For details regarding the specifications and operation of the ADuCM360/ADuCM361, refer to the latest datasheet and the UG-367 user guide. By maximizing the use of clock and power mode options, the average IDD consumed by the ADuCM360/ADuCM361 can be reduced to just 1 mA. This figure is achieved despite both the ADCs and the PGAs on the front end being enabled, the ARM Cortex-M3 processor being set to active mode, and the SPI buses and all timers being enabled. All IDD measurements in this document are typical values measured at ambient temperature (25°C) using a supply voltage of AVDD = IOVDD = 3.0 V. Rev. 0 | Page 1 of 12 AN-1111 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 I2C ....................................................................................................7 Revision History ............................................................................... 2 PWM ...............................................................................................8 Clock Control Registers ................................................................... 3 Reducing Analog IDD .....................................................................8 CLKCON0 ..................................................................................... 4 Power-Down Modes .........................................................................9 CLKSYSDIV ................................................................................... 4 Mode 1: MCUHALT Mode ..........................................................9 CLKDIS .......................................................................................... 4 Mode 2: PERHALT Mode ............................................................9 CLKCON1 ..................................................................................... 6 Mode 3: SYSHALT Mode .............................................................9 UART ............................................................................................. 7 Mode 4 and Mode 5: TOTALHALT and Hibernate Modes ....9 SPI0/SPI1 ....................................................................................... 7 REVISION HISTORY /12—Revision 0: Initial Version Rev. 0 | Page 2 of 12 Application Note AN-1111 CLOCK CONTROL REGISTERS The ADuCM360/ADuCM361 contain four main clock control registers: CLKCON0, CLKCON1, CLKDIS, and CLKSYSDIV. Figure 1 provides an overview of the ADuCM360/ADuCM361 clock structure. FCLK CORTEX HCLK FLASH/SRAM CLKSYSDIV[0] CLKCON0[2:0] CLKDIS[8] DMA HFOSC 16MHz OSC PCLK DIV2EN CLKDIS[7] CD DAC LFOSC CLKCON0[4:3] LFXTAL UCLK CLKDIS[5] CLKDIS[5] TIMER0 TIMER0CLK CLKDIS[6] CLKDIS[6] EXTCLK WATCHDOG TIMER WAKE-UP TIMER CLKDIS[0] SPI0CD CLKDIS[1] PWMCD CLKDIS[3] PCLK UCLK CLKDIS[1] CLKDIS[4] CLKDIS[3] UART UARTCLK TIMER1CLK CLKDIS[2] PWM PWMCLK CLKCON1[11:9] UARTCD SPI1 SPI1CLK CLKCON1[14:12] TIMER0CLK SPI0 SPI0CLK CLKCON1[5:3] SPI1CD CLKDIS[4] CLKDIS[0] CLKCON1[2:0] PCLK PCLK UCLK TIMER1 TIMER1CLK CLKDIS[2] CLKCON1[8:6] I2CCD I2C I2CCLK CLKDIS[9] ACLK Figure 1. Clock Structure for the ADuCM360 and ADuCM361 Rev. 0 | Page 3 of 12 ADC AN-1111 Application Note CLKCON0 3.0 UCLK serves as the main system clock for both the ADuCM360 and the ADuCM361. The CLKCON0[2:0] bits in Register CLKCON0 (Address 0x40002000) select the clock divide value for UCLK. The clock divide setting is important because a lower system clock setting reduces power consumption. 2.5 IDD (mA) 2.0 Figure 2 shows the IDD of the ADuCM360/ADuCM361 for different UCLK rates. In Figure 2, the processor is enabled but the ADCs are turned off. 1.5 6 0.5 5 0 0 2 4 6 FREQUENCY (MHz) IDD (mA) 4 Figure 3. Total IDD Using a 3.0 V Supply with the Processor Running, CLKSYSDIV = 0x1 3 Table 1. CLKSYSDIV Register Bit Descriptions Bit [7:1] 0 2 0 4 8 12 16 FREQUENCY (MHz) Name Reserved DIV2EN 09746-002 1 0 Figure 2. Total IDD Using a 3.0 V Supply with the Processor Running at Different Frequencies The CLKCON0[4:3] bits select the source of UCLK. The options include the following: • • • • 8 09746-003 1.0 Description These bits are reserved and are cleared to 0. Divide-by-two enable bit. By default, this bit is 1, meaning that the system clock is 8 MHz. Enable this bit in low power systems. 1: enable the system clock divider; the system clock is 8 MHz. 0: disable the system clock divider; the system clock is 16 MHz. CLKDIS The CLKDIS register (Address 0x4000202C) enables and disables the system clock to 10 different peripherals as shown in Figure 1. By default, all CLKDIS bits are set to 1 except Bit 9, the ADC system clock enable bit. This disables the system clock to 9 of the 10 of these peripherals after a reset. To use any one of these 10 peripherals, the user must clear the appropriate bit in the CLKDIS register to enable the peripheral system clock. Internal 16 MHz oscillator (default), HFOSC Internal 32 kHz oscillator, LFOSC External 32 kHz oscillator, LFXTAL External clock from P1.0, EXTCLK The 16 MHz internal oscillator (HFOSC), by default, uses 170 µA. If an application does not use any of the 10 peripherals, to minimize power, set the CLKDIS register bit for each unused peripheral to 1. CLKSYSDIV The CLKSYSDIV register (Address 0x40002444) enables and disables a divide-by-two (DIV2EN) option on the output of the 16 MHz oscillator. When CLKSYSDIV = 0x1, the system clock (UCLK) becomes 8 MHz; therefore, the entire chip is clocked from an 8 MHz clock source instead of 16 MHz. This has the effect of not only halving the dynamic current shown in Figure 3 but also reducing the background (static) current by 90 µA typically. Table 2 lists the IDD savings by disabling the clock to each peripheral by setting CLKCON1 = 0x00, assuming that CLKSYSDIV = 0x01 (system clock = 8 MHz). In most cases, by default, the peripheral is clocked by the system clock although the peripheral remains inactive. For more information about the CLKCON1 register, see the CLKCON1 section. Rev. 0 | Page 4 of 12 Application Note AN-1111 Table 2. CLKDIS Register Bit Descriptions Bit [15:10] 9 Name Reserved DISADCCLK 8 DISDMACLK 7 DISDACCLK 6 DIST1CLK 5 DIST0CLK 4 DISPWMCLK 3 DISUARTCLK 2 DISI2CCLK 1 DISSPI1CLK 0 DISSPI0CLK Description These bits are reserved and cleared to 0 1: disable ADC system clock 0: enable ADC system clock 1: disable DMA system clock 0: enable DMA system clock 1: disable DAC system clock 0: enable DAC system clock 1: disable Timer1 system clock 0: enable Timer1 system clock 1: disable Timer0 system clock 0: enable Timer0 system clock 1: disable PWM system clock 0: enable PWM system clock 1: disable UART clock 0: enable UART system clock 1: disable I2C system clock 0: enable I2C system clock 1: disable SPI1 system clock 0: enable SPI1 system clock 1: disable SPI0 system clock 0: enable SPI0 system clock IDD Reduction 75 µA reduction when set to 1. Note that ADC0 and ADC1 are in idle mode by default, ADCxMDE register = 0x0003. 40 µA reduction when set to 1. Note that by default, all DMA channels are disabled. 12 µA reduction when set to 1. Note that the DAC, by default, is in power-down mode, DACCON register = 0x200. 20 µA reduction when set to 1. 15 µA reduction when set to 1. 95 µA reduction when set to 1. 135 µA reduction when set to 1. 70 µA reduction when set to 1. 80 µA reduction when set to 1. 85 µA reduction when set to 1. Rev. 0 | Page 5 of 12 AN-1111 Application Note CLKCON1 The CLKCON1 register (Address 0x40002004) scales the clock to the main communications peripherals: SPI0, SPI1, UART, I2C, and PWM. By default, the CLKCON1 register is 0x0000. peripheral and set the clock frequency to its minimum value. For example, if the PWM is not used, set CLKCON1, Bits[14:12] to 111. Note that the peripheral clock must be equal to or faster than the processor clock speed. If the peripheral clock is slower than the processor clock speed, the peripheral is disabled. To minimize IDD when any of the SPI, I2C, UART, or PWM peripherals are unused in an application, disable the clock to that Table 3. CLKCON1 Register Bit Descriptions1 Bit 15 [14:12] Name Reserved PWMCD [11:9] UARTCD [8:6] I2CCD [5:3] SPI1CD [2:0] SPI0CD 1 Description Clock divide bits for PWM system clock 000: UCLK/1 = 16 MHz 001: UCLK/2 = 8 MHz 010: UCLK/4 = 4 MHz 011: UCLK/8 = 2 MHz 100: UCLK/16 = 1 MHz 101: UCLK/32 = 500 kHz 110: UCLK/64 = 250 kHz 111: UCLK/128 = 125 kHz Clock divide bits for UART system clock 000: UCLK/1 = 16 MHz 001: UCLK/2 = 8 MHz 010: UCLK/4 = 4 MHz 011: UCLK/8 = 2 MHz 100: UCLK/16 = 1 MHz 101: UCLK/32 = 500 kHz 110: UCLK/64 = 250 kHz 111: UCLK/128 = 125 kHz Clock divide bits for I2C system clock 000: UCLK/1 = 16 MHz 001: UCLK/2 = 8 MHz (the minimum value to support a 400 kHz I2C baud rate) 010: UCLK/4 = 4 MHz 011: UCLK/8 = 2 MHz (the minimum value to support a 100 kHz I2C baud rate) 100: UCLK/16 = 1 MHz 101: UCLK/32 = 500 kHz 110: UCLK/64 = 250 kHz 111: UCLK/128 = 125 kHz Clock divide bits for SPI1 system clock 000: UCLK/1 = 16 MHz 001: UCLK/2 = 8 MHz 010: UCLK/4 = 4 MHz 011: UCLK/8 = 2 MHz 100: UCLK/16 = 1 MHz 101: UCLK/32 = 500 kHz 110: UCLK/64 = 250 kHz 111: UCLK/128 = 125 kHz Clock divide bits for SPI0 system clock 000: UCLK/1 = 16 MHz 001: UCLK/2 = 8 MHz 010: UCLK/4 = 4 MHz 011: UCLK/8 = 2 MHz 100: UCLK/16 = 1 MHz 101: UCLK/32 = 500 kHz 110: UCLK/64 = 250 kHz 111: UCLK/128 = 125 kHz Calculations are for UCLK = 16 MHz with CLKSYSDIV[0] = 0; an additional divide-by-two is required when CLKSYSDIV[0] is set to 1. Rev. 0 | Page 6 of 12 Application Note AN-1111 Master Mode UART To minimize the current drawn by the UART, use the lowest possible clock setting that allows the application to comply with the required UART baud rate setting. Changing the clock frequency to the UART likewise requires recalculating the correct values that are entered into the COMDIV register, which is the register that controls the baud rate. SPI Clock Rate = SPI Clock/(2 × (1 + SPIxDIV)) where SPI Clock is the divided system clock to the SPI set up by the CLKSYSDIV and CLKCON1 registers. To calculate the baud rate, use the following equation: Baud Rate = UARTCLK ÷ (2 × 16 × COMDIV) ÷ (M + N ÷ 2048) Slave Mode In slave mode, the master on the SPI bus controls the baud rate. However, the internal ADuCM360/ADuCM361 SPI clock rate, set by the CLKCON1 register, must be at least four times faster than the master SPI output clock (host clock). where: COMDIV = 1 to 65,536. M = 1 to 3. N = 0 to 2047. UARTCLK is the divided system clock to the UART set up by the CLKSYSDIV and CLKCON1 registers. Figure 4 shows the possible IDD savings when the UART clock is reduced. 250 200 UART IDD (µA) Changing the clock frequency to the SPI while in SPI master mode requires recalculating the correct values to be entered into the SPIxDIV register (where x is 0 for SPI0 and 1 for SPI1), which is the register that controls the SPI clock rate. Calculate the baud rate as follows: I2C To minimize the current drawn by the I2C block, use the lowest possible clock setting that allows the application to comply with the required I2C clock rate. Figure 6 shows the possible IDD savings when the I2C clock is reduced. Note that these figures do not include the IDD from the external pull-up resistors on the SDA and SCL pins. The minimum value to support a 400 kHz I2C baud rate is an I2C system clock of 8 MHz. Whereas, the minimum value to support a 100 kHz I2C baud rate is an I2C system clock of 2 MHz. 150 100 90 80 50 70 2 4 6 8 10 12 14 16 FREQUENCY (MHz) I2C IDD (µA) Figure 4. UART IDD vs. UART Clock Frequency SPI0/SPI1 50 40 30 To minimize the current drawn by the SPI block, use the lowest possible clock setting that allows the application to comply with the required SPI clock rate. Figure 5 shows the IDD savings from each SPI block when a reduced clock is selected. 20 10 0 0 2 6 8 10 12 14 16 Figure 6. IDD vs. I2C System Clock Frequency 80 Master Mode 70 Changing the clock frequency to the I2C block while in I2C master mode requires recalculating the correct values for entering data to the I2CDIV register, which is the register that controls the I2C clock rate. The I2CDIV is a 16-bit register containing two 8-bit values, high and low. This is set up according to the formula: 60 50 40 30 fI2CSCL = fPERIPH/(Low + High + 3) 20 10 0 0 2 4 6 8 10 12 14 FREQUENCY (MHz) Figure 5. IDD vs. SPI Clock Frequency for Each SPI Port 16 09746-005 SPI IDD (µA) 4 FREQUENCY (MHz) 90 09746-006 0 09746-004 60 0 where: fPERIPH = is the I2C peripheral clock. fPERIPH = fUCLK/(CLKSYSDIV × I2CCD) where UCLK is the system clock, 16 MHz;. CLKSYSDIV is 1 or 2, depending on the CLKSYSDIV[0] bit setting; and I2CCD is the clock divide value Rev. 0 | Page 7 of 12 AN-1111 Application Note It is important to consider the following information when reducing the analog IDD: and is set by the CLKCON1[8:6] bits from 1 to 7. Low = the low period of the clock, I2CDIV[7:0] = (REQD_LOW_TIME/UCLK_PERIOD) − 1. High = the high period of the clock, I2CDIV[15:8] = (REQD_HIGH_TIME/UCLK_PERIOD) – 2. • Thus, for 100 kHz operation with an I2C peripheral clock of 16 MHz, the low and high bit values are as follows: • Low = 0x4F High = 0x4E For 400 kHz operation, the low and high bit values are as follows: • Low = 0x13 High = 0x12 • Slave Mode In slave mode, the master on the I2C bus controls the baud rate. • PWM To minimize the current drawn by the PWM block, use the lowest possible clock setting that allows the application to meet the required PWM duty cycle and output frequency. Figure 7 shows the possible IDD savings when reducing the PWM clock. • 120 Table 4. Breakdown of Analog Peripherals IDD 100 80 PWM IDD (µA) The ADC update rate selected by the ADCxFLT registers does not affect the IDD consumption. Regardless of the ADC filter update rate, the ADC modulator always works with a 500 kHz clock source. When the PGA is enabled and the gain is greater than or equal to 2, the ADC input buffers are not required; therefore, Register ADCxCON, Bits[17:14] can be set to 1111. This setting saves 70 µA per ADC. When the PGA is set to a gain greater than or equal to 32, an additional 60 µA is consumed by the PGA compared to gains of less than 32. When the PGA is disabled (gain = 1), enable the ADC input buffers, unless an external buffer is provided. The external reference input buffers consume 60 µA each. If the external reference negative voltage is connected to AGND, the negative input buffer can be bypassed and powered by setting Register ADCxCFG, Bits[1:0] = 11. Register IEXCCON, Bit 2 = 0 disables the Excitation Current Source 0. Similarly, Register IEXCCON, Bit 5 = 0 disables Excitation Current Source 1. When only one excitation current is used, disable the other one to save power. 60 40 0 0 2 4 6 8 10 12 FREQUENCY (MHz) 14 16 09746-007 20 Figure 7. IDD vs. PWM Clock Frequency REDUCING ANALOG IDD Table 4 lists some of the options when configuring ADC0 and ADC1 on the ADuCM360/ADuCM361, and the associated IDD values for each option. As Table 4 shows, the analog IDD can be minimized by carefully configuring the ADCs and the DAC. Peripheral Name Modulator Gain = 2, 4, 8, or 16 (PGA Total) Gain = 32, 64, or 128 (PGA Total) ADC Positive Input Buffer ADC Negative Input Buffer External Reference Buffer Positive Negative Excitation Current (Excluding Output Current) Source 0 Source 1 DAC Rev. 0 | Page 8 of 12 ADC0 70 µA 130 µA ADC1 70 µA 130 µA 190 µA 190 µA 35 µA 35 µA 35 µA 35 µA Common to Both ADCs Other 60 µA 60 µA 25 µA 25 µA 50 µA Application Note AN-1111 POWER-DOWN MODES The ADuCM360/ADuCM361 provide five power-down levels. When a user is deciding on which power-down mode best suits an application, there is a trade-off among the IDD savings, the wake-up time, and which of the peripherals needs to be active. The IDD savings between Mode 3 and Mode 1 or between Mode 3 and Mode 2 are minimal at FCLK rates ≤ 1 MHz. 1600 In Mode 1, Mode 2, and Mode 3, it is possible for peripherals to continue operating by using the DMA operation while the CPU is powered down. To achieve this, either ADC1 or ADC0 must be enabled for DMA operation. Use a DMA complete interrupt to awaken the device from Mode 1, Mode 2, or Mode 3. 1200 IDD (µA) MODE 2 The IDD figures in the following sections assume that the ADC DMA mode is not enabled. MODE 1 800 MODE 3 400 In Mode 1, HCLK is off and the ARM Cortex-M3 processor is in sleep mode. The wake-up time is three to five times FCLK, where FCLK is the clock selected by the CLKCON0[2:0] bits. 0 0 4 8 12 16 FREQUENCY (MHz) 09746-008 MODE 1: MCUHALT MODE Figure 8. Power-Down IDD for Mode 1, Mode 2, and Mode 3 vs. FCLK, CLKSYSDIV = 0x0 Calculate the expected IDD in Mode 1 as follows: When Register CLKSYSDIV = 0x0 IDD [µA] = 50 × FCLK + 355 900 When Register CLKSYSDIV = 0x1 IDD [µA] = 50 × FCLK + 435 600 MODE 2 MODE1 IDD (µA) MODE 2: PERHALT MODE In Mode 2, PCLK is off and the ARM Cortex-M3 processor is in sleep mode. The wake-up time is three to five times FCLK, where FCLK is the clock selected by the CLKCON0[2:0] bits. MODE 3 300 When Register CLKSYSDIV = 0x0 IDD [µA] = 60 × FCLK + 345 0 0 When Register CLKSYSDIV = 0x1 IDD [µA] = 60 × FCLK + 425 2 4 6 FREQUENCY (MHz) 8 09746-009 Calculate the expected IDD in Mode 2 as follows: Figure 9. Power-Down IDD for Mode 1, Mode 2, and Mode 3 vs. FCLK, CLKSYSDIV = 0x1 The IDD savings between Mode 1 and Mode 2 are minimal. MODE 3: SYSHALT MODE MODE 4 AND MODE 5: TOTALHALT AND HIBERNATE MODES In Mode 3, HCLK, ACLK, and PCLK are off and the ARM Cortex-M3 processor is in sleep mode. The wake-up time is three to five times FCLK, where FCLK is the clock selected by the CLKCON0[2:0] bits. In Mode 4 and Mode 5, HCLK, ACLK, and PCLK are off and the ARM Cortex-M3 processor is in DEEPSLEEP mode. The wake-up time is ~30.8 µs. The typical IDD in these modes is 2 µA to 4 µA. Calculate the expected IDD in Mode 3 as follows: When Register CLKSYSDIV = 0x0 IDD [µA] = 16 × FCLK + 345 When Register CLKSYSDIV = 0x1 IDD [µA] = 16 × FCLK + 420 Rev. 0 | Page 9 of 12 AN-1111 Application Note NOTES Rev. 0 | Page 10 of 12 Application Note AN-1111 NOTES Rev. 0 | Page 11 of 12 AN-1111 Application Note NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN09746-0-10/12(0) Rev. 0 | Page 12 of 12