AD ADUCM361

Low Power Precision Analog Microcontroller
ARM Cortex M3, with dual Sigma-Delta ADCs
Preliminary Technical Data
ADuCM360/ADuCM361
FEATURES
Analog Input/Output
Dual (24-bit) ADCs (ADuCM360)
Single (24-bit) ADC (ADuCM361)
Single Ended and fully Differential inputs
Programmable ADC output rate (4 Hz to 4 kHz)
Simultaneous 50Hz/60Hz rejection
50SPS Continuous Conversion Mode
16.67SPS Single Conversion Mode
Flexible input MUX for input channel selection to both ADCs
Primary and Auxiliary (24-bit) ADC channel
6 differential or 11 Single-Ended input channels
4 internal channels for monitoring DAC, Temperature
sensor, IOVDD and AVDD (ADC1 only)
Programmable Gain (1 to 128)
Selectable input range: ±6.64 mV to ±1.2 V
RMS noise: 43nV @3.75Hz, 180nV @ 50Hz
Programmable sensor excitation current sources
10/50/100/150/200/250/300/400/500/600/800uA and
1mA current source options
On-chip precision Voltage reference (±4 ppm/°C)
Single 12-bit voltage output DAC
NPN mode for 4-20mA loop applications
Microcontroller
ARM Cortex™-M3 32-bit processor
Serial Wire download and debug
Internal Watch crystal for wakeup timer
16 MHz Oscillator with 8-way Programmable Divider
Memory
128k Bytes Flash/EE Memory, 8k Bytes SRAM
In-circuit debug/download via Serial Wire and UART
Power
Operates directly from a 3.0V battery
Supply Range: 1.8V to 3.6V (max)
Power Consumption
MCU Active Mode: Core consumes 290µA / MHz
Active Mode: 1.0mA (All peripherals active), core
operating at 500KHz
Power down mode: 4µA (WU Timer Active)
On-Chip Peripherals
UART, I2C and 2 x SPI Serial I/O
16-bit PWM Controller
19-Pin Multi-Function GPIO Port
2 General Purpose Timers
Wake-up Timer/Watchdog Timer
Multi-Channel DMA and Interrupt Controller
Package and Temperature Range
48 lead LFCSP (7mm x 7mm) package –40°C to 125°C
Development Tools
Low-Cost QuickStart™ Development System
Third-Party Compiler and emulator tool Support
Multiple Functional Safety features for improved diagnostics
APPLICATIONS
Industrial automation and process control
Intelligent, precision sensing systems
4 mA to 20 mA loop-powered smart sensor systems
Medical devices, patient monitoring
Rev. Pr R
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
ADuCM360/ADuCM361
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
Ain0
Ain1
Ain2
Ain3
Ain4/IEXC
Ain5/IEXC
VBias
Gen
...
.
. .. .
.. .
.
..
.. .
.
..
AMP
MUX
Ain6/IEXC
Ain7/IEXC/VBias0/EXT_REF2IN+
Ain8/EXT_REF2INAin9
Ain10
Ain11/VBias1
12-BIT
DAC
BUF
DAC
. .
. .
AMP
DAC,
TEMP,
IOVDD/4
AVDD/4
ON-CHIP
1.8V ANALOG
LDO
VREF
Σ−∆
24-BIT
..
Σ−∆ ADC
Modulator
VREF
Σ−∆
Modulator
..
16MHz
..
SINC3/4
FILTER
SINC2
FILTER
PRECISION
REFERENCE
. .
VREF- VREF+
RESET
ON-CHIP
OSC (3%)
16MHz
XTAL0
XTAL1
MEMORY
128KB FLASH
8KB SRAM
TIMER0
TIMER1
WATCHDOG
WAKEUP-TIMER
PWM
DMA+
INTERRUPT
CONTROLLER
SERIAL WIRE
DEBUG +
PROGRAMMING
& DEBUG
INT_REF
19 GENERAL
PURPOSE
I/O PORTS
SWDIO
SWCLK
DVDD_REG
AVDD_REG
BUF
Figure 1. ADuCM360 Block Diagram
Rev. Pr R Page 2 of 21
POR
GPIO PORTs
UART PORT
2 x SPI PORTs
I2C PORT
24-BIT
BUF
GND_SW
ARM
CORTEX-M3
MCU
Σ−∆ ADC
10/50/100/200/
500/750/1000uA
Current Sources
IREF
SINC3/4
FILTER
SINC2
FILTER
SELECTABLE
VREF Sources
.....
ON-CHIP
1.8V DIGITAL
LDO
IOVDD IOVDD
ADuCM360/ADuCM361
Preliminary Technical Data
TABLE OF CONTENTS
Features ...............................................................................................1
Noise Resolution of Primary and Auxiliary ADCs ................ 10
Functional Block Diagram ...............................................................2
I2C Timing Diagrams ................................................................. 12
General Description ..........................................................................4
SPI Timing Diagrams ................................................................. 13
Specifications .....................................................................................5
Absolute Maximum Ratings .......................................................... 16
ADuCM360/ADuCM361 Microcontroller Electrical
Specifications .................................................................................5
ESD Caution ................................................................................ 16
Outline Dimensions ........................................................................ 21
Rev. Pr R| Page 3 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
GENERAL DESCRIPTION
The ADuCM360 is a fully integrated, 4 kSPS, 24-bit data acquisition system incorporating dual, high performance multichannel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs),
32-bit ARM Cortex M3® MCU, and Flash/EE memory on a
single chip. The part is designed for direct interfacing to
external precision sensors in both wired and battery powered
applications.
The ADuCM360/ADuCM361 also integrates a range of on-chip
peripherals which can be configured under microcontroller
software control as required in the application. These
peripherals include UART, I2C and dual SPI Serial I/O
communication controllers, 19-Pin GPIO Ports, 2 General
Purpose Timers, Wake-up Timer and System Watchdog Timer.
A 16-bit PWM with six output channels is also provided.
The ADuCM361 contains all the features of the ADuCM360
except the primary ADC, ADC0 is not available – only the
auxiliary ADC, ADC1 is available.
The ADuCM360/ADuCM361 is specifically designed to operate
in battery powered applications where low power operation is
critical. The microcontroller core can be configured in a normal
operating mode consuming 290μA/MHz (including
Flash/SRAM Idd) resulting in an overall system current
consumption of 1mA when all peripherals are active.
The device contains an on-chip 32 KHz oscillator and an
internal 16MHz high-frequency oscillator. This clock is routed
through a programmable clock divider from which the MCU
core clock operating frequency is generated. The maximum
core clock speed is 16MHz and this is not limited by operating
voltage or temperature.
The microcontroller core is a low power Cortex-M3 core from
ARM. It is a 32-bit RISC machine, offering up to 20 MIPS peak
performance. The Cortex-M3 MCU incorporates a flexible 11channel DMA controller supporting all wired (SPI, UART, I2C)
communication peripherals. 128k Bytes of non-volatile
Flash/EE and 8k Bytes of SRAM are also integrated on-chip.
The Analog sub-system consists of dual ADCs each connected
to a flexible input MUX. Both ADCs can operate in fully
differential and single ended modes. Other on-chip ADC
features include dual programmable excitation current sources,
burn-out current sources and a bias voltage generator of
AVDD_REG/2 (900mV) to set the common-mode voltage of an
input channel. A low-side internal ground switch is provided to
allow powering down of a bridge between conversions. The
ADCs contain two parallel filters – a Sinc3 or Sinc4 in parallel
with a Sinc2. The Sinc3 or Sinc4 filter is for precision
measurements. The Sinc2 filter is for fast measurements and for
detection of step changes in the input signal The device also
contains a low noise, low drift internal band-gap reference or
can be configured to accept up to 2 external reference sources in
ratiometric measurement configurations. An option to buffer
the external reference inputs is also provided on-chip. A singlechannel buffered voltage output DAC is also provided on chip.
The part can also be configured in a number of low power
operating modes under direct program control, including
hibernate mode (internal wake-up timer active) consuming
only 4µA. In hibernate mode, peripherals such as external
interrupts or the internal wake up timer can wake up the device.
This allows the part to operate in an ultra-low power operating
mode and still respond to asynchronous external or periodic
events.
On-chip factory firmware supports in-circuit serial download
via a serial wire interface (2-pin JTAG system) and UART while
non-intrusive emulation is also supported via the serial wire
interface. These features are incorporated into a low-cost
QuickStart Development System supporting this Precision
Analog Microcontroller family.
The part operates from an external 1.8V to 3.6V voltage supply
and is specified over an industrial temperature range of -40°C to
125°C.
Rev. Pr R Page 4 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
SPECIFICATIONS
ADUCM360/ADUCM361 MICROCONTROLLER ELECTRICAL SPECIFICATIONS
AVDD/IOVDD = 1.8 V to 3.6V, Internal 1.2V reference, fCORE = 16 MHz, all specifications TA = −40°C to +125°C, unless otherwise
noted.
Table 1. ADuCM360/ADuCM361 Specifications
Parameter
ADC SPECIFICATIONS
Conversion Rate 1
Both Primary & Auxiliary
Channels
No Missing Codes1
RMS Noise and Data Output
Rates
Integral Nonlinearity1
Offset Error,2,3
Offset Error1,2,3
Offset Error Drift vs.
Temperature 4
Test Conditions/Comments
Min
Chop off
Chop on
4
4
Chop off (fADC ≤ 500 Hz)
Chop on (fADC ≤ 250 Hz)
See Noise and Resolution tables
in the User Guide
Gain = 1
Gain = 2, 4, 8, 16, 32, 64, 128
24
24
Chop off, offset error is in the
order of the noise for the programmed gain and update rate
following calibration
Chop on
Chop off
Chop on
Offset Error Drift vs. Time
Full-Scale Error1,5,6,7
Gain Drift vs. Temperature4
Absolute Input Voltage Range
Unbuffered Mode
Buffered Mode
Unbuffered Mode:
Differential Input Voltage
Ranges1
Max
Unit
4000
1333
Hz
Hz
Bits
Bits
±15
±25
ppm of FSR
ppm of FSR
±100/Gain
μV
±1.0
100/ Gain
μV
nV/°C
10
TBD
nV/°C
nV/1000
hours
mV
ppm/°C
±0.5/Gain
±1
Gain = 1 to 16, external
reference
Gain = 32 to 128 external
reference
TBD
±3
Gain Error Drift vs. Time
PGA Gain Mismatch Error
Power Supply Rejection1,8
Typ
TBD
85
ppm/1000
hours
%
dB
100
dB
85
dB
±0.15
Chop on, ADC = 0.25 V (Gain =
4), ext. reference
Chop off, ADC = 7.8 mV (Gain =
128), ext. reference
Chop off, ADC = 1 V (Gain = 1),
ext. reference
Gain=1
Gain =1
Gain >=2
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32 (AVDD >=2.0V)
(AVDD <2.0V)
Gain = 64 (AVDD >=2.0V)
AGND
AGND+ 100mV
AGND
Rev. Pr R| Page 5 of 21
Avdd
Avdd-100mV
Avdd
±VREF
±500
±250
±125
±62.5
±26.56
±18.75
±13.28
V
V
mV
mV
mV
mV
mV
mV
mV
mV
mV
ADuCM360/ADuCM361
Preliminary Technical Data
Parameter
Test Conditions/Comments
(AVDD <2.0V)
Gain = 128 (AVDD >=2.0V)
(AVDD <2.0V)
Min
Common mode Voltage, Vcm1
Vcm=(AIN(+)+AIN(-))/2,
Gain=2 to 128
Input current will be higher
when Vcm <0.5V
Gain = 1, Buffered mode
(excluding pins with Vbias)
Gain >1, Buffered mode
(excluding pins with Vbias)
Unbuffered mode. Input current
will vary with input voltage
Buffered mode:
AIN0, AIN1, AIN2, AIN3
AIN4, AIN5, AIN6, AIN7
AIN8, AIN9, AIN10, AIN11
Unbuffered mode
AGND
ADC Gain =1
ADC Gain =2 to 128
70
80
50 Hz/60 Hz ± 1 Hz,
16.7 Hz update rate, chop on
50 Hz update rate, chop off
ADC Gain =1
ADC Gain =2 to 128
97
90
Input Current1,9
Average Input Current Drift
Common-Mode Rejection DC1
On ADC Input
Common-Mode Rejection1
50 Hz/60 Hz
Normal-Mode Rejection1
50 Hz/60 Hz
On ADC Input
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
Accuracy
GROUND SWITCH
Ron
Allowable Current
VOLTAGE REFERENCE
ADC Precision Reference
Internal VREF
Initial Accuracy1
Reference Temperature
Coefficient (Tempco)1,8
Power Supply Rejection1
50 Hz/60 Hz ± 1 Hz, 16.6 Hz fADC/
chop on, 50 Hz fADC/ chop off
After user calibration
MCU in power down or standby
mode before measurement
60
With 20K resistor off – direct
short to ground
Measured at TA = 25°C
-0.05
−15
Typ
Unit
mV
mV
mV
V
1
nA
2
nA
500
nA/V
±5
±16
±9
±250
pA/°C
pA/°C
pA/°C
pA/V/°C
100
dB
dB
dB
80
dB
82.1
mV
250
6
mV/°C
°C
12
20
Ohms
mA
1.2
V
%
ppm/°C
±8
100
Rev. Pr R Page 6 of 21
Max
±9.375
±6.64
±4.6875
0.05
+15
dB
ADuCM360/ADuCM361
Preliminary Technical Data
Parameter
External Reference Input
Range
Input Current
Test Conditions/Comments
Min
Buffered mode
Unbuffered mode
0
0
Minimum Differential voltage
between VREF+ and VREF- pins
is 400mV
Buffered mode
Unbuffered mode
Normal Mode Rejection
Common Mode Rejection
Reference Detect Levels
EXCITATION CURRENT SOURCES
Output Current
Initial Tolerance at 25°C
Drift1
Initial Current Matching at 25°C1
Drift Matching1
Load Regulation (AVDD) 1
Output Compliance1
DAC CHANNEL SPECIFICATIONS
Voltage Range
DC Specifications 10
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
NPN Mode
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Output Current Range1
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
Available from each current
source – 10/50/200uA nominal
Iout >= 50uA
Using internal reference resistor
Using external 150 kΩ reference
resistor between IREF pin and
AGND. Resistor must have a drift
spec of 5ppm/°C
Matching between both current
sources
AVDD = 3.3 V
10uA to 210uA Iout
Iout >210uA
RL = 5 kΩ, CL = 100 pF
Internal reference
External reference
10
Typ
Max
Unit
AVDD-0.1
AVDD
V
V
15
500
80
78
dB
400
mV
50
nA
nA/V
1000
μA
±5
200
75
%
ppm/°C
ppm/°C
±0.5
%
50
0.2
AGND − 30 mV
AGND − 30 mV
AVDD − 0.85 V
AVDD − 1.1 V
ppm/°C
%/V
V
V
0
0
VREF
1.8
V
V
±1
±15
±1
Bits
LSB
LSB
mV
%
23.6
Bits
LSB
LSB
mA
mA
mA
12
±3
±0.5
±2
Guaranteed monotonic
1.2 V internal reference
VREF range (reference = 1.2 V)
12
±1.0
±0.5
±0.35
±0.75
0.008
1 LSB change at major carry
(where maximum number of
bits simultaneously change in
the DAC0DAT register)
Rev. Pr R| Page 7 of 21
10
±20
µs
nV-sec
ADuCM360/ADuCM361
Parameter
POWER-ON RESET (POR)
POR Trip Level
Timeout from POR
WATCHDOG TIMER (WDT)
Timeout Period1
Timeout Step Size
FLASH/EE MEMORY1
Endurance 11
Data Retention 12
Digital Inputs
Logic 1 Input Current (leakage
current)
Logic 0 Input Current (leakage
current)
Input Capacitance
Logic Inputs
VINL, Input Low Voltage
VINH, Input High Voltage
Logic Outputs
VOH, Output High Voltage
VOL, Output Low Voltage
CRYSTAL OSCILLATOR1
Logic Inputs, XTALI Only 13
Input Low Voltage (VINL)
Input High Voltage (VINH)
XTALI Capacitance
XTALO Capacitance
ON-CHIP Low Power Oscillator
Oscillator
Accuracy
ON-CHIP High Frequency
Oscillator
Oscillator
Accuracy
MCU CLOCK RATE
Preliminary Technical Data
Test Conditions/Comments
Refers to voltage at DVDD pin
Power-on level
Power-down level
After Reset Event
Typ
Max
1.6
1.6
50
0.00003
T3CON[3:2]=[10]
Tj=85°C
All digital inputs
VINH =VDD or VINH = 1.8V
Internal pull-up disabled
RESET , SWCLK, SWDIO
VINL = 0V
Internal pull-up disabled
RESET , SWCLK, SWDIO
8192
20,000
10
10
100
nA
μA
10
100
nA
μA
10
pF
0.2 x VDD
VDD – 400mV
0.4
0.8
1.7
6
6
32,768
−20
To be confirmed across full
temperature range of -40 to
+125C
Eight programmable core clock
selections within this range:
sec
ms
Cycles
Years
0.7 x VDD
ISOURCE = 1mA
ISINK = 1mA
Unit
V
V
ms
7.8125
Using an External Clock
MCU START-UP TIME
At Power-On
Min
V
V
V
V
V
V
pF
pF
+20
kHz
%
0.125
-1
2
16
1
MHz
%
0.125
2
16
MHz
16
MHz
0.032768
Includes kernel power-on
execution time
Includes kernel power-on
execution time
Rev. Pr R Page 8 of 21
41
ms
1.44
ms
ADuCM360/ADuCM361
Preliminary Technical Data
Parameter
From MCU Power-Down
(mode 1, 2 and 3)
From TOTAL-HALT or
HIBERNATE (mode 4 or mode
5) mode
POWER REQUIREMENTS
Power Supply Voltages
VDD
Power Consumption
IDD (MCU Active Mode) 14,15
IDD (MCU Powered Down)1
IDD (Primary ADC) (total)15
PGA
Input Buffers
Digital Interface +
Modulator
IDD (Auxiliary ADC)
External Reference Input
buffers
Test Conditions/Comments
Fclk is the Cortex-M3 core clock
Min
Typ
3-5 x Fclk
Max
30.8
1.8
MCU clock rate = 16 MHz, all
peripherals on
MCU clock rate = 500 KHz, Both
ADCs on (Input buffers off ) with
PGAs Gain = 4, 1 x SPI on, all
timers on
Full temperature range
HIBERNATE (mode 5)
Reduced temperature range
−40°C to +85°C
PGA enabled – total, G>=32
G=4/8/16 – PGA only
G=32/64/128 – PGA only
2 x Input buffers is 70uA
Input buffers off, G=4/8/16 only
60uA each
Unit
μs
3.6
V
5.5
mA
1
mA
4
10
μA
2
5
μA
320
130
180
70
μA
μA
70
200
120
μA
μA
μA
μA
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
Tested at gain range = 4 after initial offset calibration.
Measured with an internal short. A system zero-scale calibration removes this error.
4
A recalibration at any temperature removes these errors.
5
These numbers do not include internal reference temperature drift.
6
Factory calibrated at gain = 1.
7
System calibration at a specific gain range removes the error at this gain range.
8
Measured using the box method.
9
Input current measured with one ADC measuring a channel. If both ADCs measure the same input channel, then the input current will increase – approximately
double
10
Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30.
11
Endurance is qualified to 20,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
12
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
13
Voltage input levels only relevant if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface will determine the
common mode voltage.
14
Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7mA.
15
Total IDD for ADC includes figures for PGA≥32, input buffers, digital interface and the Sigma Delta modulator.
1
2
3
Rev. Pr R| Page 9 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
NOISE RESOLUTION OF PRIMARY AND AUXILIARY ADCS
Table 2: RMS Noise (µV) vs. Gain and Output Update Rate
(Using an Internal Reference (1.2V) Both ADCs)
Update Rate (Hz)
3.75 (Chop On)
ADCxFLT = 0x8D7C
30 (Chop Off)
ADCxFLT = 0x007E
50 (Chop Off)
ADCxFLT = 0x007D
100 (Chop Off)
ADCxFLT = 0x004D
488 (Chop Off Sinc4)
ADCxFLT = 0x100F
976 (Chop Off Sinc4)
ADCxFLT = 0x1007
1953 (Chop Off Sinc4)
ADCxFLT = 0x1003
3906 (Chop Off Sinc4)
ADCxFLT = 0x1001
Gain of 1
Gain of 2
Gain of 4
Gain of 8
Gain of 16
Gain of 32
Gain of 64
Gain of 128
1.05
0.45
0.23
0.135
0.072
0.064
0.055
0.052
2.1
1.37
0.63
0.37
0.22
0.2
0.16
0.155
3.7
1.6
0.83
0.47
0.29
0.24
0.21
0.2
5.45
2.41
1.13
0.63
0.38
0.32
0.27
0.25
10
4.7
2.2
1.3
0.79
0.67
0.58
0.57
13.5
6.5
3.3
1.7
1.1
0.91
0.74
0.7
19.3
10
4.7
2.6
1.55
1.3
1.15
1.0
67.0
36
16.6
8.8
4.9
2.68
1.76
1.4
Table 3: Typical Output RMS Effective Number of Bits in Normal Mode
(Using an Internal Reference (1.2V), Both ADCs, Peak-to-Peak Bits in Parentheses)
ADC
Register
Status
Chop On
Sinc3
Chop Off
Sinc3
Data
Update
Rate
3.75 Hz
30 Hz
±1.0 V
(PGA = 1)
Input Voltage Noise (mV)
±500 mV
±250 mV
(PGA = 2)
(PGA = 4)
21.1
(18.4p-p)
20.1
(17.4p-p)
21.3
(18.6p-p)
19.7
(17p-p)
21.3
(18.6p-p)
19.8
(17.1p-p)
19.3
(16.6p-p)
19.5
(16.8p-p)
19.5
(16.8p-p)
18.9
(16.2p-p)
Chop Off
Sinc3
50 Hz
Chop Off
Sinc3
100 Hz
Chop Off
Sinc4
488 Hz
17.9
(15.2p-p)
18
(15.2p-p)
Chop Off
Sinc4
976 Hz
17.4
(14.7p-p)
17.5
(14.8p-p)
16.9
(14.2p-p)
15.1
(12.4p-p)
16.9
(14.2p-p)
15
(12.3p-p)
Chop Off
Sinc4
Chop Off
Sinc4
1953
Hz
3906
Hz
18.7
(16p-p)
±125 mV
(PGA = 8)
±62.5 mV
(PGA = 16)
±31.25 mV
(PGA = 32)
±15.625 mV
(PGA = 64)
±7.8125 mV
(PGA = 128)
21.1
(18.4p-p)
19.6
(16.9p-p)
19.3
(16.6p-p)
21
(18.3p-p)
19.4
(16.7p-p)
20.2
(17.4p-p)
18.5
(15.8p-p)
19.4
(16.7p-p)
17.8
(15.1p-p)
18.5
(15.7p-p)
16.9
(14.2p-p)
19
(16.3p-p)
18.3
(15.5p-p)
17.4
(14.7p-p)
16.5
(13.8p-p)
19
(16.3p-p)
18.9
(16.2p-p)
18.6
(16.1p-p)
17.8
(15.1p-p)
17.1
(14.4p-p)
16.2
(13.5p-p)
18.1
(15.3p-p)
17.5
(14.8p-p)
17.8
(15.1p-p)
17.5
(14.8p-p)
16.8
(14p-p)
16
(13.3p-p)
15
(12.3p-p)
17.4
(14.7p-p)
17.1
(14.3p-p)
16.3
(13.6p-p)
15.6
(12.9p-p)
14.7
(12p-p)
17
(14.3p-p)
15.1
(12.4p-p)
16.8
(14p-p)
15.1
(12.4p-p)
16.6
(13.8p-p)
14.9
(12.2p-p)
15.8
(13.1p-p)
14.8
(12p-p)
15
(13.1p-p)
14.4
(11.7p-p)
14.2
(11.5p-p)
13.7
(11p-p)
Rev. Pr R Page 10 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
Table 4: RMS Noise (µV) vs. Gain and Output Update Rate
(Using an External Reference (2.5V) Both ADCs)
Update Rate (Hz)
4.55 (Chop On)
ADCxFLT = 0x88FD
30 (Chop Off)
ADCxFLT = 0x007E
50 (Chop Off)
ADCxFLT = 0x007D
100 (Chop Off)
ADCxFLT = 0x004F
488 (Chop Off Sinc4)
ADCxFLT = 0x100F
976 (Chop Off Sinc4)
ADCxFLT = 0x1007
1953 (Chop Off Sinc4)
ADCxFLT = 0x1003
3906 (Chop Off Sinc4)
ADCxFLT = 0x1001
Gain of 1
Gain of 2
Gain of 4
Gain of 8
Gain of 16
Gain of 32
Gain of 64
Gain of 128
1.1
0.5
0.27
0.17
0.088
0.07
0.06
0.58
3
1.4
0.85
0.44
0.27
0.22
0.19
0.17
3.9
2.2
0.92
0.46
0.3
0.21
0.2
0.19
5.2
2.8
1.25
0.63
0.38
0.32
0.28
0.26
9.3
5.0
2.5
1.2
0.75
0.7
0.57
0.5
12.5
7
3.5
1.75
1.2
0.83
0.77
0.75
20.0
10
5.7
2.6
1.71
1.3
1.24
1.1
140.0
70.0
35.0
17.2
8.9
4.8
2.65
1.88
Table 5: Typical Output RMS Effective Number of Bits in Normal Mode
(Using an External Reference (2.5V), Both ADCs, Peak-to-Peak Bits in Parentheses)
ADC
Register
Status
Chop On
Sinc3
Chop Off
Sinc3
Data
Update
Rate
3.75 Hz
30 Hz
±1.0 V
(PGA = 1)
Input Voltage Noise (mV)
±500 mV
±250 mV
(PGA = 2)
(PGA = 4)
±125 mV
(PGA = 8)
±62.5 mV
(PGA = 16)
±31.25 mV
(PGA = 32)
±15.625 mV
(PGA = 64)
±7.8125 mV
(PGA = 128)
22.1
(19.4p-p)
20.7
(18p-p)
22.3
(19.5p-p)
20.7
(18p-p)
22.1
(19.4p-p)
20.5
(17.7p-p)
21.8
(19.1p-p)
20.5
(17.7p-p)
21.8
(19.1p-p)
20.1
(17.4p-p)
21.1
(18.4p-p)
19.4
(16.7p-p)
20.3
(17.6p-p)
18.6
(15.9p-p)
19.4
(16.6p-p)
17.8
(15.1p-p)
Chop Off
Sinc3
50 Hz
20.3
(17.6p-p)
20.1
(17.4p-p)
20.4
(17.7p-p)
20.4
(17.7p-p)
20
(17.3p-p)
19.5
(16.8p-p)
18.6
(15.9p-p)
17.6
(14.9p-p)
Chop Off
Sinc3
100 Hz
19.9
(17.2p-p)
19.8
(17p-p)
19.9
(17.2p-p)
19.9
(17.2p-p)
19.6
(16.9p-p)
18.9
(16.2p-p)
18.1
(15.4p-p)
17.2
(14.5p-p)
Chop Off
Sinc4
488 Hz
19
(16.3p-p)
18.9
(16.2p-p)
18.9
(16.2p-p)
19
(16.3p-p)
18.7
(15.9p-p)
17.8
(15p-p)
17.1
(14.3p-p)
16.3
(13.5p-p)
Chop Off
Sinc4
976 Hz
18.6
(15.9p-p)
18.4
(15.7p-p)
18.4
(15.7p-p)
18.4
(15.7p-p)
18
(15.3p-p)
17.5
(14.8p-p)
16.6
(13.9p-p)
15.7
(12.9p-p)
17.9
(15.2p-p)
15.1
(12.4p-p)
17.9
(15.2p-p)
15.1
(12.4p-p)
17.7
(15p-p)
15.1
(12.4p-p)
17.9
(15.2p-p)
15.1
(12.4p-p)
17.5
(14.8p-p)
15.1
(12.4p-p)
16.9
(14.2p-p)
15
(12.3p-p)
15.9
(13.2p-p)
14.8
(12.1p-p)
15.1
(12.4p-p)
14.3
(11.6p-p)
Chop Off
Sinc4
Chop Off
Sinc4
1953
Hz
3906
Hz
Rev. Pr R| Page 11 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
I2C TIMING DIAGRAMS
Capacitive load for each of the I2C 1-bus line, Cb = 400pF maximum as per I2C-bus specifications.
I2C timing is guaranteed by design and not production tested.
Table 6. I2C Timing in Fast Mode (400 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tSUP
Description
Serial Clock (SCL) low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and serial data (SDA)
Fall time for both SCL and SDA
Pulse width of spike suppressed
Min
1300
600
600
100
0
600
600
1.3
20 + 0.1 Cb
20 + 0.1 Cb
0
Max
300
300
50
Unit
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
Min
4.7
4.0
4.7
250
0
4.0
4.0
4.7
-
Max
1
300
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
Table 7. I2C Timing in Standard Mode (100 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
Description
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
tBUF
tSUP
tR
MSB
LSB
tDSU
tSHD
P
S
tF
tDHD
2–7
tR
tRSU
tH
1
SCL (I)
MSB
tDSU
tDHD
tPSU
ACK
8
tL
9
tSUP
STOP
START
CONDITION CONDITION
1
S(R)
REPEATED
START
Figure 2. I2C Compatible Interface Timing
1 2
I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
Rev. Pr R Page 12 of 21
tF
04955-054_edited
SDA (I/O)
ADuCM360/ADuCM361
Preliminary Technical Data
SPI TIMING DIAGRAMS
Table 8. SPI Master Mode Timing
Parameter
tSL
tSH
tDAV
tDOSU
Description
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge
Data output setup before SCLK edge1
tDSU
tDHD
tDF
tDR
tSR
tSF
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
0
Max
35.5
(SPIDIV + 1) ×
tUCLK
58.7
16
12
12
12
12
35.5
35.5
35.5
35.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tUCLK = 62.5 ns. It corresponds to the internal 16MHz clock before the clock divider.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
SCLK
(POLARITY = 1)
tDAV
tDF
MOSI
MISO
tSF
tDR
MSB
MSB IN
BITS 6 TO 1
BITS 6 TO 1
LSB
LSB IN
04955-055_edited
1
Min
tDSU
tDHD
Figure 3. SPI Master Mode Timing (PHASE Mode = 1)
Rev. Pr R| Page 13 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
MOSI
tDF
MSB
BITS 6 TO 1
MSB IN
LSB
BITS 6 TO 1
LSB IN
04955-056_edited
MISO
tDR
tDSU
tDHD
Figure 4. SPI Master Mode Timing (PHASE Mode = 0)
Table 9. SPI Slave Mode Timing
Parameter
tCS
Description
CS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width 1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
1
Min
38
62.5
Typ
Max
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
49.1
20.2
10.1
12
12
12
12
0
tUCLK = 62.5 ns. It corresponds to the internal 16MHz clock before the clock divider.
Rev. Pr R Page 14 of 21
35.5
35.5
35.5
35.5
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuCM360/ADuCM361
Preliminary Technical Data
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDF
MISO
tDR
MSB
MOSI
BITS 6 TO 1
MSB IN
LSB
BITS 6 TO 1
LSB IN
tDSU
tDHD
04955-057_edited
tDAV
Figure 5. SPI Slave Mode Timing (PHASE Mode = 1)
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK_
(POLARITY = 1)
tDAV
tDOCS
MISO
MOSI
MSB
MSB IN
tDR
BITS 6 TO 1
BITS 6 TO 1
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (PHASE Mode = 0)
Rev. Pr R| Page 15 of 21
LSB
LSB IN
04955-058_edited
tDF
ADuCM360/ADuCM361
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter
AVDD/IOVDD to GND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
VREF to AGND
Analog Inputs to AGND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD (Human Body Model) rating
All Pins
θJA Thermal Impedance
48-Pin LFCSP _VQ
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
Pb-Free Assemblies
(20 sec to 40 sec)
Rating
−0.3 V to 3.96V
−0.3 V to 3.96V
−0.3 V to 3.96V
−0.3 V to TBD
−0.3 V to TBD
–40°C to +125°C
–65°C to +150°C
150°C
±2kV
27°C/W
240°C
260°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. Pr R Page 16 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
Pin Configuration and Function Descriptions
Figure 7. ADuCM360/ADuCM361 Pinout
Table 11. Pin Function Descriptions
Pin No.
1
2
Mnemonic
RESET
P2.1/SDA/UARTDCD
3
P2.2/BM
4
5
6
7
XTAL0
XTAL1
IOVDD
DVDD_REG
8
AIN0
9
AIN1
10
AIN2
Description
Reset. Input pin, active low. An internal pull-up is provided.
General-Purpose Input and General-Purpose Output P2.1/ I2C serial data Pin/Alternatively, this
pin may be the UART Data carrier Detect pin.
This is a multi function input/output pin.
General-Purpose Input and General Purpose Output P2.2/ Boot mode input select pin. When
this pin is held low during any reset sequence, the part will enter UART download mode.
This is a dual function input/output pin.
External Crystal Oscillator Output Pin. Optional 32.768kHz source for Real time clock.
External Crystal Oscillator Input Pin. Optional 32.768kHz source for Real time clock.
Digital System Supply pin.
Internal Digital Regulator Supply Output. This pin must be connected to ground via a 470nF
capacitor.
Note: This pin must be connected to pin 18, AVDD_REG
ADC Analog Input 0. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes.
ADC Analog Input 1. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes.
ADC Analog Input 2. This pin can be configured as a positive or negative input to either ADC in
Rev. Pr R| Page 17 of 21
ADuCM360/ADuCM361
Pin No.
Mnemonic
11
AIN3
12
AIN4/IEXC
13
14
GND_SW
VREF+
15
VREF−
16
17
18
AGND
AVDD
AVDD_REG
19
20
21
DAC
INT_REF
IREF
22
AIN5/IEXC
23
AIN6/IEXC
24
AIN7/VBIAS0/IEXC/EXT_REF2IN+
25
AIN8/EXT_REF2IN-
26
AIN9
27
AIN10
28
AIN11/VBIAS1
29
P0.0/MISO1
30
P0.1/SCLK1/SCL/SIN
31
P0.2/MOSI1/SDA/SOUT
32
P0.3/IRQ0/CS1
33
P0.4/RTS/ECLKO
34
P0.5/CTS/IRQ1
Preliminary Technical Data
Description
Differential or single ended modes.
ADC Analog Input 3. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes.
ADC Analog Input 4. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes.
Or, it may be configured as the output pin for either Excitation current source 0 or 1.
Sensor Power Switch to Analog Ground Reference.
External Reference Positive Input, an external reference can be applied between VREF+ and
VREF-.
External Reference Negative Input, an external reference can be applied between VREF+ and
VREF-.
Analog System Ground reference pin.
Analog System Supply pin.
Internal Analog Regulator Supply Output. This pin must be connected to ground via a 470nF
capacitor.
Note: This pin must be connected to pin 7, DVDD_REG
DAC Voltage Output
This pin must be connected to ground via a 470nF decoupling capacitor.
Optional reference current resistor connection for the Excitation current sources.
Reference current set by low drift external resistor (5ppm/C).
Multi-Function Pin: ADC Analog Input 5. This pin can be configured as a positive or negative input
to either ADC in Differential or single ended modes. Alternatively, it may be configured as the
output pin for either Excitation current source 0 or 1. Or, it may be configured as the output pin for
either Excitation current source 0 or 1.
Multi-Function Pin: ADC Analog Input 6. This pin can be configured as a positive or negative input
to either ADC in Differential or single ended modes.
Or, it may be configured as the output pin for either Excitation current source 0 or 1.
Multi-Function Pin: ADC Analog Input 7. This pin can be configured as a positive or negative input
to either ADC in differential or single ended modes. Alternatively, this pin can be configured as an
analog output pin to generate a Bias Voltage, VBIAS3 of AVDD_REG/2.
Or, it may be configured as the output pin for either Excitation current source 0 or 1. Alternatively,
this pin can be configured as an external reference 2 positive input.
Multi-Function Pin: ADC Analog Input 8. This pin can be configured as a positive or negative input
to either ADC in Differential or single ended modes. Alternatively, this pin can be configured as an
external reference 2 negative input.
ADC Analog Input 9. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes. Alternatively, this pin can be configured as the non-inverting
input to the DAC output buffer when the DAC is configured for NPN mode.
ADC Analog Input 10. This pin can be configured as a positive or negative input to either ADC in
Differential or single ended modes.
Multi-Function Pin: ADC Analog Input 11. This pin can be configured as a positive or negative input
to either ADC in Differential or single ended modes. Alternatively, this pin can be configured as an
analog output pin to generate a Bias Voltage, VBIAS5 of AVdd/2.
General-Purpose Input and General-Purpose Output P0.0/SPI1 Master In – Slave out Pin.
This is a dual function input/output pin.
General-Purpose Input and General-Purpose Output P0.1/SPI1 Serial Clock Pin/I2C Serial Clock
Pin/ UART Serial Input. This is a multi function input/output pin.
This pin will be the data input for the UART downloader.
General-Purpose Input and General-Purpose Output P0.2/ SPI1 Master Out – Slave In Pin /I2C
Serial Data Pin/ UART Serial output. This is a multi function input/output pin.
This pin will be the data output for the UART downloader.
General-Purpose Input and General-Purpose Output P0.3/ External Interrupt Request 0/ SPI1
Chip Select Pin (Active Low). This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P0.4/ Request-to-Send Signal in UART
Mode/ Clock out (for test purposes) pin. This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P0.5/ Clear-to-Send Signal in UART Mode. /
External Interrupt Request 1.
Rev. Pr R Page 18 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
Pin No.
Mnemonic
35
P0.6/IRQ2/SIN
36
P0.7/POR/SOUT
37
38
IOVDD
P1.0/IRQ3/PWMSYNC/ECLKI
39
P1.1/IRQ4/PWMTRIP/DTR
40
P1.2/PWM0/RI
41
P1.3/PWM1/DSR
42
P1.4/PWM2/MISO0
43
P1.5/IRQ5/PWM3/SCLK0
44
P1.6/IRQ6/PWM4/MOSI0
45
P1.7/IRQ7/PWM5/CS0
46
P2.0/SCL/UARTCLK
47
48
SWCLK
SWDIO
EP
Description
This is a dual function input/output pin.
General-Purpose Input and General-Purpose Output P0.6/ External Interrupt Request 2/ UART
Serial Input. This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P0.7/ Power on Reset active high bit/ UART
Serial output. This is a triple function input/output pin.
Digital System Supply pin.
General-Purpose Input and General Purpose Output P1.0/ External Interrupt Request 3/ PWM
external Sync input/External clock input pin.
This is a Quad function input/output pin.
General-Purpose Input and General Purpose Output P1.1/ External Interrupt Request 4/ PWM
external trip input/UART Data terminal Ready pin.
This is a multi function input/output pin.
General-Purpose Input and General-Purpose Output P1.2/PWM0 Output/UART Ring Indicator
pin.
This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P1.3/PWM1 Output/UARTData Set Ready
pin.
This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P1.4/PWM2 Output/ SPI0 Master In –
Slave out Pin.
This is a triple function input/output pin.
General-Purpose Input and General-Purpose Output P1.5/ External Interrupt Request 5/ PWM3
Output/ SPI0 Serial Clock Pin.
This is a Quad function input/output pin.
General-Purpose Input and General-Purpose Output P1.6/ External Interrupt Request 6/ PWM4
Output/ SPI0 Master out, Slave in Pin.
This is a Quad function input/output pin.
General-Purpose Input and General-Purpose Output P1.7/ External Interrupt Request 7/ PWM5
Output/ SPI0 Chip Select Pin (Active Low).
This is a Quad function input/output pin.
General-Purpose Input and General Purpose Output P2.0/ I2C Serial Clock Pin. Alternatively,
this pin may be an optional input clock pin for the UART block only.
This is a Triple function input/output pin.
Serial Wire debug clock input pin.
Serial Wire debug data input/output pin.
**Exposed Paddle. The LFCSP_VQ has an exposed paddle that MUST BE connected to digital
ground.
Rev. Pr R| Page 19 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. Common Mode Voltage (Vcm) in Volts vs Input Current in nA, Gain=4, ADC input 250mV, AVdd=3.6V, T=25C
Figure 9. Common Mode Voltage (Vcm) in Volts vs Input Current in nA, Gain=128, ADC input 7.8125mV, AVdd=3.6V, T=25C
14000000
12000000
10000000
8000000
ADC Codes
6000000
4000000
2000000
0
-40 -20 0 20 40 60 80 100 120
Temp
Figure 10. ADC Codes (decimal values) v Die temperature
Rev. Pr R Page 20 of 21
ADuCM360/ADuCM361
Preliminary Technical Data
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
INDICATOR
48
37
36
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.45
0.40
0.35
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
25
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
(CP-48-4)
Figure 11. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
Dimensions shown in millimeters
Rev. Pr R| Page 21 of 21
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
©2012 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their
respective owners.
PR09743-0-5/12(PrR).
PIN 1
INDICATOR
112408-B
7.00
BSC SQ