PDF Data Sheet Rev. A

16-Bit Precision, Low Power Meter On A
Chip with Cortex-M3 and Connectivity
ADuCM350
Data Sheet
FEATURES
Integrated full-speed USB 2.0 controller and PHY
Multilayer advanced microcontroller bus architecture
(AMBA) bus matrix
Central direct memory access (DMA) controller
Real-time clock (RTC)
General-purpose, wake-up, and watchdog timers
Communication
Input/output
I2S and beeper interface
LCD display controller (parallel and serial)
LCD segment controller
SPI, I2C, and UART peripheral interfaces
Programmable GPIOs
Power
Coin cell battery compatible
2.5 V to 3.6 V active measurement range
Power management unit (PMU)
Power-on reset (POR) and power supply monitor (PSM)
Packages and temperature range
Operating temperature range: −40°C to +85°C
Package: 120-lead, 8 mm × 8 mm CSP_BGA
Analog performance
160 kSPS, 16-bit, precision analog-to-digital converter (ADC)
4 dedicated voltage measurement channels
8 current measurement channels
Impedance measurement engine
High precision voltage reference
Supply noise rejection filtering
Ultralow leakage configurable switch matrix
12-bit digital-to-analog converter (DAC)
Precision instrumentation amplifier control loop
6-channel CapTouch controller
Temperature sensor
Analog hardware accelerators
Autonomous analog front-end (AFE) controller
Independent sequencer for AFE functions
Direct digital synthesizer (DDS)/arbitrary waveform
generator
Receive filters
Complex impedance measurement (DFT) engine
Processing
16 MHz ARM Cortex-M3 processor
384 kB of embedded flash memory
32 kB system SRAM
16 kB Flash configured EEPROM
APPLICATIONS
Point-of-care diagnostics
Body-worn devices for monitoring vital signs
Amperometric, voltametric, and impedometric measurements
FUNCTIONAL BLOCK DIAGRAM
PLL
SW/JTAG
1 × 256kB
1 × 128kB
LF XTAL
FLASH
HF OSC
LF OSC
NVIC
16kB
EEPROM
TRACE
DMA
AFE
● 16-BIT PRECISION ADC
● PRECISION REFERENCE
● SWITCH MATRIX
● 12-BIT DAC
● IN-AMP CONTROL LOOP
● TIA
SIGNAL
GENERATION
AFE
CONTROLLER
DFT
USB PHY
AMBA
BUS
MATRIX
SRAM0
(16kB)
SRAM1
(16kB)
POR
USB
PSM
RECEIVE
FILTERS
PDI
LP LDO
CapTouch
HP LDO
SPIH
UART
SPI0
SPI1
I 2C
AHB ‐APB
BRIDGE
ABP‐0
I2S
LCD
TMR0
GPIO
CRC
TMR1
PMU
BEEP
RTC
MISC
ABP‐1
TMR2
WDT
12073-001
HF XTAL
ARM
CORTEX-M3
Figure 1.
Rev. A
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Technical Support
www.analog.com
ADuCM350
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 25
Applications ....................................................................................... 1
Analog Front End ........................................................................... 30
Functional Block Diagram .............................................................. 1
Excitation Stage .......................................................................... 30
Revision History ............................................................................... 2
Measurement Stage .................................................................... 32
General Description ......................................................................... 3
AFE Control ................................................................................ 33
Specifications..................................................................................... 4
CapTouch Features ..................................................................... 33
Analog Front-End Specifications ............................................... 4
MicroSubSystem ............................................................................. 34
Switch Matrix Specifications ....................................................... 5
Memories ..................................................................................... 34
Transimpedance Amplifier Specifications ................................ 6
Debug Capability ........................................................................ 34
ADC Specifications ...................................................................... 6
Programmable GPIOs ............................................................... 34
Temperature Sensor Specifications ............................................ 6
Timers .......................................................................................... 34
CapTouch....................................................................................... 6
USB ............................................................................................... 34
DFT-Based Impedance Measurements ..................................... 7
Power Management and Clocking ........................................... 35
Digital Platform ............................................................................ 7
Display Options .......................................................................... 35
System Clocks/Timers ............................................................... 10
Audio Options ............................................................................ 36
Power Management Specifications .......................................... 12
Development Support .................................................................... 37
Trickle Charger ........................................................................... 12
Documentation........................................................................... 37
Timing Characteristics .............................................................. 13
Hardware ..................................................................................... 37
Absolute Maximum Ratings.......................................................... 19
Software ....................................................................................... 37
Thermal Resistance .................................................................... 19
Packaging and Ordering Information ......................................... 38
ESD Caution ................................................................................ 19
Outline Dimensions ................................................................... 38
Pin Configuration and Function Descriptions ........................... 20
Ordering Guide .......................................................................... 38
REVISION HISTORY
5/14—Revision A: Initial Version
Rev. A | Page 2 of 40
Data Sheet
ADuCM350
GENERAL DESCRIPTION
The ADuCM350 is a complete, coin cell powered, high
precision, meter-on-chip for portable device applications for
applications such as point-of-care diagnostics and body-worn
devices for monitoring vital signs. The ADuCM350 is designed
for high precision amperometric, voltametric, and impedometric
measurement capabilities.
The ADuCM350 analog front end (AFE) features a 16-bit,
precision, 160 kSPS analog-to-digital converter (ADC); 0.17%
precision voltage reference; 12-bit, no missing codes digital-toanalog converter (DAC); and a reconfigurable ultralow leakage
switch matrix. The ADuCM350 also includes an ARM® CortexM3-based processor, memory, and all I/O connectivity to
support portable meters with display, USB communication, and
active sensors. The ADuCM350 is available in a 120-lead, 8 mm
× 8 mm CSP_BGA and operates from −40°C to +85°C.
To support extremely low dynamic and hibernate power
management, the ADuCM350 provides a collection of power
modes and features, such as dynamic and software controlled
clock gating and power gating.
The AFE is connected to the ARM Cortex-M3 via an advanced
high performance bus (AHB) slave interface on the advanced
microcontroller bus architecture (AMBA) matrix, as well as
direct memory access (DMA) and interrupt connections.
Rev. A | Page 3 of 40
ADuCM350
Data Sheet
SPECIFICATIONS
All characterization is at VCCM = 2.5 V to 3.6 V, specifications below 2.5 V are for functionality only, all minimum and maximum
specifications are specified for a temperature range of −40°C to +85°C, unless otherwise noted.
ANALOG FRONT-END SPECIFICATIONS
AFE LDO Specifications
Table 1. AFE LDO Specifications
Parameter
VOLTAGE
Output Voltage
Min
Typ
Max
Unit
Test Conditions/Comments
1.71
1.8
1.89
V
150
200
mV
Measured with a load capacitance (CLOAD) = 0.47 µF; measured with 1 mA
load current on AVDD_RX/TX; all AFE blocks powered down
10 mA load applied; no AFE blocks enabled
1080
0.65
µV/V
mV/mA
10 mA load applied
10 mA load applied
500
µs
Measured with a CLOAD = 0.47 µF; current limit enabled
Dropout
REGULATION
Line
Load
POWER UP
Power-Up Time
High Precision Internal Reference Specifications
Table 2. High Precision Internal Reference Specifications
Parameter
ADC VREF
Reference Voltage Initial Accuracy1
Min
Typ
Max
Unit
Test Conditions/Comments
1.797
1.79
1.8
1.8
1.803
1.803
570
V
V
mΩ
−52
+90
ppm/°C
−45
+48
ppm/°C
For a temperature range of 0°C to 50°C
For a temperature range of −40°C to +85°C
LDO and reference enabled; all other AFE
blocks disabled; reference loaded with
50 µA on VREF
For a temperature range of −40°C to
+85°C, maximum value from −40°C to
+25°C, and from +25°C to +85°C specified
For a temperature range of 0°C to 50°C,
maximum value from −40°C to +25°C, and
from 25°C to 85°C specified
1.797
ppm
V
µV/V
Output Impedance
Temperature Coefficient2
VREF Thermal Hysteresis
REF_EXCITE Switching Load
Line Regulation
Short-Circuit Current to Ground
DAC VREF
Reference Voltage
VBIAS
VBIAS Voltage
1
2
1.789
50
1.793
50
10
mA
1.77
1.8
1.83
V
1.095
1.1
1.102
V
Reference voltage is trimmed unloaded. Measured with CLOAD = 4.7 µF. Measured at 25°C.
Guaranteed by design and/or characterization.
Rev. A | Page 4 of 40
ILOAD = 200 µA; internal ADC measurement
VCCM1 = 2.5 V, VCCM2 = 3.6 V; reference
loaded with 300 µA
Current limit off
Measured with a CLOAD = 0.47 µF; no
current load
Data Sheet
ADuCM350
DAC/RCF/PGA Specifications
Table 3. DAC/PGA/RCF Specifications
Parameter1
DAC
Output Range
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Min
−600
−1
Negative
Offset Error, Midscale
280.7
Unit
Test Conditions/Comments
+600
12
mV
Bits
LSB
As seen by sensor
+1
LSB
±0.2
% FSR
±1
% FSR
±0.2
% FSR
±1
% FSR
±1
mV
320
380.95
PGA (gain = 1), measured at an output of
the excitation loop, DAC code = 0xE00
PGA (gain = 0.025), measured at an output
of the excitation loop, DAC code = 0xE00
PGA (gain = 1), measured at an output of
the excitation loop, DAC code = 0x200
PGA (gain = 0.025), measured at an output
of the excitation loop, DAC code = 0x200
PGA (gain = 1 or gain = 0.025), measured
at an output of the excitation loop across
RCAL
Covered by DAC full-scale error measured
on an output of the excitation loop
Covered by DAC full-scale error measured
on an output of the excitation loop
0.025
RECONSTRUCTION FILTER (RCF)
3 dB Corner Frequency
Measured at an output of the excitation
loop, using gain = 1 and default DAC clock
(16 MHz ÷ 49 DAC clock speed)
Measured at an output of the excitation
loop, using gain = 1 and default DAC clock
(16 MHz ÷ 49 DAC clock speed)
kHz
1
Gain from PGA in State 1
1
Max
±0.85
Full-Scale Error
Positive
Clocking Frequency
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Gain from PGA in State 0
Typ
50
kHz
There may be some system offsets and gain errors that can be calibrated at the system level to improve dc accuracy. Hence, the voltage swing at the output
of the DAC is ±800 mV to guarantee ±600 mV swing on the sensor.
SWITCH MATRIX SPECIFICATIONS
Table 4. Switch Matrix Specifications
Parameter
RON1
Current Carrying Switches
Dx, DR1, Tx, and TR2
IVS
Noncurrent Carrying Switches
Px, Nx, and NR2
PR1
NL
PL
DC OFF LEAKAGE2
T and N Switches
P Switches
D Switches
Min
Typ
Max
Unit
40
40
50
75
Ω
Ω
900
950
350
260
Ω
Ω
Ω
Ω
600
600
260
210
370
pA
340
350
pA
pA
Rev. A | Page 5 of 40
Test Conditions/Comments
Sum value of four T switches and four N
switches
Sum value of four P switches
Sum value of four D switches
ADuCM350
Parameter
DC ON LEAKAGE2
T, N, and P Switches
D Switches
1
2
Data Sheet
Min
Typ
Max
530
340
Unit
Test Conditions/Comments
pA
pA
Sum value for 25 switches, including NL
Sum value for eight switches
RON characterized with a voltage sweep from 0 V to VCCM. Production tested at 1.8 V.
See Figure 38 as a reference. The AFE x pin is driven to 0.2 V.
TRANSIMPEDANCE AMPLIFIER SPECIFICATIONS
Table 5. Transimpedance Amplifier Specifications
Parameter
TRANSIMPEDANCE AMPLIFIER
Maximum Current Sink/Source
Min
Short-Circuit Protection Functionality
Typ
Max
Unit
Test Conditions/Comments
±5
mA
Ensure an RTIA selection to generate ±750 mV swing for optimal
linearity performance
10
mA
ADC SPECIFICATIONS
Table 6. ADC Specifications1
Parameter
ADC
Input Range
No Missing Codes
DNL
INL
Min
Max
Unit
Test Conditions/Comments
1.85
V
Bits
LSB
LSB
Internal reference
16
±0.9
±0.7
±1
LSB
160
54
kSPS
kHz
0.35
Sample Rate After Decimation
3 dB Bandwidth
1
Typ
@ 160 kSPS with respect to an optimal
voltage range of ±750 mV, from 0°C to
50°C
@ 160 kSPS with respect to an optimal
voltage range of ±750 mV, from −40°C to
+85°C
RTIA = 7.5 kΩ, CTIA = 220 pF; ±100 μA current measurement.
TEMPERATURE SENSOR SPECIFICATIONS
Table 7. Temperature Sensor Specifications
Parameter
TEMPERATURE SENSOR
Accuracy
Min
Typ
Max
±1
±2
Unit
Test Conditions/Comments
°C
°C
0°C to 50°C, trimmed at 25°C
−40°C to +85°C, trimmed at +25°C
CapTouch
Table 8. CapTouch Specifications
Parameter
CapTouch™ CHARACTERISTICS
Core Resolution
Core SNR
CAPT_x
Update Rate
Update Rate per Sensor
CAPT_x Input Range
CAPT_x Offset (CapDAC) Range
Min
Typ
Max
14
Unit
±8
Bits
dB
nA
µs
µs
pF
75
pF
60
±10
7.5
7.5
1E6
Rev. A | Page 6 of 40
Test Conditions/Comments
1 kHz test tone, input range of ADC = 1.8 V
GPIO leakage test
Programmable, dependent on configuration
No filtering enabled, clock = 16 MHz
∆CIN is register programmable from 0.5 pF to
9.3 pF
Data Sheet
Parameter
CapDAC Resolution
Output Noise
Peak-to-Peak
RMS
ADuCM350
Min
Typ
0.1
Max
8
1.3
Unit
pF
Test Conditions/Comments
Codes
Codes
DFT-BASED IMPEDANCE MEASUREMENTS
Table 9. DFT-Based Impedance Measurements1
Parameter
IMPEDANCE
Accuracy2
Magnitude
Phase
Precision3
Magnitude
Phase
Min
Typ
Max
Unit
Test Conditions/Comments
0.33
0.17
%
Degrees
Standard deviation as a percent of Z
Standard deviation of Z
0.17
0.08
%
Degrees
Standard deviation as a percent of Z
Standard deviation of Z
For a Z of 181 Ω (0.02% tolerant resistor). Excitation frequency = 20 kHz, sine amplitude = 9 mVRMS, RCAL = 1 kΩ, RTIA = 7.5 kΩ, CTIA = 220 pF. Measurements at 25°C. Single
DFT measurement.
Device-to-device repeatability for 1000 devices.
3
Single device, repeatable measurements.
1
2
DIGITAL PLATFORM
Digital LDO
Table 10. Digital LDO Specifications
Parameter
OUTPUT VOLTAGE
Min
1.71
Typ
1.8
Max
1.89
Unit
V
DROPOUT
150
200
mV
REGULATION
Line
Load
POWER-UP TIME
1.4
0.41
42
Test Conditions/Comments
Measured with a CLOAD = 0.47 µF,
measured with a 10 mA load current on
DVDD
10 mA load applied, no AFE blocks
enabled
mV/V
mV/mA
µs
10 mA load current on DVDD
0 mA to 10 mA load current
Time taken from LDO enable to when LDO
voltage is within specification, CLOAD =
0.47 µF, regulator unloaded
Unit
V
Test Conditions/Comments
mV/V
mV/mA
VCCM = 2.0 V to 3.6 V
0 µA to 100 µA load
Low Power LDO
Table 11. Low Power LDO Specifications
Parameter
OUTPUT VOLTAGE
REGULATION
Line
Load
Min
1.71
Typ
1.8
Max
1.89
0.45
28.5
Rev. A | Page 7 of 40
ADuCM350
Data Sheet
Flash/General-Purpose Flash
Table 12. Flash/General-Purpose Flash Specifications
Parameter
FLASH/GP FLASH
Endurance1
Erase Time
Program Time
Data Retention2
1
2
Min
Typ
Max
20,000
20
20
100
Unit
Test Conditions/Comments
Cycles
ms
µs
Years
@ 1.8 V
@ 1.8 V
Below room temperature
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
Digital Inputs/Outputs: Specified
Specified pin supply range from 2.5 V to 3.6 V.
Table 13. Digital Inputs and Outputs1 Specifications
Parameter
PIN SUPPLY
Impedance
Pull-Down
Pull-Up
Internal Pull-Up/Pull-Down Enabled Leakage2
Digital I/O Leakage Current
Input Capacitance
Input Voltage
Low (VINL)
High (VINH)
Output Voltage
Low (VOL)
VOL High Drive
High (VOH) 3
VOH High Drive
Min
2.5
Typ
3
Max
3.6
20
15
200
.01
10
1
Unit
V
Test Conditions/Comments
kΩ
kΩ
µA
µA
pF
ISINK < 10 µA
ISOURCE < 10 µA
0.3 × pin supply
V
V
0.4
V
V
V
V
0.7 × pin supply
0.4
Pin supply − 0.4
2.4
ISINK = 1.0 mA
ISINK = 1.6 mA
ISOURCE = 1.0 mA
ISOURCE = 1.6 mA
Includes GPIO, debug, SPI, I2C, PDI, LCD, I2S, and beeper.
See Table 35 for details regarding bumps/pins that have pull-up resistors.
3 2
I C does not drive out a high voltage; it uses external pull-up resistors.
1
2
Digital Inputs/Outputs: Functional
Functional pin supply range from 1.65 V to 2.5 V.
Table 14. Digital Inputs/Outputs: Functional Specifications
Parameter
PIN SUPPLY
Input Voltage
Min
1.65
Typ
Max
2.5
Unit
V
Test Conditions/Comments
Low (VINL)
0.3 × pin supply
V
High (VINH)
Output Voltage
0.7 × pin supply
V
0.45
V
ISINK = 1.0 mA
Pin supply − 0.5
V
ISOURCE = 1.0 mA
Low (VOL)
High (VOH)
1
I C does not drive out a high voltage; it uses external pull-up resistors.
1 2
Rev. A | Page 8 of 40
Data Sheet
ADuCM350
Universal Serial Bus Regulator Specifications
Table 15. Universal Serial Bus Regulator Specifications
Parameter
SERIAL BUS REGULATOR
Input Voltage Range
Regulated Output Voltage
Dropout
Regulation
Line
Load
Power-Up Time
Min
Typ
Max
Unit
Test Conditions/Comments
5.25
3.4
440
V
V
mV
40 mA continuous current
0.0043
0.0093
37
%/V
%/mA
µs
3.6
3.2
4.5 V to 5.5 V
@ 5 V, 220 nF ceramic decoupling capacitor
Universal Serial Bus DC Specifications
Table 16. Universal Serial Bus DC Specifications
Parameter
RECEIVER
Single-Ended Input Voltage (Driven)
High
Low
Differential Receiver Input
Common Mode
Sensitivity
TRANSMITTER
Output Voltage
Low (VOL)
Min
Typ
Max
Unit
0.8
V
V
2.0
High (VOH)
0.8
0.2
2.5
0
0.3
V
2.8
3.6
V
44
3.095
Ω
Ω
kΩ
1.575
kΩ
24.8
kΩ
Driver Output Impedance
Term Series Resistor
Pull-Up Resistor (D+ High)
28
Pull-Up Resistor (D+ Low)
0.9
Pull-Down Resistors
14.25
40
1.5
1.425
15
V
V
Test Conditions/Comments
V(USB DP) − V(USB DM)
Pull-up resistor asserted on the USB pin,
USB DP, RPU to AVDD
Pull-down resistor asserted on USB DP and
USB DM (15 kΩ to GND)
RDRIVER + RSERIES
Termination voltage = USB regulator
voltage
Termination voltage = USB regulator
voltage
Universal Serial Bus AC Specifications
Meeting USB 2.0 compliance electrical tests.
Table 17. Universal Serial Bus AC Specifications
Parameter
FULL SPEED DRIVER TIMING
Signaling Rate
Output Time
Rise
Fall
Rise and Fall Matching
Output Voltage Crossover
FULL SPEED JITTER
Driver Jitter Generated
Load Capacitance
Min
Typ
11.988
12
Max
Unit
Test Conditions/Comments
CLOAD = 50 pF
MHz
4
4
90
1.3
20
20
111.1
2.0
ns
ns
%
V
−2
−1
+2
+1
50
ns
ns
pF
Rev. A | Page 9 of 40
VOH − VOL (10% to 90%), CLOAD = 50 pF
VOH − VOL (10% to 90%), CLOAD = 50 pF
Exclude transition from idle
Exclude transition from idle
CLOAD = 50 pF
Next transitions
Paired transitions
Testing slew rate
ADuCM350
Data Sheet
LCD, Charge Pump
Table 18. LCD, Charge Pump Specifications
Parameter
CAPACITANCE
Reservoir Capacitance Between
VLCDVDD and VLCD_GND
Flying Capacitance
VLCD
Switching Voltage
VLCD FLY1
VLCD FLY2
VLCD Charge Pump Switching
Frequency
Minimum VLCD with Respect to
VCCM_ANA and VCCM_DIG
VLCDVDD
VLCDVDD Voltage Range
VLCDVDD Pin Leakage
Min
Typ
0.47
1
Unit
Test Conditions/Comments
µF
2.2
4.7
nF
Between VLCD FLY1 and VLCD FLY2
−0.7
0
VLCD + 0.2
VCCM
V
V
kHz
Top of flying capacitor
Bottom of flying capacitor
V
When <2.1 V after 62.5 ms elapses indicates
fault condition
3
0.2
5
V
nA
nA
ms
5-bit programmable in steps of 40 mV
To VCCM
To GND
VLCDVDD = 0 V to 3.6 V, reservoir = 1 µF,
flying capacitor = 2.2 nF (minimum) and
4.7 nF (maximum)
0.32
%
32
2.1
2.4
VLCDVDD Start-Up Time
VLCDVDD Line Regulation
V_LCD_xx VOLTAGE RANGE
V_LCD_13 Voltage Range
V_LCD_23 Voltage Range
COMx PINS
DC Voltage Across Segment and
COMx Pins
PIN OUTPUT IMPEDANCE
Segment
Common
Max
3.65
VLCD ÷ 3 − 10
2/3 VLCD − 13
VLCD ÷ 3 + 10
2/3 VLCD + 13
mV
mV
50
mV
2000
130
Ω
Ω
SYSTEM CLOCKS/TIMERS
The following tables document the system clock specifications in the ADuCM350.
Platform External Crystal Oscillator
Table 19. Platform External Crystal Oscillator Specifications
Parameter
LOW FREQUENCY
CEXT1 = CEXT2
Frequency
HIGH FREQUENCY
CEXT1 = CEXT2
Frequency
Min
Typ
Max
Unit
Test Conditions/Comments
12
15
18
pF
External capacitor, C1 = C2 (symmetrical
load)
32,768
10
12
8 or 16
Hz
15
Rev. A | Page 10 of 40
pF
MHz
External capacitor
Data Sheet
ADuCM350
On-Chip RC Oscillators
Table 20. On-Chip RC Oscillators Specifications
Parameter
HIGH FREQUENCY RC OSCILLATOR
Frequency
Accuracy
Start-Up Time
LOW FREQUENCY RC OSCILLATOR
Frequency
Accuracy
Start-Up Time
Min
Typ
Max
Unit
+5
MHz
%
µs
+20
Hz
%
µs
Max
Unit
Test Conditions/Comments
32
2500
92
MHz
MHz
ppm
ps
@ 32 MHz, external XTAL
60
2500
68
MHz
MHz
ppm
ps
16
−5
35
32,768
−20
980
Test Conditions/Comments
PLLs
Table 21. PLL Specifications
Parameter
SYSTEM PLL
Input Frequency
Output Frequency
Frequency Error
RMS Jitter
USB PLL
Input Frequency
Output Frequency
Frequency Error
Period Jitter
Min
Typ
8
16
16
8
16
16
16 MHz input
@ 60 MHz, external XTAL
Watchdog, Wake-Up, and General-Purpose Timers
Table 22. Watchdog, Wake-Up, and General-Purpose Timers Specifications
Parameter1
WATCHDOG TIMERS
Timeout Period
Shortest
Longest
WAKE-UP TIMERS
Timeout Period
Shortest
Longest
GENERAL-PURPOSE TIMER × 3
Timeout Period
Shortest
Longest
Timer Output PWM Frequency
1
Min
1
Typ
Max
Unit
Test Conditions/Comments
0.03
8191
ms
sec
32,768 Hz clock, prescaler = 1
32,768 Hz clock, prescaler = 4096
62.5
136
ns
Years
16 MHz clock, prescaler = 1
32,768 Hz clock, prescaler = 32,768
62.5
65,535
ns
sec
MHz
16 MHz clock, prescaler = 1
32,768 Hz clock, prescaler = 32,768
16
Guaranteed by design.
Rev. A | Page 11 of 40
ADuCM350
Data Sheet
POWER MANAGEMENT SPECIFICATIONS
The following tables cover the specifications for the power management section of the ADuCM350.
Power Supplies
Table 23. Power Supplies Specifications
Parameter
SUPPLIES
VCCM_ANA/VCCM_DIG
VCCM_ANA/VCCM_DIG
VBACK
VBUS
VDD_IO
VLCDVDD
Min
2
2.5
1.62
4.75
1.8
1.8
Typ
5
Max
Unit
3.6
3.6
3.6
5.25
3.6
3.6
V
V
V
V
V
V
Test Conditions/Comments
VCCM_x pins connected to the CR2032 battery, main supply for ADuCM350
Battery operating range
Super capacitor pin, back-up mode supply
USB 5 V supply
Supply for some digital I/O pads; see Table 35, I/O supply column for details
Supply for LCD I/O
Power Supply Monitoring
Table 24. Power Supply Monitoring Specifications
Parameter1
VCCM PSM
Voltage Detection Range
Hysteresis
Trip Point Detection Accuracy
VRTC PSM
Voltage Detection Range
Hysteresis
Trip Point Detection Accuracy
VBACK PSM
Voltage Detection Range
Hysteresis
Trip Point Detection Accuracy
1
Min
Typ
Max
Unit
Test Conditions/Comments
1.7
±10
3.2
±100
Hysteresis + 70
V
mV
mV
100 mV step size
1.55
±25
1.7
±100
Hysteresis + 70
V
mV
mV
100 mV step size
1.7
3.2
±100
Hysteresis + 70
V
mV
mV
100 mV step size
For details regarding these parameters, see the UG-587 hardware reference manual.
TRICKLE CHARGER
Table 25. Trickle Charger Specifications
Parameter
CURRENT
Charge Current
Reverse Current
VOLTAGE
Forward Voltage
Min
Typ
Max
Unit
Test Conditions/Comments
mA
μA
Limits load on button cell at power-up
1
120
mV
Where forward current reduces to zero
0.48
40
Rev. A | Page 12 of 40
Data Sheet
ADuCM350
TIMING CHARACTERISTICS
LCD Segment/Common Timing Specifications
Table 26. LCD Segment/Common Timing Specifications1, 2
FRAMESEL[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
FRAMESEL[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FRAMESEL[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FRAMESEL[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fLCD (Hz)
256
204.8
170.7
146.3
128
113.8
102.4
93.1
85.3
78.8
73.1
68.3
64
60.2
56.9
53.9
Static Mux
Frame Rate (Hz)
128
102.4
85.3
73.1
64
56.9
51.2
46.5
42.7
39.4
36.6
34.1
32
30.1
28.4
26.9
fLCD (Hz)
1024
819.2
682.7
585.1
512
455.1
409.6
372.4
341.3
315.1
292.6
273.1
256
240.9
227.6
215.6
4× Mux
Frame Rate (Hz)
128
102.4
85.3
73.1
64
56.9
51.2
46.5
42.7
39.4
36.6
34.1
32
30.1
28.4
26.9
fLCD = fBCLK/(FRAMESEL + 4). See the UG-587 hardware reference manual for details
FRAMESEL[3], FRAMESEL[2], FRAMESEL[1], and FRAMESEL[0] indicate the bit numbers in the LCD_COM register.
I2C Timing
Capacitive load for each of the I2C bus lines (CB) = 400 pF maximum as per I2C bus specifications; I2C timing is guaranteed by design and
not production tested.
Table 27. I2C Timing in Fast Mode (400 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD1
tRSU
tPSU
tBUF
tR
tF
tSUP
1
Description
Clock low pulse width
Clock high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both clock and data
Fall time for both clock and data
Pulse width of spike suppressed
Min
1300
600
600
100
0
600
600
1.3
20 + 0.1 Cb
20 + 0.1 Cb
0
Max
300
300
50
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VINH (minimum) of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
Table 28. I2C Timing in Standard Mode (100 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD1
tRSU
Description
Clock low pulse width
Clock high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Min
4.7
4.0
4.7
250
0
4.0
Rev. A | Page 13 of 40
Max
Unit
μs
ns
μs
ns
μs
μs
ADuCM350
Parameter
tPSU
tBUF
tR
tF
Description
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both clock and data
Fall time for both clock and data
Min
4.0
4.7
Max
Unit
μs
μs
μs
ns
1
300
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VINH (minimum) of the SCL signal) to bridge the undefined region
of the falling edge of SCL.
tBUF
tSUP
tR
SDA (I/O)
MSB
LSB
tDSU
tSHD
tF
tDHD
tR
tRSU
tH
1
SCL (I)
MSB
tDSU
tDHD
tPSU
ACK
8
9
1
2 TO 7
P
S
tL
tSUP
STOP
START
CONDITION CONDITION
S(R)
REPEATED
START
Figure 2. I2C-Compatible Interface Timing
Rev. A | Page 14 of 40
tF
12073-002
1
Data Sheet
Data Sheet
ADuCM350
I2S Timing Specifications
I2S timing is guaranteed by design and not production tested; timing specifications are given for a standard I2S data rate of 2.5 MHz; the
I2S bus is designed to operate up to 25 MHz.
Table 29. I2S Timing: Master Transmitter
Parameter
I2S MASTER TRANSMITTER TIMING
SCLK Period
Minimum Clock Period
Clock High Period
Clock Low Period
Delay
Data Hold Time
Clock Rise Time
1
Symbol
Min
Typ
Max
Unit
T
TTR
360
360
400
440
ns
ns
tHC
tLC
tDTR
tHTR
tRC
160
160
60
ns
ns
ns
ns
ns
300
100
Test Conditions/Comments1
TTR is the minimum allowed clock
period for the transmitter, T > TTR
Minimum > 0.35 × T = 140 ns
Minimum > 0.35 × T = 140 ns
Minimum < 0.80 × T = 320 ns
Minimum > 0 ns
Minimum > 0.15 × TTR = 54 ns (slave
mode only)
T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.
Table 30. I2S Timing: Slave Receiver
Parameter
I2S SLAVE RECEIVER TIMING
SCLK Period
Clock High Period
Clock Low Period
Data Setup Time
Data Hold Time
Min
Typ
Max
Unit
Test Conditions/Comments1
T
tHC
tLC
tSR
tHTR
360
110
160
400
440
ns
ns
ns
ns
ns
TTR = 360 ns
Minimum < 0.35 × T = 126 ns
Minimum < 0.35 × T = 126 ns
Minimum < 0.20 × T = 72 ns
Minimum < 0 ns
300
100
T refers to the typical value listed for the SCLK period; therefore, T = 400 ns in this case.
T
tRC*
tLC ≥ 0.35T
SCLK
tHC ≥ 0.35T
VH = 2.0V
tHTR ≥ 0
VL = 0.8V
tDTR ≤ 0.8T
SD/WS
*tRC IS ONLY RELEVANT FOR TRANSMITTERS IN SLAVE MODE.
NOTES
1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).
Figure 3. I2S-Compatible Interface Transmitter Timing
Rev. A | Page 15 of 40
12073-003
1
Symbol
ADuCM350
Data Sheet
T
tLC ≥ 0.35T
tHC ≥ 0.35T
VH = 2.0V
SCLK
VL =0.8V
tSR ≥ 0.2T
tHTR ≥ 0
12073-004
SD
AND
WS
NOTES
1. SD = SERIAL DATA, WS = WORD SELECT, WS = 0: CHANNEL 1 (LEFT), WS = 1: CHANNEL 2 (RIGHT).
Figure 4. I2S-Compatible Interface Receiver Timing
SPI Timing
SPIH can be used for high data rate peripherals.
Table 31. SPI Master Mode Timing1
Parameter
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
2
Min
Typ
(SPIXDIV[5:0] + 1) × tUCLK
(SPIXDIV[5:0] + 1) × tUCLK
0
Max
12
12
12
12
35.5
35.5
35.5
35.5
35.5
(SPIDIV + 1) × tUCLK
58.7
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Guaranteed by design.
tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.
CS
SCLK
(POLARITY = 0)
1/2 SCLK
CYCLE
3/4 SCLK
CYCLE
tCS
tSFS
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MOSI
MISO
MSB
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
LSB
LSB IN
12073-005
1
Description
SCLK low pulse width2
SCLK high pulse width2
Data output valid after SCLK edge
Data output setup before SCLK edge2
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDHD
Figure 5. SPI Master Mode Timing (Phase Mode = 1)
Rev. A | Page 16 of 40
Data Sheet
ADuCM350
1 SCLK CYCLE
1 SCLK CYCLE
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
MOSI
tDR
MSB
MSB IN
LSB
BIT 6 TO BIT 1
LSB IN
12073-006
MISO
BIT 6 TO BIT 1
tDSU
tDHD
Figure 6. SPI Master Mode Timing (Phase Mode = 0)
Table 32. SPI Slave Mode Timing
Parameter
tCS
Description
CS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
Typ
Max
Unit
ns
(SPIXDIV[5:0] + 1) × tUCLK
(SPIDIV[5:0] + 1) × tUCLK
62.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49.1
20.2
10.1
12
12
12
12
35.5
35.5
35.5
35.5
25
0
tUCLK = 62.5 ns. It corresponds to the maximum internal clock frequency before clock dividers.
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MISO
MSB
MOSI
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
tDSU
12073-007
1
Min
38
tDHD
Figure 7. SPI Slave Mode Timing (Phase Mode = 1)
Rev. A | Page 17 of 40
ADuCM350
Data Sheet
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
MOSI
MSB
MSB IN
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
12073-008
MISO
tDR
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (Phase Mode = 0)
Rev. A | Page 18 of 40
Data Sheet
ADuCM350
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 33.
Parameter
Supplies
VCCM_ANA, VCCM_DIG, VLCDVDD,
VDD_IO, VBACK to AGND_x/DGNDx
Decoupling
DVDD, AVDD_RX/TX, VBIAS, VREF, VUSB
Digital Input/Output
P0.x, P1.x, P2.x, P3.x, P4.x, BOOT, RESETX
TRACEx
Switch Matrix (RCAL 1, RCAL 2, AFE x)
TIA (TIA_I, TIA_O)
Analog Inputs (AN_x)
REF_EXCITE
VLCD FLY1, VLCD FLY2
V_LCD_13, V_LCD_23
VBUS to DGND
USB DM, USB DP to DGND
HF_XTALx, LF_XTALx
Analog Ground to Digital Ground
AGND CTOUCH, AGND_RX/TX, AGND_REF
to DGND, DGND1, DGND2, DGND USB
Rating
−0.3 V to +3.6 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
−0.3 V to +2.0 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +5.25 V
−0.3 V to +3.6 V
−0.3 V to +1.98 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages; assumes
use of a JEDEC 4-layer board.
Table 34. Thermal Resistance
Package Type
CSP_BGA
ESD CAUTION
−0.3 V to +0.3 V
Rev. A | Page 19 of 40
θJA
35
Unit
°C/W
ADuCM350
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2
3
4
5
6
7
A
DNC
P2.1/
COM1/
RESX
P2.3/
COM3/
DCX
8
P2.5/S2/
ECLOCKWRX
P1.0/S3/
D0/SCL
P1.2/S5/
D2/DIN
P1.4/S7/
D4
P1.6/S9/
D6
P1.8/S11/
D8
P1.10/
S13/D10
P1.12/
S15/D12
P1.14/
S17/D14
P2.10/S23
P2.9/S22
P2.15/S28
B
V_LCD_23
P2.0/
COM0
P2.2/
COM2/
CSX
P2.4/S1/
P1.1/S4/
RWX-RDX D1/DOUT
P1.3/S6/
D3
P1.5/S8/
D5
P1.7/S10/
D7
P1.9/S12/
D9
P1.11/
S14/D11
P1.13/
S16/D13
P1.15/
S18/D15
P2.11/S24 P2.12/S25
P2.8/S21
C
HF_XTAL2
V_LCD_13
P3.10/S31
P2.7/S20/
TOUTA
D
HF_XTAL1
VLCDVDD
P2.13/S26
P2.6/
S19/TE
E
VUSB
VLCD FLY1
P3.11/S32 P2.14/S27
F
USB DM
VLCD FLY2
DGND
USB
G
USB DP
VBUS
H
TMSSWDIO/
P0.8
J
DGND2/ P3.8/S29
LCD_GND
9
10
11
12
13
14
15
P3.3/
SPI0_CS
P3.0/
SPI0_SCLK
P3.2/
SPI0_MOSI
DGND1
P3.4/
I2CSCL/
SPI1_SCLK
P3.1/
SPI0_MISO
P3.6/UTX/
TOUTB/
SPI1_MOSI
TCKSWCLK/
P0.9
VCCM_
DIG
P3.5/
I2CSD/
SPI1_MISO
DGND
VDD_IO
TDO-SWO/
P0.6/UTX
TDI/P0.7/
URX
P3.14/
LRCLK
P3.7/URX/
TOUTC/
SPI1_CS
P0.4/
CAPT_E
P0.1/
CAPT_B
K
DVDD
P0.11
P3.12/
BEEP/
BMCLK
AGND_REF
P0.3/
CAPT_D
P0.0/
CAPT_A
L
P4.0/
I2CSCL
P4.1/
I2CSD
P0.5/
CAPT_F
P0.2/
CAPT_C
M
VBACK
P0.15/
SPIH_CS
TRACE0
TRACECLK
N
LF_XTAL2
BOOT
TRACE2
TRACE1
P
LF_XTAL1
P0.13/
SPIH_MISO
P0.14/
SPIH_MOSI
VCCM_
ANA
RCAL 1
AFE 2
AFE 4
AFE 6
AFE 8
VBIAS
TIA_I
AN_A
AN_B
AGND
CTOUCH
TRACE3
R
P4.2/
TOUTB
P0.10/
TOUTC
P0.12/
SPIH_SCLK
AVDD_RX/
AVDD_TX
RCAL 2
AFE 1
AFE 3
AFE 5
AFE 7
VREF
TIA_O
REF_
EXCITE
AN_C
AN_D
TRST
P3.13/
BEEPX/
SDATA
RESETX
P3.9/S30
AGND_RX/
AGND_TX
12073-009
1
Figure 9. Bump Location (Top View Looking Through Device, Bumps Not to Scale)
Table 35. Pin Function Descriptions
Pin No.
Mnemonic
Power and Ground
P4
VCCM_ANA
I/O1
I/O Supply2
GPIO
Pull-Up/Down2
S
VCCM_ANA
N/A
H6
VCCM_DIG
S
VCCM_DIG
N/A
G2
M1
VBUS
VBACK
S
S
VBUS
VBACK
N/A
N/A
H15
E1
R10
VDD_IO
VUSB
VREF
S
A
A
VDD_IO
VUSB
N/A
N/A
N/A
N/A
P10
VBIAS
A
N/A
N/A
Rev. A | Page 20 of 40
Description
Battery Connection and Analog Circuit Power.
Connect VCCM_ANA to the CR2032 battery.
VCCM_ANA powers the analog circuits. This
pin is connected to VCCM_DIG internally.
Battery Connection and Digital Circuit Power.
Connect VCCM_DIG to the CR2032 battery.
VCCM_DIG powers the digital circuits. This pin
is connected to VCCM_ANA internally.
5 V USB Supply Voltage.
RTC Supply. Connect VBACK to the super
capacitor.
VDD_IO Supply.
Regulated USB 3.6 V Supply.
1.8 V Reference Voltage Decoupling Capacitor
Pin.
1.1 V Bias Voltage Decoupling Capacitor Pin.
Data Sheet
ADuCM350
Pin No.
K1
R4
Mnemonic
DVDD
AVDD_RX/AVDD_TX
I/O1
A
A
I/O Supply2
N/A
AVDD TX/RX
GPIO
Pull-Up/Down2
N/A
N/A
K9
K10
H14
G6
F7
F6
AGND_RX/AGND_TX
AGND_REF
DGND
DGND1
DGND2/LCD_GND
DGND USB
G
G
G
G
G
G
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AFE Pins
P12
P13
R13
R14
P5
AN_A
AN_B
AN_C
AN_D
RCAL 1
A
A
A
A
A
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
N/A
N/A
N/A
N/A
N/A
R5
RCAL 2
A
VCCM_ANA
N/A
R6
P6
R7
P7
R8
P8
R9
P9
P11
AFE 1
AFE 2
AFE 3
AFE 4
AFE 5
AFE 6
AFE 7
AFE 8
TIA_I
A
A
A
A
A
A
A
A
A
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
VCCM_ANA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
R11
TIA_O
A
VCCM_ANA
N/A
R12
REF_EXCITE
Debug Interface
J1
TDO-SWO/P0.6/UTX
A
VCCM_ANA
N/A
I/O
VCCM_DIG
Pull-up
J2
TDI/P0.7/URX
I/O
VCCM_DIG
Pull-up
H1
TMS-SWDIO/P0.8
I/O
VCCM_DIG
Pull-up
H2
TCK-SWCLK/P0.9
I/O
VCCM_DIG
Pull-down
R15
M15
M14
N15
N14
P15
TRST
TRACECLK
TRACE0
TRACE1
TRACE2
TRACE3
I
O
O
O
O
O
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
N/A
N/A
N/A
N/A
N/A
N/A
Rev. A | Page 21 of 40
Description
1.8 V Digital Regulator Decoupling Capacitor Pin.
1.8 V Analog Regulator Decoupling Capacitor
Pin for Receiver (Rx)/Transmitter (Tx) Circuits.
Rx/Tx Analog Ground.
Reference Ground.
Digital Ground.
Digital Ground.
Digital Ground/Ground for LCD.
USB Ground. Connect DGND USB to the
digital ground plane.
ADC Mux Input.
ADC Mux Input.
ADC Mux Input.
ADC Mux Input.
Terminal A of Calibration Resistor. Connect
RCAL 1 to the switch matrix.
Terminal B of Calibration Resistor. Connect
RCAL 2 to the switch matrix.
Uncommitted AFE Pin 1.
Uncommitted AFE Pin 2.
Uncommitted AFE Pin 3.
Uncommitted AFE Pin 4.
Uncommitted AFE Pin 5.
Uncommitted AFE Pin 6.
Uncommitted AFE Pin 7.
Uncommitted AFE Pin 8.
Transimpedance Amplifier Input. Connect the
IV resistor to this pin.
Transimpedance Amplifier Output. Connect
the IV resistor to this pin.
Gated Precision Reference Voltage.
JTAG Serial Data Output or Serial Wire Trace
Output/GPIO/UART_TX. This is a
multifunction pin.
JTAG Serial Data Input/GPIO/UART_RX. This is
a multifunction pin.
JTAG Test Mode Select or Serial Wire
Data/GPIO. This is a multifunction pin.
JTAG Test Clock or Serial Wire Clock/GPIO. This
is a multifunction pin.
Trace Reset.
Trace Clock.
Trace Data 0.
Trace Data 1.
Trace Data 2.
Trace Data 3.
ADuCM350
Data Sheet
Pin No.
SPI H
R3
Mnemonic
I/O1
I/O Supply2
GPIO
Pull-Up/Down2
P0.12/SPIH_SCLK
I/O
VCCM_DIG
Pull-up
P2
P0.13/SPIH_MISO
I/O
VCCM_DIG
Pull-up
P3
P0.14/SPIH_MOSI
I/O
VCCM_DIG
Pull-up
M2
P0.15/SPIH_CS
I/O
VCCM_DIG
Pull-up
Other Serial Ports
F14
P3.0/SPI0_SCLK
G14
P3.1/SPI0_MISO
F15
P3.2/SPI0_MOSI
F10
P3.3/SPI0_CS
I/O
I/O
I/O
I/O
VDD_IO
VDD_IO
VDD_IO
VDD_IO
Pull-up
Pull-up
Pull-up
Pull-up
G10
P3.4/I2CSCL/SPI1_SCLK
I/O
VDD_IO
Pull-up
H10
P3.5/I2CSD/SPI1_MISO
I/O
VDD_IO
Pull-up
G15
P3.6/UTX/TOUTB/SPI1_MOSI
I/O
VDD_IO
Pull-up
J10
P3.7/URX/TOUTC/SPI1_CS
I/O
VDD_IO
Pull-up
I/O
I/O
VCCM_DIG
VCCM_DIG
N/A
N/A
USB Data −.
USB Data +.
A
VCCM_DIG
Pull-up
USB
F1
USB DM
G1
USB DP
CapTouch Interface
K15
P0.0/CAPT_A
Description
GPIO/Serial Port H Clock. This is a dual
function pin.
GPIO/Serial Port H MISO. This is a dual
function pin.
GPIO/Serial Port H MOSI. This is a dual
function pin.
GPIO/Serial Port H Chip Select (Active Low).
This is a dual function pin.
GPIO/SPI 0 SCLK. This is a dual function pin.
GPIO/SPI 0 MISO. This is a dual function pin.
GPIO/SPI 0 MOSI. This is a dual function pin.
GPIO/SPI 0 Chip Select (Active Low). This is a
dual function pin.
GPIO (External Interrupt 7)/I2C Clock/SPI 1
SCLK. This is a multifunction pin.
GPIO/I2C Data/SPI 1 MISO. This is a
multifunction pin.
GPIO/UART Tx/Timer B Output/SPI 1 MOSI.
This is a multifunction pin.
GPIO/UART Rx/Timer C Output/SPI 1 Chip
Select (Active Low). This is a multifunction pin.
J15
P0.1/CAPT_B
A
VCCM_DIG
Pull-up
L15
P0.2/CAPT_C
A
VCCM_DIG
Pull-up
K14
P0.3/CAPT_D
A
VCCM_DIG
Pull-up
J14
P0.4/CAPT_E
A
VCCM_DIG
Pull-up
L14
P0.5/CAPT_F
A
VCCM_DIG
Pull-up
P14
AGND CTOUCH
System Clocks
P1
LF_XTAL1
N1
LF_XTAL2
D1
HF_XTAL1
C1
HF_XTAL2
Display
E2
VLCD FLY1
F2
VLCD FLY2
D2
VLCDVDD
C2
V_LCD_13
G
N/A
N/A
GPIO (External Interrupt 1)/CapTouch A. This is
a dual function pin.
GPIO (External Interrupt 2)/CapTouch B. This is
a dual function pin.
GPIO (External Interrupt 3)/CapTouch C. This is
a dual function pin.
GPIO (External Interrupt 4)/CapTouch D. This
is a dual function pin.
GPIO (External Interrupt 5)/CapTouch E. This is
a dual function pin.
GPIO (External Interrupt 6)/CapTouch F. This is
a dual function pin.
Capacitance to Digital Converter AC Shield.
A
A
A
A
RTC_VBACK
RTC_VBACK
DVDD
DVDD
N/A
N/A
N/A
N/A
32 kHz XTAL Pin.
32 kHz XTAL Pin.
16 MHz XTAL Pin.
16 MHz XTAL Pin.
A
A
S
A
VLCD VDD
VLCD VDD
N/A
VLCD VDD
N/A
N/A
N/A
N/A
B1
A
VLCD VDD
N/A
LCD Flying Capacitor Top Plate.
LCD Flying Capacitor Bottom Plate.
Full-Scale LCD Voltage Output or VLCD Supply.
One-Third (1/3) LCD Voltage. Leave this pin as
no connect.
Two-Thirds (2/3) LCD Voltage. Leave this pin
as no connect.
V_LCD_23
Rev. A | Page 22 of 40
Data Sheet
ADuCM350
Pin No.
B2
Mnemonic
P2.0/COM0
I/O1
I/O
I/O Supply2
VLCD VDD
GPIO
Pull-Up/Down2
Pull-up
A2
P2.1/COM1/RESX
I/O
VLCD VDD
Pull-up
B3
P2.2/COM2/CSX
I/O
VLCD VDD
Pull-up
A3
P2.3/COM3/DCX
I/O
VLCD VDD
Pull-up
B4
P2.4/S1/RWX-RDX
I/O
VLCD VDD
Pull-up
A4
P2.5/S2/ECLOCK-WRX
I/O
VLCD VDD
Pull-up
A5
P1.0/S3/D0/SCL
I/O
VLCD VDD
Pull-down
B5
P1.1/S4/D1/DOUT
I/O
VLCD VDD
Pull-down
A6
P1.2/S5/D2/DIN
I/O
VLCD VDD
Pull-down
B6
A7
B7
A8
B8
P1.3/S6/D3
P1.4/S7/D4
P1.5/S8/D5
P1.6/S9/D6
P1.7/S10/D7
I/O
I/O
I/O
I/O
I/O
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
Pull-down
Pull-down
Pull-down
Pull-down
Pull-down
A9
B9
A10
P1.8/S11/D8
P1.9/S12/D9
P1.10/S13/D10
I/O
I/O
I/O
VLCD VDD
VLCD VDD
VLCD VDD
Pull-down
Pull-down
Pull-down
B10
P1.11/S14/D11
I/O
VLCD VDD
Pull-down
A11
P1.12/S15/D12
I/O
VLCD VDD
Pull-down
B11
P1.13/S16/D13
I/O
VLCD VDD
Pull-down
A12
P1.14/S17/D14
I/O
VLCD VDD
Pull-down
B12
P1.15/S18/D15
I/O
VLCD VDD
Pull-down
D15
C15
P2.6/S19/TE
P2.7/S20/TOUTA
I/O
I/O
VLCD VDD
VLCD VDD
Pull-down
Pull-down
B15
A14
A13
B13
B14
D14
E15
A15
F8
F9
C14
E14
P2.8/S21
P2.9/S22
P2.10/S23
P2.11/S24
P2.12/S25
P2.13/S26
P2.14/S27
P2.15/S28
P3.8/S29
P3.9/S30
P3.10/S31
P3.11/S32
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
VLCD VDD
Pull-down
Pull-down
Pull-down
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Rev. A | Page 23 of 40
Description
GPIO/Common Output 0 for LCD Back Plane
(COM 0). This is a dual function pin.
GPIO/COM 1/Parallel Display Interface (PDI)
Reset. This is a multifunction pin.
GPIO/COM 2/PDI Chip Select. This is a
multifunction pin.
GPIO/COM 3/PDI Data Select. This is a
multifunction pin.
GPIO/Segment Driver 1 (SEG 1)/PDI R/WX or
RDX. This is a multifunction pin.
GPIO/SEG 2/PDI E Clock Output (Motorola Bus
Mode) or PD Write Select (Intel® Bus Mode).
This is a multifunction pin.
GPIO/SEG 3/PDI D0/PDI Serial Port Clock. This
is a multifunction pin.
GPIO/SEG 4/PDI D1/PDI Serial Port Data
Output. This is a multifunction pin.
GPIO/SEG 5/PDI D2/PDI Serial Port Data Input.
This is a multifunction pin.
GPIO/SEG 6/PDI D3. This is a multifunction pin.
GPIO/SEG 7/PDI D4. This is a multifunction pin.
GPIO/SEG 8/PDI D5. This is a multifunction pin.
GPIO/SEG 9/PDI D6. This is a multifunction pin.
GPIO/SEG 10/PDI D7/System Clock Output.
This is a multifunction pin.
GPIO/SEG 11/PDI D8. This is a multifunction pin.
GPIO/SEG 12/ PDI D9. This is a multifunction pin.
GPIO/SEG 13/PDI D10. This is a multifunction
pin.
GPIO/SEG 14/PDI D11. This is a multifunction
pin.
GPIO/SEG 15/PDI D12. This is a multifunction
pin.
GPIO/SEG 16/PDI D13. This is a multifunction
pin.
GPIO/SEG 17/PDI D14. This is a multifunction
pin.
GPIO/SEG 18/PDI D15. This is a multifunction
pin.
GPIO/SEG 19/TE. This is a multifunction pin.
GPIO/SEG 20/Timer A Output. This is a multifunction pin.
GPIO/SEG 21. This is a dual function pin.
GPIO/SEG 22. This is a dual function pin.
GPIO/SEG 23. This is a dual function pin.
GPIO/SEG 24. This is a dual function pin.
GPIO/SEG 25. This is a dual function pin.
GPIO/SEG 26. This is a dual function pin.
GPIO/SEG 27. This is a dual function pin.
GPIO/SEG 28. This is a dual function pin.
GPIO/SEG 29. This is a dual function pin.
GPIO/SEG 30. This is a dual function pin.
GPIO/SEG 31. This is a dual function pin.
GPIO/SEG 32. This is a dual function pin.
ADuCM350
Data Sheet
Pin No.
Mnemonic
Miscellaneous Digital Input/Output
K8
RESETX
L1
P4.0/I2CSCL
I/O1
I/O Supply2
GPIO
Pull-Up/Down2
I
I/O
VCCM_DIG
VCCM_DIG
Pull-up
Pull-up
L2
R1
P4.1/I2CSD
P4.2/TOUTB
I/O
I/O
VCCM_DIG
VCCM_DIG
Pull-up
Pull-up
R2
P0.10/TOUTC
I/O
VCCM_DIG
Pull-up
K2
N2
P0.11
BOOT
I/O
I
VCCM_DIG
VCCM_DIG
Pull-up
Pull-down
A1
Audio
K6
DNC
N/A
N/A
P3.12/BEEP/BMCLK
I/O
VCCM_DIG
Pull-down
K7
P3.13/BEEPX/SDATA
I/O
VCCM_DIG
Pull-down
J6
P3.14/LRCLK
I/O
VCCM_DIG
Pull-down
1
2
S is supply, A is analog input, I is digital input, O is digital output, I/O is digital input/output, and G is ground.
N/A means not applicable.
Rev. A | Page 24 of 40
Description
Reset Pin (Active Low).
GPIO (External Interrupt 0)/I2C Clock. This is a
dual function pin.
GPIO/I2C Data. This is a dual function pin.
GPIO/Timer B Output. This is a dual function
pin.
GPIO (External Interrupt 8)/Timer C Output.
This is a dual function pin.
GPIO (External Clock Input Pin).
The device enters serial download mode if
this pin is held high during, and for a short
time after, a reset. It executes user code after
any reset event or if the pin is low.
Do Not Connect. Leave this pin floating.
GPIO/Beeper Output Positive/I2S Bit Clock.
This is a multifunction pin.
GPIO/Beeper Output Negative/I2S Serial Data
Output. This is a multifunction pin.
GPIO/I2S Frame Clock. This is a dual function pin.
Data Sheet
ADuCM350
TYPICAL PERFORMANCE CHARACTERISTICS
1.8010
1.8010
1.8009
1.8005
1.8008
10mA LOAD
VREF VOLTAGE (V)
ALDO VOLTAGE (V)
VCCM = 3.6V
1.8000
1.7995
1.7990
1.8007
1.8006
VCCM = 2.5V
1.8005
1.8004
1.8003
1.8002
1.7985
3.00
3.25
3.50
VCCM (V)
1.8000
–0.0003
12073-010
2.75
–0.0002
–0.0001
0
LOAD CURRENT (A)
Figure 10. ALDO Line Regulation
12073-013
1.8001
1.7980
2.50
Figure 13. VREF Load Regulation
1.810
1.804
REF_EXCITE VOLTAGE (V)
1.802
ALDO VOLTAGE (V)
1.805
1.800
1.795
1.800
1.798
1.796
–0.008
–0.006
–0.004
–0.002
0
ALDO CURRENT (A)
1.792
–0.0003
12073-011
1.790
–0.010
0
–0.0001
–0.0002
REF_EXCITE LOAD CURRENT (A)
12073-014
1.794
Figure 14. REF_EXCITE Load Regulation
Figure 11. ALDO Load Regulation
1.80100
1.10004
1.80095
1.10002
1.80090
300µA LOAD ON VREF
1.10000
VBIAS (V)
1.80080
1.80075
1.80070
1.80065
1.09998
1.09996
1.09994
1.80060
1.09992
1.80050
2.5
2.7
2.9
3.1
3.3
VCCM (V)
3.5
Figure 12. VREF Line Regulation
1.09990
2.5
2.7
2.9
3.1
3.3
VCCM (V)
Figure 15. VBIAS Line Regulation
Rev. A | Page 25 of 40
3.5
12073-015
1.80055
12073-012
VREF (V)
1.80085
Data Sheet
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
TIA_O DNL (LSB)
0.2
0
–0.2
0.2
0
–0.2
–0.6
VCCM
VCCM = 3.6V
VCCM = 3.0V
VCCM = 2.4V
–1.0
10200 15200 20200 25200 30200 35200 40200 45200 50200
CODE
–1.0
10000 15000 20000 25000 30000 35000 40000 45000 50000
CODE
Figure 16. ADC TIA_O INL (16-Bit) vs. Code (±150 μA)
Figure 19. ADC TIA_O DNL (16-Bit) vs. Code (Temperature)
1.0
1.0
VCCM
VCCM
0.6
0.8
VCCM = 3.6V
VCCM = 3.0V
VCCM = 2.4V
0.4
AN _A INL (LSB)
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
10200 15200 20200 25200 30200 35200 40200 45200 50200
–1.0
17500
CODE
12073-017
TIA_O DNL (LSB)
VCCM = 3.6V
VCCM = 3.0V
VCCM = 2.4V
0.6
32500
37500
42500
Figure 20. ADC AN_A INL (16-Bit) vs. Code
1.0
50°C
25°C
0°C
VCCM
VCCM = 3.0 V
0.8
0.6
0.4
0.4
AN _A DNL ( LSB )
0.6
0.2
0
–0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
10000 15000 20000 25000 30000 35000 40000 45000 50000
–1.0
17500
CODE
VCCM = 3.6V
VCCM = 3.0V
VCCM = 2.4V
0.2
–0.4
12073-018
TIA_O INL (LSB)
0.8
27500
CODE
Figure 17. ADC ADC TIA_O DNL (16-Bit) vs. Code
1.0
22500
12073-020
0.8
12073-019
–0.8
12073-016
–0.8
VCCM = 3.0 V
–0.4
–0.4
–0.6
50°C
25°C
0°C
22500
27500
32500
37500
42500
CODE
Figure 21. ADC AN_A DNL (16-Bit) vs. Code
Figure 18. ADC ADC TIA_O INL (16-Bit) vs. Code (Temperature)
Rev. A | Page 26 of 40
12073-021
TIA_O INL (LSB)
ADuCM350
Data Sheet
1.0
1.0
VCCM = 3.0V
50°C
25°C
0°C
0.8
2.5V
3.0V
3.6V
0.8
0.6
0.4
0.4
DAC INL (LSB)
0.6
0.2
0
0.2
0
–0.4
–0.6
–0.6
–0.8
–0.8
22510
27510
32510
37510
42510
47510
–1.0
CODE
0
500
0.8
1.0
VCCM = 3.0V
50°C
25°C
0°C
1500
2000
CODE
2500
3000
3500
4000
Figure 25. DAC INL (12-Bit) vs. Code
Figure 22. ADC AN_A INL (16-Bit) vs. Code (Temperature)
1.0
1000
12073-025
–0.4
–1.0
17510
2.5V
3.0V
3.6V
0.8
0.6
0.4
0.4
DAC DNL (LSB)
0.6
0.2
0
–0.2
MEASURED ACROSS RCAL
ATTEN OFF
COMP OFF
DAC CODE 0x200 TO 0xE00
0.2
0
–0.4
–0.6
–0.6
–0.8
–0.8
22510
27510
32510
37510
42510
–1.0
12073-023
–1.0
17510
47510
CODE
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
Figure 23. ADC AN_A DNL (16-Bit) vs. Code (Temperature)
12073-026
–0.2
–0.4
Figure 26. DAC DNL (12-Bit) vs. Code
100
DAC CODE = 0x800 (MIDSCALE)
VCCM = 3.3V
MEASURED AT RCAL
0
–3
10
(µV/√Hz)
–6
–9
DAC_ATTEN_EN = 0
1
–12
DAC_ATTEN_EN = 1
0.1
–18
1k
3.6V
3.0V
2.4V
10k
100k
FREQUENCY (Hz)
0.01
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 27. Noise Spectral Density
Figure 24. Receive Channel Antialias Filter Roll-Off
Rev. A | Page 27 of 40
100k
12073-027
–15
12073-024
AMPLITUDE (dB)
AN _A DNL (LSB)
MEASURED ACROSS RCAL
ATTEN OFF
COMP OFF
DAC CODE 0x200 TO 0xE00
–0.2
–0.2
12073-022
AN _A INL (LSB)
ADuCM350
ADuCM350
Data Sheet
1.6
500
0x400 TO 0xC00
400
NUMBER OF UNITS
VOLTAGE AT RCAL (V)
1.4
1.2
1.0
0.8
0xC00 TO 0x400
1000 MEASUREMENTS
ON 1 ADuCM350 DEVICE
Z = 127Ω + 56nF
SINE AMPLITUDE = 9mV rms
DAC_ATTEN_EN = 1
RTIA = 7.5kΩ
450
350
300
250
200
150
100
0.6
–5
0
5
10
15
20
25
0
181.5
12073-028
–10
30
TIME (µs)
500
1000 ADuCM350
DEVICES MEASURED
50
40
30
20
350
300
250
200
150
100
10
191.13
191.23
191.32
IMPEDANCE MAGNITUDE (Ω)
191.42
0
12073-029
191.04
40.08
80
40.48
40.68
40.88
41.08
IMPEDANCE PHASE (°)
Figure 29. Impedance Measurement Magnitude Accuracy
1000 ADuCM350
DEVICES MEASURED
40.28
12073-031
50
0
190.94
Figure 32. Impedance Measurement Phase Precision
18000
Z = 127Ω + 56nF
SINE AMPLITUDE = 9mV rms
DAC_ATTEN_EN = 1
RTIA = 7.5kΩ
4.662pF_G1
6.993pF_G1
9.324pF_G1
2.331pF_G2
4.662pF_G2
6.993pF_G2
9.324pF_G2
2.331pF_G4
4.662pF_G4
6.993pF_G4
9.324pF_G4
16000
14000
70
12000
CDC CODES
60
50
40
10000
8000
6000
30
20
4000
10
2000
0
–48.66
–48.63
–48.59
–48.55
–48.52
IMPEDANCE PHASE (°)
–48.48
0
12073-030
NUMBER OF UNITS
185.2
Z = 127Ω + 56nF
SINE AMPLITUDE = 9mV rms
DAC_ATTEN_EN = 1
RTIA = 7.5kΩ
400
MUMBER OF UNITS
NUMBER OF UNITS
1000 MEASUREMENTS
ON 1 ADuCM350 DEVICE
450
60
90
184.4
Figure 31. Impedance Measurement Magnitude Precision
70
100
183.7
CAPDAC COMPENSATED
AT 50pF
AUTOZERO = 2µs
HOLD TIME = 2µs
PH13 = 2µs
PH23 = 4µs
0
5
10
15
20
25
30
35
40
45
50
INPUT CAPACITANCE (pF)
Figure 33. CapTouch Linearity
Figure 30. Impedance Measurement Phase Accuracy
Rev. A | Page 28 of 40
55
60
65
70
12073-033
80
Z = 127Ω + 56nF
SINE AMPLITUDE = 9mV rms
DAC_ATTEN_EN = 1
RTIA = 7.5kΩ
183.0
IMPEDANCE MAGNITUDE (Ω)
Figure 28. Settling Time of the DAC at RCAL
90
182.2
12073-032
50
0.4
–15
Data Sheet
ADuCM350
3.5
20
1kHz TONE
0
3.0
–20
–40
GPIO P1.1 LOW DRIVE
–60
VOH (V)
AMPLITUDE (dB)
GPIO P1.1 HIGH DRIVE
2.5
–80
–100
–120
2.0
1.5
1.0
–140
0.5
0
10
20
30
40
50
60
70
80
FREQUENCY (kHz)
0.7
0.6
0.4
GPIO P1.1 LOW DRIVE
0.3
0.2
GPIO P1.1 HIGH DRIVE
0.1
0
0.002
0.003
0.004
0.005
IOL (A)
0.006
0.007
12073-035
VOL (V)
0.5
0.001
IOH (A)
Figure 36. GPIO VOH vs. IOH
Figure 34. CapTouch SNR
0
0
–0.016 –0.014 –0.012 –0.010 –0.008 –0.006 –0.004 –0.002
Figure 35. GPIO VOL vs. IOL
Rev. A | Page 29 of 40
0
0.002
12073-036
–180
12073-034
–160
ADuCM350
Data Sheet
ANALOG FRONT END
SWITCH
MATRIX
RCAL 1
RCAL
RCAL 2
AFE 8
EXCITATION ATTEN
AMPLIFIER 1 OR 40
LP RCF
50kHz
12-BIT
DAC
D
DAC CODE
(ARBITRARY)
VREFDAC
GAIN AND
OFFSET
CAL
AFE 6
X
AFE 4
AFE 2
AFE 1
ADC
MUX
N
AFE 3
VBIAS
TEMP
SENS
T
TIA_I
TIA_O
RTIA AN_A
AN_B
AN_C
AN_D
VCCM
DVDD
AVDD
GAIN
1 OR 1.5
AAF
55kHz
HANN
WINDOW
VREFADC
16-BIT
ADC
GAIN AND
OFFSET
CAL
SINC2HF
DFT
N = 2048
(12.8ms)
RE
IM
50Hz/60Hz
REJECTION
178 SINC2LF
160kSPS
900SPS
900SPS
12073-037
Y
AFE 5
DIFFERENTIAL
INPUTS
RZ
TRAPEZOID
GENERATION
326.53kSPS
P
SINGLED ENDED
INPUTS
EXAMPLE
CONFIGURATION
AFE 7
SINE
GENERATION
Figure 37. AFE System Block Diagram
For full details on the ADuCM350, refer to the UG-587
hardware reference manual.
The ADuCM350 is a high accuracy, configurable, AFE with a
low power, peripheral rich, microcontroller subsystem.
EXCITATION STAGE
The excitation/transmit stage consists of a 12-bit DAC with an
excitation buffer and an instrumentation amplifier in a feedback
path to the DAC, which forces an accurate voltage across the
impedance to be measured, thereby removing parasitics from
the measurement system.
All measurements are referenced to a precision external resistor,
which is used in the internal calibration loop to ensure no dc
bias across an unknown impedance.
A large range of impedances can be measured, depending on
the application. Users can optimize the calibration resistor
(RCAL), ac amplitude of the excitation waveform, and the
current-to-voltage (IV) resistor to tailor fit the system to the
application demands. Impedances can be measured from 80 Hz
to ~75 kHz.
The switch matrix offers the user full configurability with 34
user selectable switches. The current carrying switches on both
excitation buffer output and the transimpedance input are optimally sized for current loads. The switch matrix allows the device
to measure and store offset and gain results. The ADuCM350
can self calibrate Rx offset and gain, Tx offset and gain, and
switch leakage. This off loads the requirement for an extensive
factory calibration routine and removes temperature and aging
induced errors from measurements.
Rev. A | Page 30 of 40
Data Sheet
ADuCM350
D2
D3
D4
EXCITATION
AMPLIFIER
D5
D6
EXCITATION
D
D7
D8
DR1
RCAL 1
PL
RCAL 2
PR1
P2
P3
P4
P5
P
P6
P7
P8
N1
N2
N3
N4
N
N5
N6
N7
NR2
NL
T1
T2
VBIAS
TIA
T3
T4
T
T5
6
T6
T7
IVS
TIA_I
TIA_O
RTIA
TR2
AFE 1
AFE 2
AFE 3
AFE 4
AFE 5
AFE 6
12073-038
AFE 7
AFE 8
Figure 38. Switch Matrix
Rev. A | Page 31 of 40
ADuCM350
Data Sheet
MEASUREMENT STAGE
The AFE consists of a multiplexed input, 160 kSPS, 16-bit ADC
with four dedicated voltage measurement channels and up to
eight multiplexed current measurement channels using the onchip transimpedance amplifier. The multiplexed channels are
filtered and differentially buffered prior to data conversion.
The DFT engine performs a 2048-point single frequency
discrete Fourier transform. It takes the 16-bit ADC output and
converts it to complex impedance with real and imaginary
components. As the ADC samples at 160 kSPS, this allows for a
79.5 Hz signal energy bandwidth, which gives excellent
rejection of interferers.
100
The ADC data can be interrogated using three methods.
• By raw data at 160 kSPS.
• At the output of a 50 Hz/60 Hz filter at 900 SPS.
• Through a discrete Fourier transform (DFT) engine.
The power line filter is optimized for fast settling, just 36.6 ms
settling. Data at 900 SPS can be further decimated by the user
without requiring additional filtering.
MAGNITUDE (dB)
50
0
–50
–100
NOTCHES ARCHITECTED AT 50Hz
AND 60Hz TO REJECT POWER LINE
INTERFERENCE
–20
–40
–150
–60
–200
0
0.5
–80
–100
100
200
300
400
500
600
FREQUENCY (Hz)
700
800
900
3500
4000
1.5
2.0
FREQUENCY (Hz)
2.5
3.0
3.5
Figure 40. Frequency Response, 2048-Point DFT at 20 kHz
0
–20
–40
–60
–80
–100
0
500
1000
1500
2000
2500
3000
FREQUENCY (Hz)
12073-040
Figure 39. Power Line Rejection Modeling
TEMPERATURE
SENSOR
VBIAS
+
+
TIA_O
RTIA
AN_A
AN_B
AN_C
AN_D
AVDD/2
DVDD/2
VCCM
VBIAS
CTIA
PRECISION
REFERENCE
+
VREF = 1.8V
–
+ –
– +
–
ADC
–
–
+
+
VREF
12073-039
–
TIA_I
ANTIALIAS
FILTERING
MAGNITUDE (dB)
0
1.0
Figure 41. Rx Stage
Rev. A | Page 32 of 40
12073-041
MAGNITUDE (dB)
0
Data Sheet
ADuCM350
AFE CONTROL
AFE
DATA
FIFO
(TO M3)
WAVEFORM
GENERATOR
DFT
50Hz/60Hz
FILTER
MMR
SYSTEM BUS
ANALOG
BLOCKS
DSP
ACCELERATORS
ARM
CORTEX-M3
INTERRUPT
GENERATION
COMMAND
FIFO
12073-042
SEQUENCER
Figure 42. AFE Control
The sequencer handles low level AFE operations and allows the
AFE to perform its functions independently. It performs cycle
accurate precision AFE measurements asynchronously of the
core.
The sensor input configuration is very flexible and uses several
techniques to ensure that there are no false touches (that is, no
registering touches caused by a changing environment) on the
external sensors. To minimize noise pickup from the system,
the ADuCM350 CapTouch core includes several algorithms,
such as median and averaging filtering measurements, as well
as configurable excitation frequency and duty cycle. The
subsystem includes a self timer and touch-and-release routines
to optimize the power consumption and reduce the computing
workload in the ARM Cortex-M3.
The sequencer allows the user to create parameterized waveforms using the waveform generator block. The waveforms can
be trapezoids or sinusoids. Arbitrary waveforms are possible
using the AFE sequencer and DMA transfers.
CAPACITIVE
TOUCH
BU_ONOFF
BU_LEFT
BU_RIGHT
BU_UP
BU_DOWN
BU_ENTER
SINE
GENERATION
DAC
DAC CODE
(DC)
PCB
AGND_TX
CapTouch
12073-043
TRAPEZOID
GENERATION
Figure 44. CapTouch External Interface
Figure 43. Waveform Generation
CAPTOUCH FEATURES
The ADuCM350 incorporates a capacitive touch subsystem that
interfaces with up to six capacitive touch channels in self
capacitance mode and incorporates high performance
capacitance sensing circuitry without external components.
Rev. A | Page 33 of 40
12073-044
The AFE can be controlled by the ARM Cortex-M3 via MMRs.
All blocks within the AFE are fully controllable and observable
using the MMR registers. Access the MMRs through an AHB
bus or indirectly through a programmable sequencer. There are
two dedicated DMA channels to remove burden from the ARM
Cortex-M3 to manage data and control FIFOs.
ADuCM350
Data Sheet
MICROSUBSYSTEM
MEMORIES
In power saving mode, GPIO pins retain state; they tristate on
reset to prevent any bus irritation. GPIOs of note are as follows:
The memory offerings for the ADuCM350 are as follows:
•
•
•
•
•
• 32 pins multiplexed with LCD segment common pins
• Six pins multiplexed with CapTouch
• Nine pins on a dedicated VDDIO for ease of interfacing to
peripherals
384 kB flash.
16 kB of flash configured for EEPROM emulation.
2 kB user information.
32 kB SRAM.
2 kB dedicated SRAM for USB endpoint.
TIMERS
Flash
General-Purpose Timers
The ADuCM350 includes 384 kB of embedded flash memory,
accessed using the flash controller. The flash controller is connected to the bus matrix as a slave device for core and DMA
access, as well as the 32-bit AHB for MMR access.
ADuCM350 has three identical general-purpose timers, each
with a 16-bit count-up/count-down counter. The countup/count-down counter can be clocked from one of four user
selectable clock sources. Any selected clock source can be scaled
down using a prescaler of 16, 256, or 32,768.
The flash controller supports 384 kB of user space and 2 kB of
information space. Read and write to flash are executed via
AHB only. The 384 kB flash memory comprises one 256 kB
flash array and one 128 kB flash array. The 256 kB flash
memory array and 128 kB flash array are controlled by two
separate flash controllers with separate register controls.
With respect to flash integrity, the device supports
•
•
•
•
•
Automatic signature check of information space at reset
User signature for application code
Parity checking on a per access basis
20,000 cycle endurance with 20 ms erase and 20 μs program
100-year data retention at room temperature
General-Purpose Flash
The device contains 16 kB of embedded flash memory for
general purpose, such as EEPROM emulation.
SRAM
There is 32 kB of SRAM on chip of which 16 kB is retained
during hibernate mode and an optional 16 kB can be retained
during hibernate for reduced leakage current.
DEBUG CAPABILITY
The ADuCM350 supports two types of debug host interface:
4-wire JTAG debug (JTAG) interface and a serial 2-wire debug
(SWD) interface.
The ADuCM350 incorporates the complete embedded trace of
the ARM Cortex-M3 features to maximize code analysis, system
profiling, and debugging capabilities.
PROGRAMMABLE GPIOS
The ADuCM350 has 66 GPIO pins, most of which have
multiple, configurable functions defined by user code. They can
be configured as an input/output and have programmable pullup or pull-down resistors. All I/O pins are functional over the
full supply range (VBAT = 1.8 V to 3.6 V).
Watch Dog Timer (WDT)
The watchdog timer is a 16-bit count-down timer with a programmable prescaler. The prescaler source is selectable and can be
scaled by a factor of 1, 16, 256, or 4096. The watchdog timer is
clocked either by the 32 kHz crystal oscillator (LFXTAL) or by
the 32 kHz on-chip oscillator (LFOSC).The watchdog timer
(WDT) is used to recover from an illegal software state. After
the WUT is enabled by user code, it requires periodic servicing
to prevent it from forcing a reset or interrupt of the processor. A
WDT timeout can generate a reset or an interrupt.
Wake-Up Timer
The wake-up timer (WUT) consists of a 32-bit counter clocked
from the 32 kHz external crystal (LFXTAL), 32 kHz internal
oscillator (LFOSC), or peripheral clock (PCLK). The selected
clock source can be scaled
USB
The USB port on the ADuCM350 is a USB 2.0 full speed compliant port. The module consists of the USB controller, USB
PHY, USB RAM, and a 2-channel DMA. An integrated regulator
powered by VBUS supplies the USB PHY. A dedicated PLL with
60 MHz clock capability is available for clock generation.
The USB supports bulk, isochronous, interrupt, and control modes.
It has seven hardware endpoint and a dedicated 2-channel DMA. It
supports suspend and wakeup.
The controller hardware is supplemented by a complete set of
USB device class drivers to provide complete USB functionality
using a defined Micrium stack. The USB stack has a requirement
for an RTOS to be on the system. Analog Devices, Inc., has
developed its system using the Micrium μC/OS-II.
Rev. A | Page 34 of 40
Data Sheet
ADuCM350
POWER MANAGEMENT AND CLOCKING
Power Modes
The PMU provides control of the ADuCM350 power modes
and allows the ARM Cortex-M3 to control the clocks and
power gating to reduce the dynamic power and hibernate
power.
There are four power modes available; each mode provides an
additional low power benefit with a corresponding reduction in
functionality.
• Active mode—all peripherals can be enabled. Active power is
managed by optimized clock management.
• Core sleep—the core is clock gated but the remainder of the
system is active. No instructions can be executed in this
mode, but DMA transfers can continue between peripherals
and memory.
• System sleep—in system sleep, most peripherals are clock
gated and are no longer user programmable; the interrupt
controller remains active and the NVIC processes wake-up
events for a limited number of sources.
• Hibernate mode—some limited state retention, limited
number of wake-up interrupts, and the RTC is active.
The device also has a backup mode that supplies minimum
power to the RTC and associated circuitry from a super
capacitor. The RTC can run for >12 hours with an 80 mF
capacitor.
Power Management
The ADuCM350 has an integrated power management system
to optimize performance and extend battery life of the device.
See the UG-587 hardware reference manual for additional
details.
The power management system consists of
•
•
•
•
•
•
•
•
Integrated analog and digital LDOs regulated to 1.8 V.
Hibernate mode from 2.0 V to 3.6 V.
High performance AFE measurement from 2.5 V to 3.6 V.
Integrated power switches for low standby current in
hibernate mode.
Integrated smart diode trickle charger for a super capacitor
for use in backup mode.
Dedicated VDDIO voltage via nine GPIO pins for peripheral
interoperability.
Dedicated regulator for USB transceiver and bus supplied
from the VUSB pin.
Dedicated supervisory circuits for fail safe operation,
including power supply monitors of DVDD during flash
read/writes, PSM of VCCM to monitor supply during AFE
measurements, and PSM on the LFXTAL block to monitor
the clock source for RTC.
Clocking
Two on-chip oscillators and driver circuitry for two external
crystals are available on the ADuCM350: LFOSC is a 32 kHz
internal oscillator, HFOSC is a 16 MHz internal oscillator, and
LFXTAL is a 32 kHz external crystal oscillator, and HFXTAL is
a 16 MHz external crystal oscillator.
The ADuCM350 supports either 8 MHz or 16 MHz resonant
circuits. The HF RC oscillator has an accuracy of ±5%. A low
jitter clock source is used for accurate AFE measurements.
The USB has a frequency accuracy requirement of ±200 ppm.
The USB control logic must be clocked at >30 MHz. A
USBPHYCLK for clocking the USB PHY is also available and
must use a 60 MHz clock.
The low frequency clocking is optimized for ultralow power
applications. The RTC requires that the 32.768 kHz XTAL be
activated to run for 12 hours off a fully charged 0.08 F super
capacitor.
Real Time Clock
The RTC contains a low power crystal oscillation circuit that
operates in conjunction with a 32,768 Hz external crystal. It
achieves 25 ppm performance in keeping time at 25°C when
used with a 10 ppm crystal class load capacitors.
Features of the RTC include
• A 32-bit count register of the time in seconds from a known
reference point.
• A prescaler that divides down the 32,768 Hz crystal input to
1 Hz to advance the seconds count.
• RTC alarm and interrupt flags.
• Digital trim capability to allow a positive or negative
adjustment to the RTC count at fixed intervals.
DISPLAY OPTIONS
LCD Segment Display Driver and Controller
The ADuCM350 contains an on-chip LCD controller capable of
directly driving an LCD panel. For LCD functionality, 36 pins
are available on the device.
The LCD controller supports driving up to 128 segments, as
well as selectable multiplex option. The static option consists of
one backplane × 32 frontplanes and the 4× mux option consists
of four backplanes × 32 frontplanes. The LCD controller also
supports LCD waveform voltages that are generated using
internal charge pump circuitry and support levels from 2.4 V up
to 3.6 V LCDs, programmable frame rates, interrupt generation
at the frame boundary (for updating LCD data), and the LCD
frame clock (generated by using the on-board 32 kHz crystal).
LCD Display Controller Options
The LCD controller also has the ability to drive external LCD
display modules. It has 25 pins for the display interface, which
support data transfers of up to 16 bits.
Display controller supports Type A, Type B, and Type C of the
MIPI DBI Specification Version 2.0. Specifically, both Fixed-E
mode and Clocked-E mode options of the Type A interface are
supported, as well as all bus width options (8-/9-/16-bit data) for
Rev. A | Page 35 of 40
ADuCM350
Data Sheet
Type A and Type B, and 9-bit (Option 1) and 8-bit (Option 3)
serial interfaces for Type C.
By using the display controller, the depth on various interfaces
is as follows:
• 8-bit interface is 8, 12, or 16 bits per pixel (not 18 or 24).
• 9-bit interface is 18 bits per pixel (not 8, 12, 16, or 24).
• 16-bit interface is 8, 12, or 16 bits per pixel (not 18 or 24).
AUDIO OPTIONS
The ADuCM350 has an integrated audio driver for beeper and
an integrated I2S port.
Beeper
The beeper driver module in the ADuCM350 generates a
differential square wave of programmable frequency. It drives
an external piezoelectric sound component whose two
terminals connect to the differential square wave output.
The beeper driver consists of a module that can deliver
frequencies from 8 kHz to ~0.25 kHz. It operates on a fixed
independent 32 kHz (32,768 Hz) clock source that is unaffected
by changes in system clocks.
A timer allows for programmable tone durations from 4 ms to
1.02 sec in 4 ms increments. Single-tone (pulse) and multitone
(sequence) modes provide versatile playback options.
In sequence mode, the beeper can be programmed to play any
number of tone pairs from 1 to 254 (2 to 508 tones) or be
programmed to play forever (until stopped by the user).
Interrupts are available to indicate the start or end of any beep,
the end of a sequence, or that the sequence is nearing
completion.
I2S
The device supports I2S. The purpose of the I2S port is to
provide audio data to an amplifier, which drives a small
speaker. The I2S features available on the ADuCM350 include
the following:
•
•
•
•
•
•
•
Data samples of up to 24 bits.
Frame clocks from 8 kHz to 192 kHz.
Master/slave mode.
8-deep Tx FIFOs.
DMA mode with address autoincrement.
Interrupt mode.
Downsampling transfers.
Rev. A | Page 36 of 40
Data Sheet
ADuCM350
DEVELOPMENT SUPPORT
DOCUMENTATION
The ADuCM350 hardware reference manual details the
functionality of each block on the ADuCM350. It includes
power management, clocking, memories, peripherals, and the
AFE.
HARDWARE
The EVAL-ADuCM350EBZ evaluation kit is available to
prototype a user’s sensor configuration with the ADuCM350. A
selection of daughter cards are available to interrogate peripheral
performance, including CapTouch, PDI, LCD segment, beeper,
and I2S.
SOFTWARE
The EVAL-ADuCM350EBZ includes a complete development
and debug environment for the ADuCM350. The software
development kit (SDK) for the ADuCM350 uses the IAR
Embedded Workbench for ARM as its development
environment.
The SDK consists of full working AFE examples of power-up
sequences, calibration sequences, and measurement routines.
These AFE example routines are documented in the UG-587
hardware reference manual with supporting timing diagrams.
The SDK also includes operating system (OS) aware drivers and
example code for all the peripherals on the device, including
SPI, I2C, CapTouch, PDI, and so forth.
Also available in the support package is the ADuCM350 AFE
development GUI that operates from the National Instruments
LabVIEW® environment. This GUI allows the user to rapidly
prototype different sensors with the ADuCM350 AFE to evaluate
its high precision performance.
Rev. A | Page 37 of 40
ADuCM350
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
A1 BALL
CORNER
8.10
8.00 SQ
7.90
15
14
13
12
11
10
9
8
7
6
5
4
3
2
A1 BALL
CORNER
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7.00
BSC SQ
0.50
TOP VIEW
*1.35
1.23
1.14
BOTTOM VIEW
0.50 REF
DETAIL A
DETAIL A
1.08
1.01
0.94
0.22 NOM
0.17 MIN
0.35
COPLANARITY
0.30
0.08
0.25
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-275-CCCE-1 WITH
EXCEPTION TO PACKAGE HEIGHT.
04-02-2013-A
SEATING
PLANE
Figure 45. 120-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-120-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADuCM350BBCZ
ADuCM350BBCZ-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
120-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
120-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Z = RoHS Compliant Part.
Rev. A | Page 38 of 40
Package Option
BC-120-3
BC-120-3
Data Sheet
ADuCM350
NOTES
Rev. A | Page 39 of 40
ADuCM350
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12073-0-5/14(A)
www.analog.com/ADuCM350
Rev. A | Page 40 of 40