NCP4641 D

NCP4641
150 mA, Wide Input Range,
Voltage Regulator
The NCP4641 is a CMOS 150 mA linear voltage regulator with
high input voltage and ultra−low supply current. It incorporates
multiple protection features such as peak current limit, short circuit
current limit and thermal shutdown to ensure a very robust device.
A high maximum input voltage tolerance of 50 V and a wide
temperature range make the NCP4641 suitable for a variety of
demanding applications.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
XXX
XMM
Operating Input Voltage Range: 4 V to 36 V
Output Voltage Range: 2.0 to 12.0 V (0.1 steps)
±2% Output Voltage Accuracy
Output Current: min 150 mA (VIN = 8 V, VOUT = 5 V)
Line Regulation: 0.05%/V
Peak Current Limit Circuit
Short Current Limit Circuit
Thermal Shutdown Circuit
Available in SOT−89−5 and SOIC6−TL Package
These are Pb−Free Devices
SOIC6−TL
CASE 751BR
1
XXX
XMM
SOT−89 5
CASE 528AB
Typical Applications
• Power source for home appliances
• Power source for car audio equipment, navigation system
• Power source for notebooks, digital TVs, cordless phones and private
LAN systems
• Power source for office equipment machines such as copiers,
printers, facsimiles, scanners, projectors, etc.
NCP4641x
VIN
VIN
C1
100n
VOUT
CE
GND
1
XXXX
MM
= Specific Device Code
= Date Code
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
VOUT
C2
100n
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 1
1
Publication Order Number:
NCP4641/D
NCP4641
VIN
VOUT
Internal
VR
Vref
Current Limit
Short Protection
Thermal Shutdown
CE
GND
Figure 2. Simplified Schematic Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
SOT89
Pin No.
SOIC6−TL
Pin Name
5
6
VIN
Input pin
2
2
GND
Ground pin, all ground pins must be connected together when it is
mounted on board
4
4
GND
Ground pin, all ground pins must be connected together when it is
mounted on board
−
5
GND
Ground pin, all ground pins must be connected together when it is
mounted on board
3
3
CE
1
1
VOUT
Description
Chip enable pin (“H” active)
Output pin
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2
NCP4641
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Input Voltage
Rating
VIN
−0.3 to 50
V
Peak Input Voltage (Note 1)
VIN
60
V
Output Voltage
VOUT
−0.3 to VIN + 0.3 ≤ 50
V
Chip Enable Input
VCE
−0.3 to VIN + 0.3 ≤ 50
V
Output Current
IOUT
250
mA
900
mW
PD
Power Dissipation SOT−89
Power Dissipation SOIC6−TL
1700
Junction Temperature
TJ
−40 to 150
°C
Storage Temperature
TSTG
−55 to 125
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Duration time = 200 ms
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, SOT−89
Thermal Resistance, Junction−to−Air
RqJA
111
°C/W
Thermal Characteristics, SOIC6−TL
Thermal Resistance, Junction−to−Air
RqJA
59
°C/W
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3
NCP4641
ELECTRICAL CHARACTERISTICS TA = 25°C
Parameter
Test Conditions
Operating Input Voltage
Output Voltage
Output Voltage Temp. Coefficient
Line Regulation
Load Regulation
Dropout Voltage
Output Current
VIN = VOUT + 3 V, IOUT = 1 mA
Symbol
Min
Max
Unit
VIN
4
36
V
VOUT
x0.98
x1.02
V
VIN = VOUT + 3 V, IOUT = 1 mA, TA = −40 to
105°C
VIN = VOUT + 1.5 V to 36 V, IOUT = 1 mA
VIN = VOUT + 3 V,
IOUT = 1 mA to 40 mA
IOUT = 20 mA
2.0 V ≤ VOUT < 5.0 V
VIN = VOUT + 3 V
ppm/°C
±100
LineReg
0.05
0.20
%/V
LoadReg
10
25
mV
20
35
5.0 V ≤ VOUT < 12.0 V
2.0 V ≤ VOUT < 3.7 V
Typ
VDO
(Note 3)
3.7 V ≤ VOUT < 4.0 V
0.35
0.60
4.0 V ≤ VOUT < 5.0 V
0.25
0.40
5.0 V ≤ VOUT < 12.0 V
0.20
0.35
2.0 V ≤ VOUT < 3.0 V
IOUT
mA
100
3.0 V ≤ VOUT < 5.0 V
120
5.0 V ≤ VOUT < 12.0 V
150
V
Short Current Limit
VOUT = 0 V
ISC
50
Quiescent Current
VIN = VOUT + 3 V, IOUT = 0 mA
IQ
9
20
mA
mA
Standby Current
VIN = 36 V, VCE = 0 V
ISTB
0.1
1
mA
CE Pin Threshold Voltage
CE Input Voltage “H”
VCEH
CE Input Voltage “L”
VCEL
V
1.5
0.3
Thermal Shutdown Temperature
TSD
150
°C
Thermal Shutdown Release
Temperature
TSR
125
°C
VIN = 6 V, VOUT = 3.0 V, IOUT = 30 mA, f = 1 kHz
PSRR
27
dB
VOUT = 3.0 V, IOUT = 30 mA, f = 10 Hz to
100 kHz
VN
112
mVrms
Power Supply Rejection Ratio
Output Noise Voltage
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Dropout voltage for 2.0 V ≤ VOUT < 3.7 V can be computed by this formula: VDO = 4 V − VOUTSET
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4
NCP4641
TYPICAL CHARACTERISTICS
6.0
3.5
3.0
5.5 V
6.5 V
2.0
6.0 V
1.5
8.0 V
3.0
1.0
0.5
0
50
100
150
IOUT (mA)
200
250
0.0
300
0
50
Figure 3. Output Voltage vs. Output Current
3.0 V Version (TJ = 25 5C)
7.0
6.0
200
250
300
105°C
2.0
TJ = 25°C
VDO (V)
10 V
5.0
150
IOUT (mA)
2.5
10.5 V
11 V
11.5 V
8.0
100
Figure 4. Output Voltage vs. Output Current
5.0 V Version (TJ = 25 5C)
9.0
VOUT (V)
7.5 V
2.0
1.0
0.0
VIN = 8.5 V
4.0
VOUT (V)
VOUT (V)
2.5
7.0 V
5.0
VIN = 5.0 V
4.0
3.0
2.0
1.5
−40°C
1.0
0.5
1.0
0.0
0
50
100
150
200
250
0.0
300
0
2.5
2.5
2.0
2.0
105°C
TJ = 25°C
1.0
75
100
125
150
1.5
1.0
TJ = 25°C
−40°C
0.5
50
Figure 6. Dropout Voltage vs. Output Current
3.0 V Version
VDO (V)
VDO (V)
Figure 5. Output Voltage vs. Output Current
8.0 V Version (TJ = 25 5C)
1.5
25
IOUT (mA)
IOUT (mA)
105°C
0.5
−40°C
0.0
0
25
50
75
IOUT (mA)
100
125
0.0
150
Figure 7. Dropout Voltage vs. Output Current
5.0 V Version
0
25
50
75
IOUT (mA)
100
125
Figure 8. Dropout Voltage vs. Output Current
8.0 V Version
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5
150
NCP4641
TYPICAL CHARACTERISTICS
3.05
5.05
VIN = 5.0 V
3.03
5.03
3.02
5.02
3.01
5.01
3.00
2.99
5.00
4.99
2.98
4.98
2.97
4.97
2.96
4.96
2.95
−40
−20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
VIN = 8.0 V
5.04
VOUT (V)
VOUT (V)
3.04
4.95
−40
100
Figure 9. Output Voltage vs. Temperature,
3.0 V Version
14
8.06
8.02
IGND (mA)
VOUT (V)
VOUT = 5.0 V
12
8.04
8.00
7.98
7.96
10
8
8.0 V
6
3.0 V
4
7.94
2
7.92
−20
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
0
100
0
Figure 11. Output Voltage vs. Temperature,
8.0 V Version
3.5
12
3.0
8
5.0 V
8.0 V
2
0.5
20
40
60
80
35
0.0
100
20 mA
1.5
1.0
0
30
1 mA
2.0
4
−20
10
15
20
25
VIN, INPUT VOLTAGE (V)
2.5
VOUT = 3.0 V
VOUT (V)
IGND (mA)
10
5
Figure 12. Supply Current vs. Input Voltage
14
0
−40
100
16
VIN = 11 V
8.08
6
0
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Output Voltage vs. Temperature,
5.0 V Version
8.10
7.90
−40
−20
IOUT = 40 mA
0
5
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (°C)
VIN, INPUT VOLTAGE (V)
Figure 13. Supply Current vs. Temperature
Figure 14. Output Voltage vs. Input Voltage,
3.0 V Version
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6
35
NCP4641
TYPICAL CHARACTERISTICS
9.0
6.0
8.0
5.0
7.0
1 mA
3.0
2.0
5.0
20 mA
4.0
3.0
IOUT = 40 mA
2.0
1.0
0.0
1 mA
6.0
20 mA
VOUT (V)
VOUT (V)
4.0
IOUT = 40 mA
1.0
0
5
10
15
20
25
VIN, INPUT VOLTAGE (V)
30
0.0
35
0
5
Figure 15. Output Voltage vs. Input Voltage,
5.0 V Version
100
90
90
80
80
IOUT = 1 mA
50
40
0.1
1
10
100
100 mA
0.1
1
10
100
FREQUENCY (kHz)
Figure 17. PSRR, 3.0 V Version, VIN = 6.0 V
Figure 18. PSRR, 5.0 V Version, VIN = 8.0 V
1000
12
10
VN (mVrms/√Hz)
70
PSRR (dB)
30 mA
FREQUENCY (kHz)
80
60
50
IOUT = 1 mA
30
0
0.01
40
0
0.01
1000
90
10
IOUT = 1 mA
10
100
20
50
20
100 mA
10
40
60
30
30 mA
20
0
0.01
35
70
PSRR (dB)
PSRR (dB)
70
30
30
Figure 16. Output Voltage vs. Input Voltage,
8.0 V Version
100
60
10
15
20
25
VIN, INPUT VOLTAGE (V)
6
4
2
30 mA
100 mA
0.1
8
1
10
FREQUENCY (kHz)
100
0
0.01
1000
Figure 19. PSRR, 8.0 V Version, VIN = 11 V
0.1
1
10
FREQUENCY (kHz)
100
1000
Figure 20. Output Voltage Noise, 3.0 V Version,
VIN = 6.0 V, IOUT = 30 mA
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NCP4641
TYPICAL CHARACTERISTICS
25
50
45
40
VN (mVrms/√Hz)
15
10
5
35
30
25
20
15
10
5
1
10
FREQUENCY (kHz)
100
0
0.01
1000
Figure 21. Output Voltage Noise, 5.0 V Version,
VIN = 8.0 V, IOUT = 30 mA
0.1
1
10
FREQUENCY (kHz)
12
10
8
VOUT (V)
6
4
4.50
2
4.00
3.50
3.00
2.50
2.00
0
0.2
0.4
0.6
0.8
1.0 1.2
t (ms)
1.4
1.6
1.8
2.0
Figure 23. Line Transients, 3.0 V Version,
tR = tF = 5 ms, IOUT = 1 mA
14
12
10
8
6
6.00
4
5.50
5.00
4.50
4.00
3.50
0
0.2
0.4
0.6
0.8
100
1000
Figure 22. Output Voltage Noise, 8.0 V version,
VIN = 11.0 V, IOUT = 30 mA
VIN (V)
0.1
1.0 1.2
t (ms)
1.4
1.6
1.8
Figure 24. Line Transients, 5.0 V Version,
tR = tF = 5 ms, IOUT = 1 mA
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8
2.0
VIN (V)
0
0.01
VOUT (V)
VN (mVrms/√Hz)
20
NCP4641
TYPICAL CHARACTERISTICS
17
15
13
9
9.00
7
8.50
VIN (V)
VOUT (V)
11
8.00
7.50
7.00
6.50
0
0.2
0.4
0.6
0.8
1.0 1.2
t (ms)
1.4
1.6
1.8
2.0
Figure 25. Line Transients, 8.0 V Version,
tR = tF = 5 ms, IOUT = 1 mA
200
150
100
0
1.24
1.22
IOUT (mA)
VOUT (V)
50
1.20
1.18
1.16
1.14
0
20
40
60
80
100 120 140 160 180 200
t (ms)
Figure 26. Load Transients, 3.0 V Version,
IOUT = 1 – 20 mA, tR = tF = 50 ms, VIN = 6.0 V
200
150
100
0
2.83
2.81
2.79
2.77
2.75
2.73
0
20
40
60
80
100 120 140 160 180 200
t (ms)
Figure 27. Load Transients, 5.0 V Version,
IOUT = 1 – 20 mA, tR = tF = 50 ms, VIN = 8.0 V
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IOUT (mA)
VOUT (V)
50
NCP4641
TYPICAL CHARACTERISTICS
200
150
100
0
5.05
5.03
IOUT (mA)
VOUT (V)
50
5.01
4.99
4.97
4.95
0
20
40
60
80
100 120 140 160 180 200
t (ms)
Figure 28. Load Transients, 8.0 V Version,
IOUT = 1 – 20 mA, tR = tF = 50 ms, VIN = 11.0 V
8
Chip Enable
6
4
0
4
IOUT = 20 mA
3
VCE (V)
VOUT (V)
2
IOUT = 1 mA
2
IOUT = 150 mA
1
0
−1
0
50
100 150 200 250 300 350 400 450 500
t (ms)
Figure 29. Start−up, 3.0 V Version, VIN = 6.0 V
Chip Enable
10
8
6
2
8
0
IOUT = 20 mA
6
4
IOUT = 1 mA
2
IOUT = 150 mA
0
−2
0
50
100 150 200 250 300 350 400 450 500
t (ms)
Figure 30. Start−up, 5.0 V Version, VIN = 8.0 V
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10
VCE (V)
VOUT (V)
4
NCP4641
TYPICAL CHARACTERISTICS
Chip Enable
16
12
8
0
IOUT = 20 mA
8
6
IOUT = 1 mA
4
IOUT = 150 mA
2
0
−2
0
50
100 150 200 250 300 350 400 450 500
t (ms)
Figure 31. Start−up, 8.0 V Version, VIN = 11.0 V
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11
VCE (V)
VOUT (V)
4
NCP4641
APPLICATION INFORMATION
connected to CE pin. Do not keep CE pin not connected or
between VCEH and VCEL voltage levels. Otherwise output
voltage would be unstable or indefinite and unexpected
would flow internally.
A typical application circuit for NCP4641 series is shown
in Figure 32.
NCP4641x
VIN
VIN
C1
100 n
CE
VOUT
VOUT
Thermal
As a power across the IC increase, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and also the ambient
temperature affect the rate of temperature increase for the
part. When the device has good thermal conductivity
through the PCB the junction temperature will be relatively
low in high power dissipation applications.
The IC includes internal thermal shutdown circuit that
stops operation of regulator, if junction temperature is
higher than 150°C. After that, when junction temperature
decreases below 125°C, the operation of voltage regulator
would restart. While high power dissipation condition is, the
regulator starts and stops repeatedly and protects itself
against overheating.
C2
100 n
GND
Figure 32. Typical Application Schematic
Input Decoupling Capacitor (C1)
The device is stable without any input capacitance, but if
input line is long and has high impedance or if more stable
operation is needed, input capacitor C1 should be connected
as close as possible to the IC. Recommended range of input
capacitor value is 100 nF to 10 mF.
Output Decoupling Capacitor (C2)
PCB Layout
The NCP4641 can work stable without output capacitor,
but if faster response and higher stability reserve is needed,
output capacitor should be connected as close as possible to
the device. Recommended range of output capacitance is
100 nF to 10 mF. Larger values of output capacitance and
lower ESR improves dynamic parameters.
Pins number 2 and 4 of SOT89−5 package and pins
number 2, 4 and 5 of SOIC6−TL must be wired to the GND
plane while it is mounted on board. Make VIN and GND
lines sufficient. If their impedance is high, noise pickup or
unstable operation may result. Connect capacitors C1 and
C2 as close as possible to the IC, and make wiring as short
as possible.
Enable Operation
The enable pin CE may be used for turning the regulator
on and off. The device is activated when high level is
ORDERING INFORMATION
Nominal Output
Voltage
Description
Marking
Package
Shipping†
NCP4641H030T1G
3.0 V
Enable High
M030
SOT89−5
(Pb−Free)
1000 / Tape & Reel
NCP4641H033T1G
3.3 V
Enable High
M033
SOT−89−5
(Pb−Free)
1000 / Tape & Reel
NCP4641H050T1G
5.0 V
Enable High
M050
SOT89−5
(Pb−Free)
1000 / Tape & Reel
NCP4641H080T1G
8.0 V
Enable High
M080
SOT89−5
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*To order other package and voltage variants, please contact your ON Semiconductor sales representative.
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12
NCP4641
PACKAGE DIMENSIONS
SOIC6 (HSOP6)
CASE 751BR
ISSUE A
b1
D
A
6
F
4
A3
E
H
1
L2
3
4X
0.12
B
D
L
b
M
C
SEATING
PLANE
DETAIL A
C A-B D
6X
0.10 C
A1
A
e
C
DETAIL A
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b AND b1 DO NOT INCLUDE DAMBAR
PROTRUSION. ALLOWAQBLE PROTRUSION SHALL
BE 0.10 mm IN EXCESS OF MAXIMUM MATERIAL
CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. DIMENSIONS D
AND E ARE DETERMINED AT DATUM F.
5. DATUMS A AND B ARE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
DIM
A
A1
A3
b
b1
D
E
e
H
L
L2
MILLIMETERS
MIN
MAX
1.45
1.85
0.05
0.25
0.15
0.30
0.30
0.50
1.57
1.77
4.72
5.32
3.70
4.10
3.81 BSC
5.70
6.30
0.40
0.80
0.25 BSC
3.81
PITCH
6X
1.05
6.40
1
2X
1.87
4X
0.60
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
NCP4641
PACKAGE DIMENSIONS
SOT−89, 5 LEAD
CASE 528AB
ISSUE O
D
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. LEAD THICKNESS INCLUDES LEAD FINISH.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
5. DIMENSIONS L, L2, L3, L4, L5, AND H ARE MEASURED AT DATUM PLANE C.
H
DIM
A
b
b1
c
D
D2
E
e
H
L
L2
L3
L4
L5
1
TOP VIEW
c
A
0.10 C
C
SIDE VIEW
e
b1
L
1
2
L2
L4
4X
0.57
1.75
3
L5
5
L3
RECOMMENDED
MOUNTING FOOTPRINT*
e
b
MILLIMETERS
MIN
MAX
1.40
1.60
0.32
0.52
0.37
0.57
0.30
0.50
4.40
4.60
1.40
1.80
2.40
2.60
1.40
1.60
4.25
4.45
1.10
1.50
0.80
1.20
0.95
1.35
0.65
1.05
0.20
0.60
2.79
1.50
0.45
4.65
4
D2
1.30
BOTTOM VIEW
1.65
1
2X
2X
0.62
1.50
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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