MX29F200C T/B 2M-BIT [256K x 8 / 128K x 16] SINGLE VOLTAGE 5V ONLY FLASH MEMORY FEATURES GENERAL FEATURES • Single Power Supply Operation - 4.5 to 5.5 volt for read, erase, and program operations • 262,144 x 8 / 131,072 x 16 switchable • Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • Sector Structure - 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1, and 64K-Byte x 3 • Sector protection - Hardware method to disable any combination of sectors from program or erase operations - Temporary sector unprotected allows code changes in previously locked sectors • Latch-up protected to 100mA from -1V to Vcc + 1V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE • High Performance - Access time: 70/90ns - Byte/Word program time: 9us/11us (typical) - Erase time: 0.7s/sector, 4s/chip (typical) • Low Power Consumption - Low active read current: 40mA (maximum) at 5MHz - Low standby current: 1uA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode PACKAGE • 44-Pin SOP • 48-Pin TSOP • All devices are RoHS Compliant P/N:PM1250 REV. 2.0, DEC. 04, 2012 1 MX29F200C T/B Contents FEATURES................................................................................................................................................................... 1 GENERAL FEATURES................................................................................................................................1 SOFTWARE FEATURES.............................................................................................................................1 HARDWARE FEATURES............................................................................................................................1 PACKAGE ...................................................................................................................................................1 PIN CONFIGURATIONS............................................................................................................................................... 5 44 SOP(500mil)............................................................................................................................................5 48 TSOP(TYPE I) (12mm x 20mm).............................................................................................................5 PIN DESCRIPTION....................................................................................................................................................... 6 LOGIC SYMBOL..........................................................................................................................................6 BLOCK DIAGRAM........................................................................................................................................................ 7 Table 1. SECTOR STRUCTURE.................................................................................................................................. 8 MX29F200CT Top Boot Sector Addresses Tables.......................................................................................8 MX29F200CB Bottom Boot Sector Addresses Tables.................................................................................8 Table 2. BUS OPERATION..........................................................................................................................9 REQUIREMENTS FOR READING ARRAY DATA.....................................................................................10 WRITE COMMANDS/COMMAND SEQUENCES......................................................................................10 RESET# OPERATION...............................................................................................................................10 SECTOR PROTECT OPERATION............................................................................................................ 11 CHIP UNPROTECT OPERATION............................................................................................................ 11 TEMPORARY SECTOR UNPROTECT OPERATION............................................................................... 11 AUTOMATIC SELECT OPERATION......................................................................................................... 11 VERIFY SECTOR PROTECT STATUS OPERATION................................................................................12 DATA PROTECTION..................................................................................................................................12 WRITE PULSE "GLITCH" PROTECTION.................................................................................................12 LOGICAL INHIBIT......................................................................................................................................12 POWER-UP SEQUENCE..........................................................................................................................12 POWER-UP WRITE INHIBIT.....................................................................................................................12 POWER SUPPLY DECOUPLING..............................................................................................................12 TABLE 3. MX29F200C T/B COMMAND DEFINITIONS............................................................................13 RESET ......................................................................................................................................................14 AUTOMATIC SELECT COMMAND SEQUENCE......................................................................................14 AUTOMATIC PROGRAMMING.................................................................................................................15 CHIP ERASE............................................................................................................................................16 SECTOR ERASE.......................................................................................................................................16 SECTOR ERASE SUSPEND.....................................................................................................................17 SECTOR ERASE RESUME.......................................................................................................................17 ABSOLUTE MAXIMUM STRESS RATINGS.............................................................................................................. 18 OPERATING TEMPERATURE AND VOLTAGE......................................................................................................... 18 DC CHARACTERISTICS ......................................................................................................................................... 19 SWITCHING TEST CIRCUITS.................................................................................................................................... 20 P/N:PM1250 REV. 2.0, DEC. 04, 2012 2 MX29F200C T/B SWITCHING TEST WAVEFORMS............................................................................................................................ 20 AC CHARACTERISTICS .......................................................................................................................................... 21 Figure 1. COMMAND WRITE OPERATION..............................................................................................22 READ/RESET OPERATION....................................................................................................................................... 23 Figure 2. READ TIMING WAVEFORMS....................................................................................................23 AC CHARACTERISTICS...........................................................................................................................24 Figure 3. RESET# TIMING WAVEFORM..................................................................................................24 ERASE/PROGRAM OPERATION.............................................................................................................................. 25 Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM.....................................................................25 Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART...........................................................26 Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM...............................................................27 Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART...................................................28 Figure 8. ERASE SUSPEND/RESUME FLOWCHART.............................................................................29 Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS......................................................................30 Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM.................................................................31 Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART...................................................32 SECTOR PROTECT/CHIP UNPROTECT.................................................................................................................. 33 Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)............................33 Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv........................................................34 Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv.....................................................35 Table 5. TEMPORARY SECTOR UNPROTECT........................................................................................36 Figure 14. TEMPORARY SECTOR UNPROTECT WAVEFORMS............................................................36 Figure 15. TEMPORARY SECTOR UNPROTECT FLOWCHART............................................................37 Figure 16. SILICON ID READ TIMING WAVEFORM.................................................................................38 WRITE OPERATION STATUS.................................................................................................................................... 39 Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS).................39 Figure 18. DATA# POLLING ALGORITHM................................................................................................40 Figure 19. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)......................41 Figure 20. TOGGLE BIT ALGORITHM ....................................................................................................42 RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 43 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 44 DATA RETENTION..................................................................................................................................................... 44 LATCH-UP CHARACTERISTICS............................................................................................................................... 44 TSOP AND SOP PIN CAPACITANCE........................................................................................................................ 44 ORDERING INFORMATION....................................................................................................................................... 45 PART NAME DESCRIPTION...................................................................................................................................... 46 PACKAGE INFORMATION......................................................................................................................................... 47 REVISION HISTORY .................................................................................................................................................. 49 P/N:PM1250 REV. 2.0, DEC. 04, 2012 3 MX29F200C T/B PIN CONFIGURATIONS NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX29F200C T/B 44 SOP(500mil) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC 48 TSOP(TYPE I) (12mm x 20mm) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29F200C T/B (NORMAL TYPE) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 P/N:PM1250 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX29F200C T/B (REVERSE TYPE) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC NC A7 A6 A5 A4 A3 A2 A1 REV. 2.0, DEC. 04, 2012 4 MX29F200C T/B PIN DESCRIPTION SYMBOL A0-A16 Q0-Q14 Q15/A-1 CE# OE# RESET# WE# RY/BY# BYTE# VCC GND NC LOGIC SYMBOL PIN NAME Address Input Data Input/Output Q15(Word mode)/LSB addr.(Byte mode) Chip Enable Input Output Enable Input Hardware Reset Pin, Active low Write Enable Input Read/Busy Output Word/Byte Selection Input Power Supply Pin (+5V) Ground Pin Pin Not Connected Internally 17 A0-A16 Q0-Q15 (A-1) 16 or 8 CE# OE# WE# RESET# BYTE# P/N:PM1250 RY/BY# REV. 2.0, DEC. 04, 2012 5 MX29F200C T/B BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# CONTROL INPUT LOGIC PROGRAM/ERASE STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER Y-DECODER AND STATE X-DECODER ADDRESS A0-AM WRITE FLASH REGISTER ARRAY ARRAY Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1250 REV. 2.0, DEC. 04, 2012 6 MX29F200C T/B Table 1. SECTOR STRUCTURE MX29F200CT Top Boot Sector Addresses Tables SA0 SA1 SA2 SA3 SA4 SA5 SA6 A16 A15 A14 A13 A12 0 0 1 1 1 1 1 0 1 0 1 1 1 1 X X X 0 1 1 1 X X X X 0 0 1 X X X X 0 1 X Address Range (in hexadecimal) Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range 64/32 00000h-0FFFFh 00000h-07FFFh 64/32 10000h-1FFFFh 08000h-0FFFFh 64/32 20000h-2FFFFh 10000h-17FFFh 32/16 30000h-37FFFh 18000h-1BFFFh 8/4 38000h-39FFFh 1C000h-1CFFFh 8/4 3A000h-3BFFFh 1D000h-1DFFFh 16/8 3C000h-3FFFFh 1E000h-1FFFFh MX29F200CB Bottom Boot Sector Addresses Tables SA0 SA1 SA2 SA3 SA4 SA5 SA6 A16 A15 A14 A13 A12 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 X X X 0 1 1 X X X X X 0 1 X X X X Address Range (in hexadecimal) Sector Size (Kbytes/Kwords) (x8)Address Range (x16) Address Range 16/8 00000h-03FFFh 00000h-01FFFh 8/4 04000h-05FFFh 02000h-02FFFh 8/4 06000h-07FFFh 03000h-03FFFh 32/16 08000h-0FFFFh 04000h-07FFFh 64/32 10000h-1FFFFh 08000h-0FFFFh 64/32 20000h-2FFFFh 10000h-17FFFh 64/32 30000h-3FFFFh 18000h-1FFFFh P/N:PM1250 REV. 2.0, DEC. 04, 2012 7 MX29F200C T/B Table 2. BUS OPERATION Pins Mode Read Silicon ID Manufacture Code Read Silicon ID Device Code Read Standby Output Disable Write Sector Protect Chip Unprotect Verify Sector Protect/Unprotect Reset CE# OE# WE# RESET# A0 A1 A6 A9 Q0 ~ Q15 L L H H L L X Vhv L L H H H L X Vhv L H L L L L L X L X H H H H L X H X H L L L H X H H H H Vhv Vhv H L A0 X X A0 L L L X A1 X X A1 H H H X A6 X X A6 L H L X A9 X X A9 X X Vhv X C2H (Byte mode) 00C2H (Word mode) 51H/57H (Byte mode) 2251H/2257H (Word mode) DOUT HIGH Z HIGH Z DIN DIN DIN Code(4) HIGH Z Notes: 1. Vhv is the very high voltage, 11.5V to 12.5V. 2. X means input high (Vih) or input low (Vil). 3. SA means sector address: A12~A16. 4. Code=00H/XX00H means unprotected. Code=01H/XX01H means protected. P/N:PM1250 REV. 2.0, DEC. 04, 2012 8 MX29F200C T/B REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array out. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of time no more than Treadyand the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. "Figure 1. COMMAND WRITE OPERATION" illustrates the AC timing waveform of a write command, and "TABLE 3. MX29F200C T/B COMMAND DEFINITIONS" defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory. P/N:PM1250 REV. 2.0, DEC. 04, 2012 9 MX29F200C T/B SECTOR PROTECT OPERATION When a sector is protected, program or erase operation will be disabled on these sectors. MX29F200C T/B provides one method for sector protection. Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details. This method is by applying Vhv on RESET# pin. Refer to "Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)" for timing diagram and "Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv" and "Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv" for the algorithm for this method. CHIP UNPROTECT OPERATION MX29F200C T/B provides one method for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector are unprotected when shipped from the factory. This method is by applying Vhv on RESET# pin. Refer to "Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)" for timing diagram and "Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv" and "Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv" for algorithm of the operation. TEMPORARY SECTOR UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. AUTOMATIC SELECT OPERATION When the device is in Read array mode or erase-suspended read array mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE# and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. P/N:PM1250 REV. 2.0, DEC. 04, 2012 10 MX29F200C T/B VERIFY SECTOR PROTECT STATUS OPERATION MX29F200C T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A16 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is still not being protected. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29F200C T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1250 REV. 2.0, DEC. 04, 2012 11 MX29F200C T/B TABLE 3. MX29F200C T/B COMMAND DEFINITIONS Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle Addr Data Addr Data Addr Data Addr 4th Bus Cycle Data 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Command 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle 5th Bus Cycle 6th Bus Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read Mode Reset Mode Addr Data XXX F0 Manufacturer ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 X00 X00 00C2 Program Word 555 AA 2AA 55 555 A0 Addr Data Byte AAA AA 555 55 AAA A0 Addr Data C2 Chip Erase Word 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Automatic Select Device ID Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 X01 X02 ID Sector Erase Byte AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Word 555 AA 2AA 55 555 80 555 AA 2AA 55 Sector 30 Byte AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30 ID Sector Protect Verify Word Byte 555 AAA AA AA 2AA 555 55 55 555 AAA 90 90 (Sector)X02 (Sector)X04 XX00/XX01 Erase Erase Suspend Resume Sector B0 Sector 30 00/01 Sector Protect Word XXX 60 sector 60 sector 40 sector 00/01 Byte XXX 60 sector 60 sector 40 sector 00/01 Notes: 1. Device ID: 2251H/51H for Top Boot Sector device. 2257H/57H for Bottom Boot Sector device. 2. For sector protect verify result, XX00H/00H means sector is not protected, XX01H/01H means sector has been protected. 3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc is for protect verify. 4. It is not allowed to adopt any other code which is not in the above command definition table. P/N:PM1250 REV. 2.0, DEC. 04, 2012 12 MX29F200C T/B RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode or sector protect verify mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID Device ID Sector Protect Verify Word Byte Word Byte Word Byte Address X00 X00 X01 X02 (Sector address) X 02 (Sector address) X 04 Data (Hex) 00C2 C2 2251/2257 51/57 00/01 00/01 Representation Top/Bottom Boot Sector Top/Bottom Boot Sector Unprotected/protected Unprotected/protected There is an alternative method to that shown in "Table 2. BUS OPERATION", which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1250 REV. 2.0, DEC. 04, 2012 13 MX29F200C T/B AUTOMATIC PROGRAMMING The MX29F200C T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the "TABLE 3. MX29F200C T/B COMMAND DEFINITIONS" (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. With the internal write state controller, the device requires the user to write the program command and data only. The typical chip program time at room temperature of the MX29F200C T/B is 1.5 seconds. (Word-Mode) When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress*1 Finished Exceed time limit Q7 Q7# Q7 Q7# Q6 Toggling Stop toggling Toggling Q5 0 0 1 RY/BY#*2 0 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us and the device returns to read array state without programing the data in the protected sector. P/N:PM1250 REV. 2.0, DEC. 04, 2012 14 MX29F200C T/B CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware rests or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress Finished Exceed time limit Q7 0 1 0 Q6 Toggling Stop toggling Toggling Q5 0 0 1 Q2 Toggling 1 Toggling RY/BY# 0 1 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Time-out period In progress Finished Exceed time limit Q7 0 0 1 0 Q6 Toggling Togging Stop toggling Toggling Q5 0 0 0 1 Q3 0 1 1 1 Q2 Toggling Toggling 1 Toggling RY/BY#*2 0 0 1 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us and the device returned to read array status without erasing the data in the protected sector. P/N:PM1250 REV. 2.0, DEC. 04, 2012 15 MX29F200C T/B SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1(≤20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Erase suspend read in erase suspended sector Erase suspend read in non-erase suspended sector Erase suspend program in non-erase suspended sector Q7 1 Data Q7# Q6 No toggle Data Toggle Q5 0 Data 0 Q3 N/A Data N/A Q2 RY/BY# Toggle 1 Data 1 N/A 0 When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1250 REV. 2.0, DEC. 04, 2012 16 MX29F200C T/B ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias Storage Temperature -65°C to +125°C -65°C to +150°C -0.5V to +7.0V VCC Voltage Range RESET#, A9 The other pins. -0.5V to +13.5V -0.5V to VCC+0.7V Output Short Circuit Current (less than one second) 200 mA Note: 1. Mininum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC+2V during transition and for less than 20ns during transitions. OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ) Industrial (I) Grade Surrounding Temperature VCC Supply Voltages VCC range (TA ) 0°C to +70°C -40°C to +85°C +4.5 V to 5.5 V P/N:PM1250 REV. 2.0, DEC. 04, 2012 17 MX29F200C T/B DC CHARACTERISTICS Symbol Iilk Iolk Icr1 Icr2 Description Input Leak Output Leak Read Current (10MHz) Read Current (5MHz) Isb1 Standby Current (TTL) Isb2 Standby current (CMOS) 1uA 5uA Icw Write Current 15mA 30mA Vil Vih Input Low Voltage -0.3V Input High Voltage 0.7xVCC Very High Voltage for hardware Protect/ 11.5V Unprotect/Auto Select/Temporary Unprotect Vhv Vol Voh1 Voh2 Min. Typ. Max. ± 1.0uA 10uA 50mA 40mA 1mA Output Low Voltage 2.4V Vcc-0.4V P/N:PM1250 CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih VCC=VCC max, CE#=Vih other pin disable VCC=VCC max, CE#=VCC +0.3V, other pin disable CE#=Vil, OE#=Vih, WE#=Vil 0.8V VCC+0.3V 12V 12.5V 0.45V Ouput High Voltage (TTL) Ouput High Voltage (CMOS) Remark Iol=2.1mA, VCC=VCC min Ioh1=-2mA Ioh2=-100uA REV. 2.0, DEC. 04, 2012 18 MX29F200C T/B SWITCHING TEST CIRCUITS Vcc 0.1uF R2 TESTED DEVICE CL R1 Vcc DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance, CL: 100PF for 90ns, 30PF for 70ns Rise/Fall Times : 10ns Input Pulse levels : 0.45/0.7xVCC Input/Output reference levels for measuring timing: 0.8V, 2.0V SWITCHING TEST WAVEFORMS 0.7xVCC 2.0V 2.0V TEST POINTS 0.45V 0.8V 0.8V INPUT OUTPUT P/N:PM1250 REV. 2.0, DEC. 04, 2012 19 MX29F200C T/B AC CHARACTERISTICS Symbol Description Taa Tce Toe Tdf Toh Trc Twc Tcwc Tas Tah Tds Tdh Tcs Tch Toes Tcep Tceph Twp Twph Tghwl Tbusy Tavt Tavt Taetc Taetb Tbal Valid data output after address Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high or CE# high Output hold time from the earliest rising edge of Addrss, CE#, OE# Read period time Write period time Command write period time Address setup time Address hold time Data setup time Data hold time CE# Setup time CE# hold time OE# setup time CE# pulse width CE# pulse width high WE# pulse width WE# pulse with high Read recover time before write Program/Erase active time by RY/BY# Program operation Byte Program operation Word Chip Erase Operation Sector Erase Operation Sector Address hold time P/N:PM1250 Speed Option -70/90 Min. Typ. Max. 70/90 70/90 30/35 20 Unit ns ns ns ns 0 ns 70/90 70/90 70/90 0 45 30/45 0 0 0 0 35/45 20 35 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us us sec sec us 9 11 4 0.7 90 300 360 32 8 50 REV. 2.0, DEC. 04, 2012 20 MX29F200C T/B Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twp Twph Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Data Vih Vil DIN VA: Valid Address P/N:PM1250 REV. 2.0, DEC. 04, 2012 21 MX29F200C T/B READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS CE# Tce Vih Vil Vih WE# OE# Vil Tdf Toe Vih Vil Toh Taa Trc Vih Addresses Outputs ADD Valid Vil Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1250 REV. 2.0, DEC. 04, 2012 22 MX29F200C T/B AC CHARACTERISTICS Item Trp1 Trp2 Trh Trb1 Trb2 Description RESET# Pulse Width (During Automatic Algorithms) RESET# Pulse Width (NOT During Automatic Algorithms) RESET# High Time Before Read RY/BY# Recovery Time (to CE#, OE# go low) RY/BY# Recovery Time (to WE# go low) RESET# PIN Low (During Automatic Algorithms) to Read or Tready1 Write RESET# PIN Low (NOT During Automatic Algorithms) to Read Tready2 or Write Setup MIN MIN MIN MIN MIN Speed 10 500 0 0 50 Unit us ns ns ns ns MAX 20 us MAX 500 ns Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1250 REV. 2.0, DEC. 04, 2012 23 MX29F200C T/B ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Taetc WE# Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address 2AAh VA SA Tds Data Read Status Tah Tas Tdh 55h VA In Progress Complete 10h Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1250 REV. 2.0, DEC. 04, 2012 24 MX29F200C T/B Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1250 REV. 2.0, DEC. 04, 2012 25 MX29F200C T/B Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Taetb WE# Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Data Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h Tbusy 30h Trb RY/BY# P/N:PM1250 REV. 2.0, DEC. 04, 2012 26 MX29F200C T/B Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1250 REV. 2.0, DEC. 04, 2012 27 MX29F200C T/B Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO Toggle Bit checking Q6 ERASE SUSPEND not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1250 REV. 2.0, DEC. 04, 2012 28 MX29F200C T/B Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch WE# Tavt Tcs Tghwl OE# Last 2 Program Command Cycle Address 555h VA PA Tds Data Last 2 Read Status Cycle Tah Tas VA Tdh A0h Status PD Tbusy DOUT Trb RY/BY# P/N:PM1250 REV. 2.0, DEC. 04, 2012 29 MX29F200C T/B Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Tavt or Taetb Tcp CE# Tcph Tghwl OE# Tah Tas Address 555h Tds Data VA PA VA Tdh A0h Status PD Tbusy DOUT Trb RY/BY# P/N:PM1250 REV. 2.0, DEC. 04, 2012 30 MX29F200C T/B Figure 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1250 REV. 2.0, DEC. 04, 2012 31 MX29F200C T/B SECTOR PROTECT/CHIP UNPROTECT Figure 12. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) 150us: Sector Protect 15ms: Chip Unprotect 1us CE# WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv RESET# Vih VA: valid address P/N:PM1250 REV. 2.0, DEC. 04, 2012 32 MX29F200C T/B Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No Retry Count=25? No Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1250 REV. 2.0, DEC. 04, 2012 33 MX29F200C T/B Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No Retry Count=1000? No Data=00h? Yes Device fail Yes Temporary Unprotect Write reset CMD Chip Unprotect Done P/N:PM1250 REV. 2.0, DEC. 04, 2012 34 MX29F200C T/B Table 5. TEMPORARY SECTOR UNPROTECT Parameter Trpvhh Tvhhwl Alt Description Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# Trsp RESET# Vhv to WE# Low Condition Speed MIN 500 MIN 4 Unit ns us Figure 14. TEMPORARY SECTOR UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# WE# Tvhhwl RY/BY# Vhv 12V RESET# 0 or 5V 0 or 5V Trpvhh Trpvhh P/N:PM1250 REV. 2.0, DEC. 04, 2012 35 MX29F200C T/B Figure 15. TEMPORARY SECTOR UNPROTECT FLOWCHART Start Apply RESET# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from RESET# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=11.5 ~ 12.5V. 2. The protected conditions of the protected sectors are the same to temporary sector unprotect mode. P/N:PM1250 REV. 2.0, DEC. 04, 2012 36 MX29F200C T/B Figure 16. SILICON ID READ TIMING WAVEFORM CE# Vih Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 A0 Vil Vih Vil Taa A1 Taa Vih Vil ADD DATA Q0-Q7 Vih Vil Vih Vil DATA OUT DATA OUT C2H 51H (TOP boot) 57H (Bottom boot) P/N:PM1250 REV. 2.0, DEC. 04, 2012 37 MX29F200C T/B WRITE OPERATION STATUS Figure 17. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Tdf Address VA VA Taa Toh Q7 Complement Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1250 REV. 2.0, DEC. 04, 2012 38 MX29F200C T/B Figure 18. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) Q7 = Data# ? No Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1250 REV. 2.0, DEC. 04, 2012 39 MX29F200C T/B Figure 19. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Tdf Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# Notes: 1. VA : Valid Address 2. CE# must be toggled when toggle bit toggling. P/N:PM1250 REV. 2.0, DEC. 04, 2012 40 MX29F200C T/B Figure 20. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice (Note1, 2) NO Q6 Toggle ? YES Program/Erase fail Write Reset CMD Program/Erase Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1250 REV. 2.0, DEC. 04, 2012 41 MX29F200C T/B RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in "Figure A. AC Timing at Device Power-Up" is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Vcc Vcc(min) GND Tvr Tf CE# WE# Tce Vil Vih Vil Tf OE# Tr Vil Taa Vih Tr or Tf Valid Address Vil Voh DATA Toe Vih Tr or Tf ADDRESS Tr Vih High Z Valid Ouput Vol Figure A. AC Timing at Device Power-Up Symbol Tvr Tr Tf Parameter Vcc Rise Time Input Signal Rise Time Input Signal Fall Time Min. 20 P/N:PM1250 Max. 500000 20 20 Unit us/V us/V us/V REV. 2.0, DEC. 04, 2012 42 MX29F200C T/B ERASE AND PROGRAMMING PERFORMANCE PARAMETER LIMITS TYP. 9 11 0.7 4 2.3 1.5 MIN. Byte Programming Time Word Programming Time Sector Erase Time Chip Erase Time Chip Programming Time Byte Mode Word Mode Erase/Program Cycles UNITS MAX. 300 360 8 32 6.8 4.5 us us sec sec sec sec Cycles 100,000 Note: 1. Typical condition means 25°C, 5V. 2. Maximum condition means 90°C, 4.5V, 100K cycles. DATA RETENTION PARAMETER Condition Min. Data retention 55˚C 20 Max. UNIT years LATCH-UP CHARACTERISTICS MIN. -1.0V -1.0V -100mA Input Voltage difference with GND on all pins except I/O pins Input Voltage difference with GND on all I/O pins Vcc Current Includes all pins except VCC. Test conditions: VCC = 5V, one pin per testing MAX. 13.5V VCC + 1.0V +100mA TSOP AND SOP PIN CAPACITANCE Parameter Symbol CIN2 COUT CIN Parameter Description Control Pin Capacitance Output Capacitance Input Capacitance Test Set VIN=0 VOUT=0 VIN=0 P/N:PM1250 TYP MAX 12 12 8 UNIT pF pF pF REV. 2.0, DEC. 04, 2012 43 MX29F200C T/B ORDERING INFORMATION MX29F200CTMI-70 MX29F200CTMI-90 ACCESS TIME (ns) 70 90 MX29F200CTTI-70 70 40 5 MX29F200CTTI-90 90 40 5 MX29F200CBMI-70 MX29F200CBMI-90 70 90 40 40 5 5 MX29F200CBTI-70 70 40 5 MX29F200CBTI-90 90 40 5 MX29F200CTMI-70G MX29F200CTMI-90G 70 90 40 40 5 5 MX29F200CTTI-70G 70 40 5 MX29F200CTTI-90G 90 40 5 MX29F200CBMI-70G MX29F200CBMI-90G 70 90 40 40 5 5 MX29F200CBTI-70G 70 40 5 MX29F200CBTI-90G 90 40 5 PART NO. OPERATING STANDBY Current MAX. (mA) Current MAX. (mA) 40 5 40 5 P/N:PM1250 PACKAGE Remark 44 Pin SOP 44 Pin SOP 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 44 Pin SOP 44 Pin SOP 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 44 Pin SOP 44 Pin SOP 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 44 Pin SOP 44 Pin SOP 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) REV. 2.0, DEC. 04, 2012 44 MX29F200C T/B PART NAME DESCRIPTION MX 29 F 200 C T T I 70 G OPTION: G: RoHS Compliant package blank: normal SPEED: 70:70ns 90: 90ns TEMPERATURE RANGE: I: Industrial (-40°C to 85°C) PACKAGE: M:SOP T: TSOP BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 200: 2M, x8/x16 Boot Sector TYPE: F: 5V DEVICE: 29: Flash P/N:PM1250 REV. 2.0, DEC. 04, 2012 45 MX29F200C T/B PACKAGE INFORMATION P/N:PM1250 REV. 2.0, DEC. 04, 2012 46 MX29F200C T/B P/N:PM1250 REV. 2.0, DEC. 04, 2012 47 MX29F200C T/B REVISION HISTORY Revision No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Description Page 1. Removed "Preliminary" title P1 2. Removed commercial grade All 3. Added access time: 55ns All 1. Removed access time : 55ns P1,18,19,22 P23,40,41 2. Removed sector protect/ chip unprotect without 12V P1,7,14,32~35 3. Added in-system sector protect/ chip unprotect P34~36 4. Added data# polling, toggle bit algorithm P27,28 5. Added RY/BY# timing waveform P25,29,31 1. Data Sheet Format changed All 1. Data modification All 1. Added statement P47 1. Added note 4 into "TABLE 3. MX29F200C T/B COMMAND DEFINITIONS"P10 1. Modified "Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM" P28 1. Modified "Figure 10. CE# CONTROLLED WRITE TIMING WAVEFORM" P28 (Changed "Twhwh1 or Twhwh2" into "Tavt or Taetb") 2. Modified Figure 12. DATA# POLLING TIMING WAVEFORM P36 1. Added note of Absolute Maximum Stress Ratings P15 2. Added Trc, Twp, Twph & Tghwl P18,22,24,27 P28 3. Added Icw P16 1. Added data retention table P41 2. Modified the sector erase time max from 15s to 8s P18,41 1. Modified description for RoHS compliance P1,44,45 2. Modified Output Load Capatitance P19 P/N:PM1250 Date DEC/14/2005 JUN/20/2006 AUG/15/2006 AUG/17/2006 NOV/06/2006 JAN/22/2008 FEB/21/2008 MAR/09/2009 MAY/25/2009 JUN/30/2009 DEC/04/2012 REV. 2.0, DEC. 04, 2012 48 MX29F200C T/B Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2005~2012. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 49