AND8277/D Ratings, Specifications and Waveforms for FACT Data Sheets http://onsemi.com APPLICATION NOTE Specifying FACT Devices Traditionally, when a semiconductor manufacturer completed a new device for introduction, specifications were based on the characterization of just a few parts. While these specifications were appealing to the designer, they were often too tight and, over time, the IC manufacturers had difficulty producing devices to the original specs. This forced the manufacturer to relax circuit specifications to reflect the actual performance of the device. As a result, designers were required to review system designs to ensure the system would remain reliable with the new specifications. Motorola realized and understood the problems associated with characterizing devices too aggressively. To provide more realistic and manufacturable specs, Motorola devised a systematic and thorough process to generate specifications. Devices are selected from multiple wafer lots to ensure process variations are taken into account. In addition, the process parameters are measured and compared to the known process limits. This method of characterizing parts more accurately represents the product across time, voltage, temperature and process rather than portraying the fastest possible device. FACT circuits are therefore guaranteed to be manufacturable over time without the need to respecify timing. These specification guidelines allow designers to design systems more efficiently since the devices used will behave as documented. Unspecified guardbands no longer need to be added by the designer to ensure system reliability. Gates — Switch one input. Bias the remaining inputs such that the output switches. Power Dissipation — Test Philosophy Load Capacitance — Each output which is switching should be loaded with the standard 50 pF. Latches — Switch the Enable and D inputs such that the latch toggles. Flip-Flops — Switch the clock pin while changing D (or bias J and K) such that the output(s) change each clock cycle. For parts with a common clock, exercise only one flip-flop. Decoders — Switch one address pin which changes two outputs. Multiplexers — Switch one address pin with the corresponding data inputs at opposite logic levels so that the output switches. Counters — Switch the clock pin with other inputs biased such that the device counts. Shift Registers — Switch the clock pin with other inputs biased such that the device counts. Transceivers — Switch one data input. For bidirectional devices enable only one direction. Parity Generator — Switch one input. Priority Encoders — Switch the lowest priority input. In an effort to reduce confusion about measuring CPD, a JEDEC standard test procedure (per JEDEC, Appendix E) has been adopted which specifies the test setup for each type of device. This allows a device to be exercised in a consistent manner for the purpose of specification comparison. All device measurements are made with VCC = 5 V at 25°C, with 3-state outputs both enabled and disabled. © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 0 If the device is tested at a high enough frequency, the static supply current can be ignored. Thus at 1 MHz, the following formula can be used to calculate CPD: CPD = ICC/(VCC) (1 × 106) − Equivalent Load Capacitance 1 Publication Order Number: AND8277/D AND8277/D Ratings and Specifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V Vin DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Source/Sink Current, per Pin ±50 mA ICC DC VCC or GND Current per Output Pin ±50 mA Tstg Storage Temperature −65 to +150 °C 1 Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. Motorola does not recommend operation of FACT circuits outside databook specifications. Figure 3-1. Absolute Maximum Ratings1 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Supply Voltage Vin, Vout DC Input Voltage, Output Voltage (Ref. to GND) tr, tf Input Rise and Fall Time (Note 1) ′AC Devices except Schmitt Inputs Min Typ Max ′AC 2.0 5.0 6.0 ′ACT 4.5 5.0 5.5 0 VCC VCC @ 3.0 V 150 VCC @ 4.5 V 40 VCC @ 5.5 V 25 VCC @ 4.5 V 10 VCC @ 5.5 V 8.0 Unit V V ns/V tr, tf Input Rise and Fall Time (Note 2) ′ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) TA Operating Ambient Temperature Range 85 °C IOH Output Current — High −24 mA IOL Output Current — Low 24 mA ns/V 140 −40 1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. Figure 3-2. Recommended Operating Conditions http://onsemi.com 2 25 °C AND8277/D DC CHARACTERISTICS for ’AC Family Devices Symbol Parameter VCC (V) 74AC 74AC TA = +25°C TA = −40°C to +85°C Typ VIH VIL VOH 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 5.5 ±0.1 ±1.0 μA VI = VCC, GND 5.5 75 mA VOLD = 1.65 V Max 5.5 −75 mA VOHD = 3.85 V Min 80 μA VIN = VCC or GND Maximum Low Level Output Voltage Maximum Input Leakage Current IOLD †Minimum Dynamic Output Current ICC Guaranteed Limits 3.0 4.5 5.5 IIN IOHD Conditions Minimum High Level Input Voltage 3.0 4.5 5.5 VOL Unit Maximum Quiescent Supply Current 3.0 4.5 5.5 0.002 0.001 0.001 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC. http://onsemi.com 3 IOUT = −50 μA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 μA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA AND8277/D DC CHARACTERISTICS for ’ACT Family Devices Symbol VIH VIL VOH VCC (V) Parameter 74ACT 74ACT TA = 25°C TA = −40°C to +85°C Typ Guaranteed Limits Conditions Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT = 0.1 V or VCC − 0.1 V Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT = 0.1 V or VCC − 0.1 V Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 3.86 4.86 3.76 4.76 0.1 0.1 0.1 0.1 4.5 5.5 0.36 0.36 0.44 0.44 V ±0.1 ±1.0 μA VI = VCC, GND 1.5 mA VI = VCC − 2.1V 4.5 5.5 VOL Unit 4.5 5.5 Maximum Low Level Output Voltage 0.001 0.001 V V V IOUT = −50 μA *VIN = VIL or VIH −24 mA IOH −24 mA IOUT = 50 μA *VIN = VIL or VIH 24 mA IOL 24 mA IIN Maximum Input Leakage Current 5.5 ΔICCT Additional Max. ICC/Input 5.5 IOLD †Minimum Dynamic Output Current 5.5 75 mA VOLD = 1.65 V Max 5.5 −75 mA VOHD = 3.85 V Min 80 μA VIN = VCC or GND IOHD ICC Maximum Quiescent Supply Current 0.6 5.5 8.0 * All outputs loaded; thresholds on input associated with output under test. † Maximum test duration 2.0 ms, one output loaded at a time. 500 Ω DUT TEST LOAD OPEN 2 × VCC 50 pF tPZH tPHZ tPZL tPLZ 450 Ω tr = 3 ns tf = 3 ns 50 Ω SCOPE Figure 3-3. AC Tri-State Loading Circuit AC Loading and Waveforms Loading Circuit Figure 3-3 shows the AC loading circuit used in characterizing and specifying propagation delays of all FACT devices (’AC and ’ACT) unless otherwise specified in the data sheet of a specific device. The use of this load, differs somewhat from previous (HCMOS) practice, provides more meaningful information and minimizes problems of instrumentation and customer correlation. In the past, +25°C propagation delays for TTL devices were specified with a load of 15 pF to ground; this required great care in building test jigs to minimize stray capacitance and implied the use of high impedance, high frequency scope probes. FAST circuits changed to 50 pF of capacitance allowing more leeway in stray capacitance and also loading the device during rising or falling output transitions. This more closely resembles the inloading to be expected in average applications and thus gives the designer more useful delay figures. We have incorporated this scheme into the FACT product line. The net effect of the change in AC load is to increase the average observed propagation delay by about 1 ns. The 500 ohm resistor to ground can be a high frequency passive probe for a sampling oscilloscope, which costs much less than the equivalent high impedance probe. Alternately, the 500 ohm resistor to ground can simply be a 450 ohm resistor feeding into a 50 ohm coaxial cable leading to a sampling scope input connector, with the internal 50 ohm termination of the scope completing the path to ground. This http://onsemi.com 4 AND8277/D is the preferred scheme for correlation. (See Figure 3-3.) With this scheme there should be a matching cable from the device input pin to the other input of the sampling scope; this also serves as a 50 ohm termination for the pulse generator that supplies the input signal. Shown in Figure 3-3 is a second 500 ohm resistor from the device output to a switch. For most measurements this switch is open; it is closed for measuring one set of the Enable/Disable parameters (LOW-to-OFF and OFF-to-LOW) of a 3-state output. With the switch closed, the pair of 500 ohm resistors and the 2 × VCC supply voltage establish a quiescent HIGH level. ’ACxx Devices VCC VCC − 0.1 V 70% VCC 30% VCC 0.1 V 0V AC TEST INPUT LEVELS ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, DC LOW INPUT RANGE LOW LEVEL NOISE IMMUNITY DC HIGH INPUT RANGE HIGH LEVEL NOISE IMMUNITY TRANSITION REGION Figure 3-4a. Test Input Signal Levels ’ACTxx Devices VCC VCC − 0.1 V 3V 2V 0.8 V 0.1 V 0V AC TEST INPUT LEVELS ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, ,,,,, DC LOW INPUT RANGE LOW LEVEL NOISE IMMUNITY DC HIGH INPUT RANGE Figure 3-4b. Test Input Signal Levels http://onsemi.com 5 HIGH LEVEL NOISE IMMUNITY TRANSITION REGION AND8277/D Test Conditions Figures 3-4a and 3-4b describe the input signal voltage levels to be used when testing FACT circuits. The AC test conditions follow industry convention requiring VIN to range from 0 V for a logic LOW to 3 V for a logic HIGH for ’ACT devices and 0 V to VCC for ’AC devices. The DC parameters are normally tested with VIN at guaranteed input levels, that is VIH to VIL (see data tables for details). Care must be taken to adequately decouple these high performance parts and to protect the test signals from electrical noise. In an electrically noisy environment, (e.g., a tester and handler not specifically designed for high speed work), DC input levels may need to be adjusted to increase the noise margin to allow for the extra noise in the tester which would not be seen in a system. Noise immunity testing is performed by raising VIN to the nominal supply voltage of 5 V then dropping to a level corresponding to VIH characteristics, and then raising again to the 5 V level. Noise tests can also be performed on the VIL characteristics by raising VIN from 0 V to VIL, then returning to 0 V. Both VIH and VIL noise immunity tests should not induce a switch condition on the appropriate outputs of the FACT device. Good high frequency wiring practices should be used in constructing test jigs. Leads on the load capacitor should be as short as possible to minimize ripples on the output wave form transitions and to minimize undershoot. Generous ground metal (preferably a ground plane) should be used for the same reasons. A VCC bypass capacitor should be provided at the test socket, also with minimum lead lengths. It is important to understand why this oscillation occurs. Consider the outputs, where the problem is initiated. Usually, CMOS outputs drive capacitive loads with low DC leakage. When the output changes from a HIGH level to a LOW level, or from a LOW level to a HIGH level, this capacitance has to be charged or discharged. With the present high performance technologies, this charging or discharging takes place in a very short time, typically 2−3 ns. The requirement to charge or discharge the capacitive loads quickly creates a condition where the instantaneous current change through the output structure is quite high. A voltage is generated across the VCC or ground leads inside the package due to the inductance of these leads. The internal ground of the chip will change in reference to the outside world because of this induced voltage. Consider the input. If the internal ground changes, the input voltage level appears to change to the DUT. If the input rise time is slow enough, its level might still be in the device threshold region, or very close to it, when the output switches. If the internally-induced voltage is large enough, it is possible to shift the threshold region enough so that it re-crosses the input level. If the gain of the device is sufficient and the input rise or fall time is slow enough, then the device may go into oscillation. As device propagation delays become shorter, the inputs will have less time to rise or fall through the threshold region. As device gains increase, the outputs will swing more, creating more induced voltage. Instantaneous current change will be greater as outputs become quicker, generating more induced voltage. Package-related causes of output oscillation are not entirely to blame for problems with input rise and fall time measurements. All testers have VCC and ground leads with a finite inductance. This inductance needs to be added to the inductance in the package to determine the overall voltage which will be induced when the outputs change. As the reference for the input signals moves further away from the pin under test, the test will be more susceptible to problems caused by the inductance of the leads and stray noise. Any noise on the input signal will also cause problems. With FACT logic having gains as high as 100, it merely takes a 50 mV change in the input to generate a full 5 V swing on the output. Rise and Fall Times Input signals should have rise and fall times of 3 ns and signal swing of 0 V to 3.0 V VCC for ’ACT devices or 0 V to VCC for ’AC devices. Rise and fall times less than or equal to 1 ns should be used for testing fmax or pulse widths. CMOS devices, including 4000 Series CMOS, HC, HCT and FACT families, tend to oscillate when the input rise and fall times become lengthy. As a direct result of its increased performance, FACT devices can be more sensitive to slow input rise and fall times than other lower performance technologies. tw DATA IN Vmi tpxx CONTROL IN tpxx DATA OUT Vmi trec Vmo Vmi CLOCK tPHL tPLH OUTPUT Figure 3-5. Waveform for Inverting and Non-Inverting Functions Vm Vmo Figure 3-6. Propagational Delay, Pulse Width and trec Waveforms * Vmi = 50% VCC for ’AC devices; 1.5 V for ’ACT devices Vmo = 50% for ’AC/’ACT devices http://onsemi.com 6 AND8277/D Enable and Disable Times Figures 3-8 and 3-9 show that the disable times are measured at the point where the output voltage has risen or fallen by 10% from the voltage rail level (i.e., ground for tPLZ or VCC for tPHZ). This change enhances the repeatability of measurements, reduces test times, and gives the system designer more realistic delay times to use in calculating minimum cycle times. Since the high impedance state rising or falling waveform is RC-controlled, the first 10% of change is more linear and is less susceptible to external influences. More importantly, perhaps from the system designer’s point of view, a change in voltage of 10% is adequate to ensure that a device output has turned OFF. Measuring to a larger change in voltage merely exaggerates the apparent Disable time and thus penalizes system performance since the designer must use the Enable and Disable times to devise worst case timing signals to ensure that the output of one device is disabled before that of another device is enabled. DATA IN Vmi ts th CONTROL (CLOCK) INPUT Vmi trec MR OR CLEAR Vmi Figure 3-7. Setup Time, Hold Time and Recovery Time OUTPUT CONTROL Propagation Delay, fmax, Set, Hold, and Recovery Times Vmi tPHZ tPZH A 1 MHz square wave is recommended for most propagation delay tests. The repetition rate must necessarily be increased for testing fmax. A 50% duty cycle should always be used when testing fmax. Two pulse generators are usually required for testing such parameters as setup time (ts), hold time (th), recovery time (tREC) shown in Figure 9. VCC 90% VCC Vmo DATA OUT Figure 3-8. 3-State Output High Enable and Disable Times Electrostatic Discharge OUTPUT CONTROL Precautions should be taken to prevent damage to devices by electrostatic discharge. Static charge tends to accumulate on insulated surfaces such as synthetic fabrics or carpeting, plastic sheets, trays, foam, tubes or bags, and on ungrounded electrical tools or appliances. The problem is much worse in a dry atmosphere. In general, it is recommended that individuals take the precaution of touching a known ground before handling devices. To effectively avoid electrostatic damage to FACT devices, it is recommended that individuals wear a grounded wrist strap when handling devices. More often, handling equipment, which is not properly grounded, causes damage to parts. Ensure that all plastic parts of the tester, which are near the device, are conductive and connected to ground. Vmi tPZL DATA OUT Vmo tPLZ 10% VCC GND Figure 3-9. 3-State Output Low Enable and Disable Times *Vmi = 50% VCC for ’AC devices; 1.5 V for ’ACT devices Vmo = 50% VCC for ’AC/’ACT devices ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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