AND8029/D Ramp Compensation for the NCP1200 Prepared by: Christophe Basso ON Semiconductor http://onsemi.com APPLICATION NOTE INTRODUCTION Lowering the Peaking A current mode controlled SMPS exhibits one low frequency pole, ωp, and two poles which are located at Fswitching/2. These poles move in relation to the duty cycle and the external compensation ramp, when present. The two high frequency poles present a Q that depends on the compensating ramp and the duty–cycle. Ridley demonstrated that the Q becomes infinite at D = 0.5 with no external ramp (mc = 1), confirming the inherent instability of a CCM current–mode SMPS operating at a duty cycle greater than 0.5. Below stands the definition of this quality coefficient: As any current–mode controllers, the NCP1200 can be subject to subharmonic oscillations. Oscillations take place when the Switch–Mode Power Supply (SMPS) operates in Continuous Conduction Mode (CCM) together with a duty–cycle near or greater than 50%. For Discontinuous Conduction Mode (DCM) designs, this normally does not happen. However, at the lowest line levels and when the SMPS is pushed to its upper output power capability, CCM can engender these oscillations within the current loop. This application note details how to properly cure this problem by injecting the correct amount of ramp compensation. Q Origin of the Problem A current–mode power supply is a two–loop system: one loop controls the inductor peak current while the other monitors the output voltage. The current loop is actually embedded into the voltage loop which fixes the final current setpoint. In CCM operation, the action of the current loop can be compared to a sample and hold device. This sampling action creates a pair of RHP zeroes in the current loop which are responsible for the boost in gain at Fswitching/2 but also stress the phase lag at this point. If the gain margin is too low at this frequency, any perturbation in the current will make the system unstable since, as we said, both voltage and current loops are embedded. You can fight the problem by providing the converter with an external compensation ramp. This ramp will oppose the duty cycle action by lowering the current–loop DC gain, correspondingly increasing the phase margin at Fswitching/2, finally damping the high Q poles in the Vout/Vcontrol transfer function. As other benefits of ramp compensation, Ray Ridley [1] confirmed that an external ramp whose slope is equal to 50% (mc = 1.5) of the inductor downslope could nullify the audio susceptibility in a BUCK converter, as already calculated by Holland [2]. As more external ramp is added, the low frequency pole ωp moves to higher frequencies while the double poles will be split into two distinct poles. The first one will move towards lower frequencies until it joins and combines with the first low frequency pole at ωp. At this point, the converter behaves as if it is operating in voltage mode. Semiconductor Components Industries, LLC, 2001 March, 2001 – Rev. 1 1 where mc = 1 + Se/Sn. Se is the · (mc · D 0.5) external ramp slope, Sn is the inductor on–time slope and D′= 1 – D. For designers, once the system’s Q has been determined, they should look for the amount of ramp compensation that 1 0.5 . 1 . will make this number equal to 1: mc D How to Create a Ramp? On the NCP1200, you do not have access to any oscillator sawtooth. However, you can easily charge a capacitor when the gate drive is high, and immediately discharge it when the MOSFET switches off. Figure 1a shows how to simply generate a sawtooth from the gate drive: DRV 2 R D 3 Radd1 CS 1 Rsense C Radd2 150 Figure 1a A very simple way to generate a ramp from a square wave signal. 1 Publication Order Number: AND8029/D AND8029/D 250 µA. With a gate plateau of 11 V, this leads to a resistor of ≈11 V/250 µA = 44 kΩ. With a charging current of 250 µA, what capacitor do we need to generate a ramp that reaches Calculating the RC component values is a rather easy task. By drawing the smallest current from the drive to avoid increasing the standby power, R shall be of high value. If this is the case, you can consider this system as a current generator. By applying Vc · C i · t , you calculate R and C. Suppose we want to create a ramp that goes up to 5.0 V when a 60 kHz NCP1200 is operating at 50% duty–cycle. The ON time is therefore 5.0 V in 8.33 µs? Well, C 250 · 8.33 416 pF. 5 However, because the charging current varies during the ramping (we actually obtain an exponential), we will to reduce both elements to their next lower normalized values, e.g., 39 kΩ and 390 pF. If we feed our SPICE simulator with these values, Figure 1b and 1c confirms the calculations: 1 8.3 s . In order to not bothering 2 · 60 k the NCP1200 operation, let’s select a charging current of 4.50 3.50 Vdrive 2.50 1.50 500M 2 R1 39k + Vdrv 1 D1 1N4148 Vramp C1 390pF Vramp 14.0 10.0 6.00 2.00 –2.00 10.0U Figure 1b 30.0U 50.0U 70.0U 90.0U Figure 1c A simple simulation schematic confirms the calculations: the capacitor voltage ramps up from a few hundred of mV up to nearly 5.0 V. By ramping from 0.6 V to 4.5 V in 8.3 µs, we have created a signal exhibiting a slope of 468 mV/µs. The external ramp injection will keep Q below 1. To adhere to this requirement, we must inject a compensating “What compensation level shall I inject?” 1 0.5 . 1 1.9. By applying mc ramp mc equal to D definition, we can deduct the final amount of external ramp Let’s suppose the following specs for our FLYBACK converter: we must inject: mc 1 Se or Se (mc 1) · Sn. In a Sn VHVDC = 110 V Fsw = 60 kHz Lp = 1.8 mH η = 80% N = Np:Ns = 0.1 Poutmax = 15 W FLYBACK, the ON slope Sn is given by the rectified DC rail applied over the primary inductance Lp: Sn VHVDC. Lp With Lp = 1.8 mH, Rsense = 1.5 Ω and the lowest main equals 110 V, then Sn = 91.5 mV/µs once reflected in volts over Rsense. To get the final level of ramp compensation, let’s compute Se by: Se (mc 1) · Sn or 82 mVs . To obtain this ramp from our ramping generator, we must create a division ratio of 0.082/468 or 175 m. If we select a 10 kΩ resistor to convey the current sense information, then the To calculate the operating duty–cycle D, we need to compute the peak current authorizing a 15 W output power flow from the 1.8 mH primary inductance: Pin 1 · Lp · Ip? · Fsw. From our specs, we know that 2 ramp resistor is calculated using: 10 k 0.175 · 10 k or Pin = 15/08 = 18.8 W. At the boundary between DCM and CCM, the peak current is evaluated to: Ip 0.175 47 k in this example. 590 mA. To reach this value, we need to Lp2 ·· Pin Fsw Simulation of the Converter To check our calculation, we can use the NCP1200 SPICE model. Figure 2a portrays the application schematic for this converter with INTUSOFT’s IsSpice4 model version: Lp apply VHVDC over Lp during: Ip · 9.6 s. VHVDC Compared to a 60 kHz switching frequency, it corresponds to a 58% duty–cycle or D = 0.58. http://onsemi.com 2 AND8029/D R3 200 m 6 Clp 10 nF Iprim Vclamp + Istartup + Vinput 110 Vadj 11 18 Rclp 22 k 16 1 2 3 4 Lp 1.8 mH VCC Rconv 10 k D2 1N4148 20 32 C2 220 µF IC = 13.5 C1 220 µF IC = 13.5 R15 470 13 R5 100 m 19 X4 MOC8101 14 Vsense 15 Vramp C6 390 pF Vout + 17 R17 300 m R4 100 m Iripple1 Vdrain Idrain 10 X6 MTP6N60m 21 Rcomp 1 Meg Vsum 31 9 L5 30 µH + NCP1200 R9 39 k Isec 12 Drv 5 7 4 R16 10 m 1 Iclamp 8 7 6 5 Vsec D4 1Nxxxxx L1 BV = 60 10 µH + 28 8 D3 MUR160 X2 NCP1200 Fs = 60 k Iout X1 XFMR RATIO = –0.1 23 CVCC 22 µF IC = 12.1 Rsense 1.5 D1 1N964 VFB C3 10 n Figure 2a The current–mode SMPS built with the NCP1200 SPICE model. http://onsemi.com 3 Rload 12 AND8029/D The system enters CCM for a load of 12 Ω and subharmonic oscillations take place, as shown by Figure 2b. Measurements on the board confirm the presence of these unwanted oscillations (Figure 2c). Rcomp was kept to a high value to suppress any compensating action. 700M 500M 300M 100M Primary Current 100M – 350 Drain Voltage 250 150 50.0 –50.0 1.020M 1.030M 1.040M 1.050M 1.060M Figure 2b Figure 2c Oscillations take place when entering CCM with a duty–cycle greater than 50% as confirmed by both models and measurements. Let’s now diminish Rcomp to 47 kΩ as previously calculated and run a new simulation. Results are depicted by Figure 2d and confirmed by Figure 2e: 700M 500M 300M 100M –100M 1.01M 350 1.03M Primary Current 1.05M 1.07M 1.09M Drain Voltage 250 150 50.0 –50.0 1.01M 1.03M 1.05M 1.07M 1.09M Figure 2d Figure 2e The right amount of ramp compensation stabilizes the converter (2d simulated, 2c measured). http://onsemi.com 4 AND8029/D the NCP1200 pins shall be kept as short as possible to avoid undesirable peaking. In case of troubles, the solutions consists in lowering the ramp generator’s output impedance and re–iterating the other elements. The previous default has disappeared and the converter is stabilized. However, the designer shall keep in mind that injecting a compensation ramp diminishes the current loop gain. This has the same effect as raising Rsense on the small–signal point of view. As a result, the controller grows its operating feedback voltage VFB (that sets Ip) to impose the same peak current. If before compensation VFB was already close to the maximum limit, the ramp injection will make it raise and the possibility exists that the NCP1200 goes into short–circuit protection (VFB ≈ 4.1 V). We deliberately selected a rather high value for the ramp generator resistor in order to not load the NCP1200 (otherwise the standby power can be degraded). As a consequence, the summing resistor Rcomp cannot be too low to prevent from disturbing the ramp generator. In a noisy environment, the electrical paths conveying these signals to References 1. R. B. RIDLEY, “A new small–signal model for current–mode control’’, PhD. dissertation, Virginia Polytechnic Institute and State University, 1990 (e–mail : [email protected]). This document can also be ordered from Ray Ridley’s homepage: http://www.ridleyengineering.com/index.html 2. HOLLAND, “Modelling, Analysis and Compensation of the Current Mode Converter”, Powercon 11, 1984 Record, Paper H–2. http://onsemi.com 5 AND8029/D Notes http://onsemi.com 6 AND8029/D Notes http://onsemi.com 7 AND8029/D ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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