T R I Q U I N T S E M I C O N D U C T O R, I N C . TQ8025 DIØ–15 (differential) PECL/CML Input Buffers PRELIMINARY DATA SHEET 32 16 x 16 Crosspoint Switch Matrix PECL/CML Output Buffers DOØ–15 (differential) 16 x 4 RESET– LDMODE CONFIG ADD15 Configuration Latches READY 4-Bit Shift Register +5V GND 4-Bit Shift Register ADDØ LOAD CLOCK ADDREN AUTOCONFIG Address Generator and Control RADDØ RADD1 TQ8025 2.5 Gigabit/sec 16x16 Digital Crosspoint Switch SWITCHING PRODUCTS 32 Features • 16 PECL/CML fully differential (back-terminated) outputs • >2.5 Gb/s data bandwidth per channel • >40 Gb/s aggregate bandwidth The TQ8025 is a non-blocking 16 x 16 digital crosspoint switch capable of data rates greater than 2.5 gigabits per second per port. With a fully differential internal data path and PECL/CML I/O, the TQ8025 offers an extremely high data rate with exceptional signal fidelity. The use of fully differential logic results in low crosstalk, jitter, and signal skew. The TQ8025 is ideally suited for digital video, data communications, telecommunication switching, and cross-connect applications. The non-blocking architecture uses 16 fully independent 16:1 multiplexers which allow each output port to be independently programmed to any input port. The TQ8025 offers two programming options: a flexible port-by-port option, and a fast configuration option. Using the fast configuration option, all 16 switch ports are programmed within 80ns by serially loading four 16-bit input port selection words. Two output pins (RADD0,1) are provided to drive an external RAM (n x 4 x 16 bits) used to store the switch configuration. An Autoconfigure option automatically transfers the new configurations into the switch core. Autoconfiguration occurs after the last input selection word is clocked into the programming registers. • Non-blocking architecture • 80 ns configuration time • Autonomous control of external RAM for configuration data • Low jitter and signal skew • ±100 ps delay match (one input to all outputs) • Fully differential data path • 132-pin MLC package with heat spreader Applications • SONET OC-48 data path • Double-speed Fibre Channel • Hubs and routers • High-definition video switching • Parallel processing Data integrity is maintained on all unchanged data paths for both the portby-port and fast configuration options. For additional information and latest specifications, see our website: www.triquint.com 1 TQ8025 PRELIMINARY DATA SHEET Specifications Table 1. Absolute Maximum Ratings 4 Storage temperature Junction temperature Case temperature with bias 1 Supply voltage 2 Voltage to any input 2 Voltage to any output 2 Current to any input 2 Current from any output 2 Power dissipation of output 3 –65 °C to +150 °C TSTORE TCH 150 °C TC VCC TJ = 150 °C 0 V to +7.0 V VIN –0.5 V to VCC + 0.5 V VOUT IIN –0.5 V to VCC + 0.5 V –1.0 mA to +1.0 mA IOUT 40 mA POUT 50 mW Notes: 1. TC is measured at the case top. 2. All voltages are measeured with respect to GND 0V and are continuous. 3. POUT = (VCC – VOUT) x IOUT. 4. Absolute maximum ratings in this table are those beyond which the device's performance may be impaired and/or permanent damage may occur. Table 2. Recommended Operating Conditions 4 Symbol Min Typ Max Units Notes 1, 3 TC Case Operating Temperature 0 — 85 °C VCC Supply Voltage 4.75 — 5.25 V VTT Load Termination Supply Voltage ICC Current Positive Supply 2.1 A RLOAD Output Termination Load Resistance ΘJC Thermal Resistance Channel to Case 4.5 °C/W Notes: 1. 2. 3. 4. 2 Parameter VCC – 2.0 — — V Ω 50 TC measured at case top. Use of adequate heatsink is required. The VTT and RLOAD combination is subject to maximum output current and power restrictions. Contact the Factory for extended temperature range applications. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed, singularly or in combination, the operating range specified. For additional information and latest specifications, see our website: www.triquint.com 2 2 TQ8025 PRELIMINARY DATA SHEET Table 3. DC Characteristics — CML I/O 5 Description Test Conditions Min Nom VCOM Common mode voltage VDIFF Differential voltage VIH VIL Input HIGH voltage Input LOW voltage (Note 2) VOH Output HIGH voltage (Note 3) VOL IOH Output LOW voltage Output HIGH current (Note 3) (Note 3, 4) IOL Output LOW current (Note 3, 4) Max Unit (Note 1) VCC – 600 — VCC mV (Note 1) 400 — 1200 mV VCC VCC – 1100 — — mV mV VCC – 100 — VCC mV VCC – 1100 20 — 23 VCC – 600 30 mV mA 0 5 8 mA Min Nom Max Unit VCC – 1500 400 — — VCC – 1100 1200 mV mV — VCC – 500 mV — — VCC – 600 mV mV — 23 VCC – 1600 30 mV mA SWITCHING PRODUCTS Symbol Table 4. DC Characteristics — PECL I/O 5 Symbol Description Test Conditions VCOM VDIFF Common mode voltage Differential voltage (Note 1) (Note 1) VIH Input HIGH voltage (Note 2) VIL VOH Input LOW voltage Output HIGH voltage (Note 3) VCC – 2100 VCC – 1100 VOL IOH Output LOW voltage Output HIGH current (Note 3) (Note 4) VCC – 2100 20 IOL Output LOW current (Note 4) CIN COUT Input capacitance Output capacitance VESD ESD breakdown rating (Note 5) 0 5 8 mA — — — — TBD TBD pF pF Class I — — Min Nom Max Table 5. DC Characteristics — TTL I/O 5 Symbol Description VIH Input HIGH voltage 2.0 — VCC V VIL Input LOW voltage 0 — 0.8 V IIH IIL Input HIGH current Input LOW current V(IHMAX) V(ILMIN) — –400 — –200 200 — uA uA VOH Output HIGH voltage IOH = 50 mA 2.4 — VCC V VOL CIN Output LOW voltage Input capacitance IOH = –20 mA 0 — — — 0.4 TBD V pF COUT Output capacitance — — TBD pF VESD ESD breakdown rating Class I — — Notes (Tables 3, 4, and 5): Test Conditions 1. 2. 3. 4. 5. (Note 5) Unit Differential inputs. VREF = 1300 mV. RLOAD = 50 ohms to VTT = VCC – 2.0 V. Not tested; consistent with VOH and VOL tests. Specifications apply over recommended operating ranges. For additional information and latest specifications, see our website: www.triquint.com 3 TQ8025 PRELIMINARY DATA SHEET Table 6. AC Characteristics Symbol Description TPW TR/F Test Conditions Min Typ Max Unit D(0:15) minimum pulse width (Note 1) 360 O(0:15) rise/fall time 20-80% (Note 1) — — — ps — 150 TPD TSKEW D(0:15), O(0:15) delay time Path delay matching (Note 1) (Note 1) ps — — 300 2.5 ns ps TJITTER Jitter (Note 2) — 50 — ps pk–pk Notes: 1. Minimum VOH to maximum VOL levels. 2. Crossing of (On)—(NOn) measured with 223 – 1 PRBS, measured over extended time. Table 7. TQ8025 Timing — Normal Configure Mode 1 Symbol Parameter Min. Max. Units T1 Hold LOAD low to SAD0:3, DAD0:3 2 ns T2 Setup DAD0:3 to LOAD high 0 ns T3 T4 CONFIGURE pulse low time Setup LOAD low to CONFIGURE low 10 3 ns ns T5 CONFIGURE low to SIGNAL PATHS updated T6 LOAD pulse width high 4 ns TBD ns Notes: 1. LDMODE = 0; AUTOCONFIG = Don't Care, RESET– = 1, CLOCK = Don't Care. Figure 1. TQ8025 Timing —␣ Normal Configure Mode DAD0:3 DEST ADDR 1 DEST ADDR 2 T1 SAD0:3 T1 SRCE ADDR 1 SRCE ADDR 2 T6 T2 LOAD T4 T3 CONFIGURE T5 SIGNAL PATHS OLD CONFIGURATION LDMODE=0; AUTOCONFIG = Don't Care, RESET– = 1, CLOCK = Don't Care. 4 For additional information and latest specifications, see our website: www.triquint.com NEW CONFIGURATION TQ8025 PRELIMINARY DATA SHEET Table 8. TQ8025 Timing — RAM Loading, Auto-Configure Mode 1 Parameter Min. Max. Units T1 LOAD high to READY low 3 ns T2 CLOCK low to READY high 3 ns T3 T4 ADDREN low to RADD enabled Setup LOAD high to CLOCK high 3 4 ns ns T5 CLOCK low to RADD increment 2 ns T6 T7 AD0:15 setup before CLOCK low AD0:15 hold time after CLOCK low 0 2 ns ns T8 CLOCK low to INT CONFIGURE high 2 ns T9 T10 CONFIGURE low pulse width ADDREN high to RADD tristate 10 3 ns ns T11 LOAD low prior to 3rd CLOCK low T12 T13 LOAD high pulse CLOCK low to SIGNAL PATHS updated T14 CLOCK period T15 LOAD high to INT CONFIGURE low 4 ns TBD 4 ns ns 20 ns TBD ns SWITCHING PRODUCTS Symbol Notes: 1. LDMODE = 1; AUTOCONFIG = 1, RESET– = 1, CONFIG = 1. Figure 2. TQ8025 Timing —␣ RAM Loading, Auto-Configure Mode T14 CLOCK T4 T12 T11 LOAD ADDREN T10 T5 T3 RADD0:1 READY 0 1 2 3 0 T1 T6 D0 AD0:15 T1 T2 T7 D1 D2 D3 T15 T15 T8 T9 INT CONFIGURE T13 SIGNAL PATHS OLD CONFIGURATION NEW CONFIGURATION LDMODE = 1; AUTOCONFIG = 0, RESET– = 1. Note: INT CONFIGURE is an internal signal shown for clarity of operation. For additional information and latest specifications, see our website: www.triquint.com 5 TQ8025 PRELIMINARY DATA SHEET Table 9. TQ8025 Timing — RAM Loading, External Configure Pulse Mode 1 Symbol Parameter Min. Max. Units T1 LOAD high to READY low 3 T2 CLOCK low to READY high 3 ns ns T3 T4 ADDREN low to RADD enabled Setup LOAD high to CLOCK high 3 4 ns ns T5 CLOCK low to RADD increment 2 ns T6 T7 AD0:15 setup before CLOCK low AD0:15 hold time after CLOCK low 0 2 ns ns T8 Setup last CLOCK before CONFIGURE low 2 ns T9 T10 CONFIGURE low pulse width ADDREN high to RADD tristate 10 3 ns ns T11 LOAD low prior to 3rd CLOCK low T12 T13 LOAD high pulse CONFIGURE low to READY low T14 CONFIGURE low to SIGNAL PATHS updated 4 ns T15 CLOCK period 20 ns 4 ns TBD TBD ns ns Notes: 1. LDMODE = 1; AUTOCONFIG = 0, RESET– = 1. Figure 3. TQ8025 Timing —␣ RAM Loading, External Configure Pulse Mode T15 CLOCK T4 T12 T11 LOAD ADDREN T3 T10 T5 RADD0:1 0 1 2 3 T1 0 T13 T2 READY T6 AD0:15 T7 D0 D1 D2 D3 T8 T9 CONFIGURE T14 OLD CONFIGURATION SIGNAL PATHS LDMODE = 1; AUTOCONFIG = 1, RESET– = 1, CONFIG = 1. 6 For additional information and latest specifications, see our website: www.triquint.com NEW CONFIGURATION TQ8025 PRELIMINARY DATA SHEET Typical Performance Data Rate: 2.5Gb/s Data Pattern: 2^7 PRBS Note: Measured jitter is 68ps pk-pk. SWITCHING PRODUCTS Signal source jitter is 32ps pk-pk. Rise and Fall Data Rate: 2.5Gb/s Rise Time: 115ps Fall Time: 109ps For additional information and latest specifications, see our website: www.triquint.com 7 TQ8025 PRELIMINARY DATA SHEET Vcc Vcc N.C. N.C. VTT VTT Vcc DI08P DI08N DI09P DI09N Vcc DI10P DI10N DI11P DI11N Vcc DI12P DI12N DI13P DI13N Vcc DI14P DI14N DI15P DI15N Vcc DO15N DO15P DO14N DO14P Vcc GND Figure 4. TQ8025 pinout — top view 33 32 31 30 29 2827 26 25 24 23 22 21 20 19 18 17 16 15 14 1312 11 10 9 8 7 6 5 4 3 2 1 GND Vcc AD15 AD14 AD13 AD12 Vcc AD11 AD10 AD09 AD08 Vcc AD07/DAD3 AD06/DAD2 AD05/DAD1 AD04/DAD0 Vcc AD03/SAD3 AD02/SAD2 AD01/SAD1 AD00/SAD0 Vcc RADD0 RADD1 LOAD RESETVcc AUTOCONFIG CLOCK CONFIG READYVcc Vcc 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 TQ8025 132-pin Heat Spreader Cavity Down Top View GND Vcc LDMODE ADDREN VTT VTT Vcc DI00P DI00N DI01P DI01N Vcc DI02P DI02N DI03P DI03N Vcc DI04P DI04N DI05P DI05N Vcc DI06P DI06N DI07P DI07N Vcc DO00P DO00N DO01P DO01N Vcc Vcc 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 8788 89 90 91 9293 94 95 9697 98 99 8 For additional information and latest specifications, see our website: www.triquint.com 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 Vcc Vcc DO13N DO13P DO12N DO12P Vcc DO11N DO11P DO10N DO10P Vcc DO09N DO09P DO08N DO08P Vcc DO07N DO07P DO06N DO06P Vcc DO05N DO05P DO04N DO04P Vcc DO03N DO03P DO02N DO02P Vcc GND TQ8025 PRELIMINARY DATA SHEET Signal Name/Level Description DI00P-DI15P Data input true and complement Differential data input ports. VH = 0 V, VL = –300 mV max. DI0N-DI15N DO0P-DO15P, Differential CML/PECL input Data output true and complement Internal 50-ohm terminations to VTT (CML = 0 V;ECL = –2.0 V). Differential data output ports. 600 mV min. differential swing. DO0N-DO15N Differential CML/PECL output AD00:15 Input address; TTL input Serial input address, LSB first in time; ADn programs output port n. RADD0:1 RAM address; TTL output, tristate Used to generate address 0-3 during configure load from RAM. ADDREN Enable RADD0:2; TTL input When low, enables RADD0:1; when high, forces RADD0:1 tristate. CLOCK AUTOCONFIG Clock; TTL input Configure mode; TTL input Controls cycle time of address generator and AUTOCONFIG. When high, internal CONFIGURE is automatically generated. READY READY; open-drain output LOAD LOAD; TTL input Indicates end of AUTOCONFIG or end of address LOAD cycle when high. Reset low by RESET-, CONFIG low, or LOAD rising. Requires external pullup to VCC. For LDMODE=1, ADDREN=0: AUTOCONFIG=0, rising LOAD causes ADDR0:1 to generate RAM addresses, then READY is asserted after four clock ticks. For AUTOCONFIG=1, LOAD rising causes ADDR0:1 to generate addresses, causing an internal CONFIG to be generated, after which READY is asserted. For LDMODE=0, see SAD0:3 and DAD0:3. Used to load address contents of internal address registers. Active LOW. Crosspoint will be configured within 4 ns (objective) of CONFIG falling low. When floated high, AD0-15 are used for configuration. When tied low, SAD0-3 and DAD0-3 are used for configuration. When AUTOCONFIG is disabled, and AD08-15 are ignored. When LDMODE is low, specifies input address to be connected to output port specified by DAD0:3. Latched by falling LOAD (LDMODE=0). When LDMODE is low, specifies output address to be connected to input port specified by SAD0:3. Latched by falling LOAD (LDMODE=0). Power and ground pins. VTT = GND for CML inputs; VTT = VCC – 2V for PECL inputs. While low, programs all output ports to connect to input port 0. Strobing CONFIG after reset restores user port programming if device power was stable since last user programming and during RESET–. Active low, Schmitt triggered. CONFIGURE CONFIGURE; TTL input LDMODE Load Mode; TTL input SAD0:3 Source Address; TTL inputs DAD0:3 Destination Address; TTL input VCC, GND, VTT +5V, Ground; Termination Voltage Reset; TTL Input RESET– For additional information and latest specifications, see our website: www.triquint.com SWITCHING PRODUCTS Table 10. TQ8025 Pin Descriptions 9 TQ8025 PRELIMINARY DATA SHEET Figure 5. Mechanical Dimensions Bottom view 1.170 +.006 .950 +.006 .800 Top view 132 PIN 1 INDEX 1 A A CERAMIC OR METAL LID 0.325 ± .005 .025 .010 +.0015 BSC CHIP CAPACITOR, 4 PLACES 1. Part is symmetrical about the center axes. 2. Centerline bisects center pin in both directions. 3. See pad detail below. Section A-A HEAT SPREADER DEVICE .060 .125 0.025 centers 0.015 CL SEATING PLANE 0.010 .064 0.105 0.525 CL PAD LAYOUT DETAIL Ordering Information TQ8025 2.5 Gb/s 16x16 Crosspoint Switch Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or ommisions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision 0.3.A August 1998 10 For additional information and latest specifications, see our website: www.triquint.com