RC Snubber Networks For Thyristor Power Control and Transient Suppression

AN1048/D
RC Snubber Networks
For Thyristor
Power Control and
Transient Suppression
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APPLICATION NOTE
By George Templeton
Thyristor Applications Engineer
INTRODUCTION
Edited and Updated
ǒdV
Ǔ
dt
RC networks are used to control voltage transients that
could falsely turn-on a thyristor. These networks are called
snubbers.
The simple snubber consists of a series resistor and
capacitor placed around the thyristor. These components
along with the load inductance form a series CRL circuit.
Snubber theory follows from the solution of the circuit’s
differential equation.
Many RC combinations are capable of providing acceptable performance. However, improperly used snubbers can
cause unreliable circuit operation and damage to the semiconductor device.
Both turn-on and turn-off protection may be necessary
for reliability. Sometimes the thyristor must function with a
range of load values. The type of thyristors used, circuit
configuration, and load characteristics are influential.
Snubber design involves compromises. They include
cost, voltage rate, peak voltage, and turn-on stress. Practical solutions depend on device and circuit physics.
dt
and regeneration (Figure 1). A change in voltage across the
junction capacitance induces a current through it. This cur-
ǒ dt Ǔ
rent is proportional to the rate of voltage change dV . It
triggers the device on when it becomes large enough to
raise the sum of the NPN and PNP transistor alphas to unity.
A
A
IA
IB
P
CJ
P
CJ
N
I1
IC
N
IJ
IC
NB
P
I2
IJ
NPN
dv
dt
G
IB
N
IK
TWO TRANSISTOR MODEL
OF
SCR
1
G
ǒdV
Ǔ
dt
s
PB
t
CJ
CEFF +
1*(aN)ap)
Figure 6.1.
C
CJ
dV
CJ
dt
IA +
1 * (aN ) ap)
K
retain a blocking state under the influence of a voltage
transient.
PE
V
PNP
WHAT IS STATIC dV ?
dt
dV
Static
is a measure of the ability of a thyristor to
dt
June, 2008 − Rev. 3
DEVICE PHYSICS
Static dV turn-on is a consequence of the Miller effect
STATIC dV
dt
© Semiconductor Components Industries, LLC, 2008
s
NE
K
INTEGRATED
STRUCTURE
Model
Publication Order Number:
AN1048/D
AN1048/D
ǒ Ǔ
170
CONDITIONS INFLUENCING dV
dt s
150
Transients occurring at line crossing or when there is no
initial voltage across the thyristor are worst case. The collector junction capacitance is greatest then because the
depletion layer widens at higher voltage.
Small transients are incapable of charging the selfcapacitance of the gate layer to its forward biased threshold
voltage (Figure 2). Capacitance voltage divider action
between the collector and gate-cathode junctions and builtin resistors that shunt current away from the cathode emitter are responsible for this effect.
STATIC dV (V/ μs)
dt
110
90
70
50
30
10
25
40
55
70
85
100
115
130
145
TJ, JUNCTION TEMPERATURE (°C)
180
Figure 6.3. Exponential
160
MAC 228A10 TRIAC
TJ = 110°C
140
STATIC dV (V/ μs)
dt
MAC 228A10
VPK = 800 V
130
ǒdV
Ǔ
dt
120
s
ǒdV
Ǔ versus Temperature
dt
s
FAILURE MODE
Occasional unwanted turn-on by a transient may be
acceptable in a heater circuit but isn’t in a fire prevention
sprinkler system or for the control of a large motor. Turn-on
is destructive when the follow-on current amplitude or rate
is excessive. If the thyristor shorts the power line or a
charged capacitor, it will be damaged.
100
80
60
40
20
0
100
200
300
400
500
600
PEAK MAIN TERMINAL VOLTAGE (VOLTS)
Figure 6.2. Exponential
700
Static dV turn-on is non-destructive when series imped-
800
dt
ance limits the surge. The thyristor turns off after a half-
ǒdV
Ǔ versus Peak Voltage
dt
cycle of conduction. High dV aids current spreading in the
dt
s
thyristor, improving its ability to withstand dI. Breakdown
dt
turn-on does not have this benefit and should be prevented.
Static dV does not depend strongly on voltage for operadt
tion below the maximum voltage and temperature rating.
Avalanche multiplication will increase leakage current and
140
120
reduce dV capability if a transient is within roughly 50 volts
dt
STATIC dV (V/ μs)
dt
of the actual device breakover voltage.
A higher rated voltage device guarantees increased dV at
80
dt
lower voltage. This is a consequence of the exponential rating method where a 400 V device rated at 50 V/μs has a
60
dt
rating. However, the same diffusion recipe usually applies
for all voltages. So actual capabilities of the product are not
much different.
Heat increases current gain and leakage, lowering
s
RINTERNAL = 600 Ω
40
higher dV to 200 V than a 200 V device with an identical
ǒdV
Ǔ,
dt
MAC 228A10
800 V 110°C
100
20
0
10
100
1000
GATE‐MT1 RESISTANCE (OHMS)
ǒ Ǔ
dV
Figure 6.4. Exponential dt s versus
Gate to MT1 Resistance
the gate trigger voltage and noise immunity
(Figure 3).
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10,000
AN1048/D
ǒ Ǔ
10
MEG
GATE‐CATHODE RESISTANCE (OHMS)
IMPROVING dV
dt s
Static dV can be improved by adding an external resistor
dt
from the gate to MT1 (Figure 4). The resistor provides a
path for leakage and dV induced currents that originate in
dt
the drive circuit or the thyristor itself.
Non-sensitive devices (Figure 5) have internal shorting
resistors dispersed throughout the chip’s cathode area. This
design feature improves noise immunity and high temperature blocking stability at the expense of increased trigger
and holding current. External resistors are optional for nonsensitive SCRs and TRIACs. They should be comparable in
size to the internal shorting resistance of the device (20 to
100 ohms) to provide maximum improvement. The internal
resistance of the thyristor should be measured with an ohmmeter that does not forward bias a diode junction.
1
MEG
G
K
100
K
0.01
0.1
1
10
100
STATIC dV (Vńms)
dt
ǒ Ǔ
dV
Figure 6.6. Exponential dt
versus
s
Gate-Cathode Resistance
A gate-cathode capacitor (Figure 7) provides a shunt
path for transient currents in the same manner as the resistor. It also filters noise currents from the drive circuit and
enhances the built-in gate-cathode capacitance voltage
divider effect. The gate drive circuit needs to be able to
charge the capacitor without excessive delay, but it does
not need to supply continuous current as it would for a
2000
STATIC dV (V/ μs)
dt
A
10
V
10K
0.001
2200
MAC 15‐8
VPK = 600 V
1800
MCR22‐006
TA = 65°C
1600
1400
resistor that increases dV the same amount. However, the
1200
capacitor does not enhance static thermal stability.
dt
1000
130
800
120
50
60
70
80
90
100
110
TJ, JUNCTION TEMPERATURE (°C)
120
130
STATIC dV (V/ μs)
dt
600
ǒ Ǔ
dV
Figure 6.5. Exponential dt s versus
Junction Temperature
MAC 228A10
800 V 110°C
110
100
90
80
70
Sensitive gate TRIACs run 100 to 1000 ohms. With an
60
0.001
external resistor, their dV capability remains inferior to
dt
ǒ dt Ǔ
1
ǒ Ǔ
non-sensitive devices because lateral resistance within the
gate layer reduces its benefit.
Sensitive gate SCRs (IGT t 200 μA) have no built-in
resistor. They should be used with an external resistor. The
recommended value of the resistor is 1000 ohms. Higher
values reduce maximum operating temperature and dV
0.01
0.1
GATE TO MT1 CAPACITANCE (μF)
dV
Figure 6.7. Exponential dt versus Gate
s
to MT1 Capacitance
ǒ dt Ǔ
The maximum dV
s
improvement occurs with a short.
Actual improvement stops before this because of spreading
resistance in the thyristor. An external capacitor of about
0.1 μF allows the maximum enhancement at a higher value
of RGK.
s
(Figure 6). The capability of these parts varies by more than
100 to 1 depending on gate-cathode termination.
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AN1048/D
ǒ dt Ǔ .
One should keep the thyristor cool for the highest dV
for sinusoidal currents is given by the slope of the secant
line between the 50% and 0% levels as:
s
Also devices should be tested in the application circuit at
the highest possible temperature using thyristors with the
lowest measured trigger current.
f I TM
ǒdIdtǓc + 61000
Ańms
where f = line frequency and ITM = maximum on-state current in the TRIAC.
Turn-off depends on both the Miller effect displacement
TRIAC COMMUTATING dV
dt
current generated by dV across the collector capacitance
WHAT IS COMMUTATING dV ?
dt
The commutating dV rating applies when a TRIAC has
dt
dt
and the currents resulting from internal charge storage
within the volume of the device (Figure 10). If the reverse
recovery current resulting from both these components is
high, the lateral IR drop within the TRIAC base layer will
forward bias the emitter and turn the TRIAC on. Commu-
R
L
dt
itive direction of current conduction because of device
geometry. The gate is on the top of the die and obstructs
current flow.
Recombination takes place throughout the conduction
period and along the back side of the current wave as it
declines to zero. Turn-off capability depends on its shape. If
ǒdtǓ
2
i
VLINE
tating dV capability is lower when turning off from the pos-
the current amplitude is small and its zero crossing dI
VMT2‐1
G
1
ǒdIdtǓ
PHASE
ANGLE
c
ǒ dt Ǔ
ǒdVdtǓ
VLINE
ǒ dt Ǔ
crossing, dV
c
Figure 6.8. TRIAC Inductive Load Turn-Off
ǒdV
Ǔ
dt
s
the volume charge begins to influence turn-off, requiring a
larger snubber. When the current is large or has rapid zero
TIME
TIME
c
has little influence. Commutating dI and
dt
delay time to voltage reapplication determine whether turnoff will be successful or not (Figures 11, 12).
c
G
ǒ Ǔ
MT1
dV DEVICE PHYSICS
dt c
TOP
A TRIAC functions like two SCRs connected in inverseparallel. So, a transient of either polarity turns it on.
There is charge within the crystal’s volume because of
prior conduction (Figure 9). The charge at the boundaries
of the collector junction depletion layer responsible for
N
P
N
+
N
N
N
Previously
Conducting Side
N
ǒdV
Ǔ is also present. TRIACs have lower ǒdV
Ǔ than
dt s
dt c
ǒdV
Ǔ because of this additional charge.
dt
N
-
N
s
The volume charge storage within the TRIAC depends
on the peak current before turn-off and its rate of zero
ǒdtǓ
REVERSE RECOVERY
CURRENT PATH
crossing dI . In the classic circuit, the load impedance
c
ǒdtǓ
is
becomes limited by dV . At moderate current amplitudes,
Φ
i
c
low, there is little volume charge storage and turn-off
VMT2‐1
VOLTAGE/CURRENT
been conducting and attempts to turn-off with an inductive
load. The current and voltage are out of phase (Figure 8).
The TRIAC attempts to turn-off as the current drops below
the holding value. Now the line voltage is high and in the
opposite polarity to the direction of conduction. Successful
turn-off requires the voltage across the TRIAC to rise to the
instantaneous line voltage at a rate slow enough to prevent
retriggering of the device.
MT2
LATERAL VOLTAGE
DROP
STORED CHARGE
FROM POSITIVE
CONDUCTION
Figure 6.9. TRIAC Structure and Current Flow
at Commutation
and line frequency determine dI . The rate of crossing
c
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VOLTAGE/CURRENT
ǒ Ǔ
ǒdtdiǓ
CONDITIONS INFLUENCING dV
dt c
Commutating dV depends on charge storage and recovdt
c
ǒdV
Ǔ
dt
ery dynamics in addition to the variables influencing static
dV. High temperatures increase minority carrier life-time
dt
c
and the size of recovery currents, making turn-off more difficult. Loads that slow the rate of current zero-crossing aid
turn-off. Those with harmonic content hinder turn-off.
TIME
0
VMT2‐1
VOLUME
STORAGE
CHARGE
CHARGE
DUE TO
dV/dt
IRRM
Circuit Examples
Figure 13 shows a TRIAC controlling an inductive load
in a bridge. The inductive load has a time constant longer
than the line period. This causes the load current to remain
constant and the TRIAC current to switch rapidly as the line
voltage reverses. This application is notorious for causing
Figure 6.10. TRIAC Current and Voltage
at Commutation
ǒdtǓ
TRIAC turn-off difficulty because of high dI .
C
RS
i
E
V
MAIN TERMINAL VOLTAGE (V)
LS
ǒdIdtǓc
DC MOTOR
-
i
60 Hz
R
L
+
t
ǒRL u8.3 msǓ
E
Figure 6.13. Phase Controlling a Motor in a Bridge
VT
0
td
High currents lead to high junction temperatures and
rates of current crossing. Motors can have 5 to 6 times the
normal current amplitude at start-up. This increases both
junction temperature and the rate of current crossing, leading to turn-off problems.
The line frequency causes high rates of current crossing
in 400 Hz applications. Resonant transformer circuits are
doubly periodic and have current harmonics at both the primary and secondary resonance. Non-sinusoidal currents
can lead to turn-off difficulty even if the current amplitude
is low before zero-crossing.
TIME
Figure 6.11. Snubber Delay Time
0.5
NORMALIZED DELAY TIME
(td* = W0 td)
c
0.2
0.1
0.2
0.02
0.05
0.03
0.02
RL = 0
M=1
IRRM = 0
VT
0.005 0.01 0.02 0.05
FAILURE MODE
0.2 0.3 0.5
c
failure causes a loss of phase control. Temporary
turn-on or total turn-off failure is possible. This can be
destructive if the TRIAC conducts asymmetrically causing a
dc current component and magnetic saturation. The winding
resistance limits the current. Failure results because of
excessive surge current and junction temperature.
0.005
0.1
c
ǒdV
Ǔ
dt
0.01
E
0.001 0.002
ǒdV
Ǔ
dt
0.05
0.1
1
DAMPING FACTOR
Figure 6.12. Delay Time To Normalized Voltage
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AN1048/D
ǒ Ǔ
IMPROVING dV
dt c
Is +
ǒ dt Ǔ
The same steps that improve dV
s
ǒ dt Ǔ
aid dV
c
Hs ML
where :
0.4 p N
Hs = MMF to saturate = 0.5 Oersted
ML = mean magnetic path length = 4.99 cm.
except
when stored charge dominates turn-off. Steps that reduce
the stored charge or soften the commutation are necessary
then.
Larger TRIACs have better turn-off capability than
smaller ones with a given load. The current density is lower
in the larger device allowing recombination to claim a
greater proportion of the internal charge. Also junction
temperatures are lower.
TRIACs with high gate trigger currents have greater
turn-off ability because of lower spreading resistance in the
gate layer, reduced Miller effect, or shorter lifetime.
The rate of current crossing can be adjusted by adding a
commutation softening inductor in series with the load.
Small high permeability “square loop” inductors saturate
causing no significant disturbance to the load current. The
inductor resets as the current crosses zero introducing a
large inductance into the snubber circuit at that time. This
slows the current crossing and delays the reapplication of
blocking voltage aiding turn-off.
The commutation inductor is a circuit element that
introduces time delay, as opposed to inductance, into the
Is +
(.5) (4.99)
+ 60 mA.
.4 p 33
SNUBBER PHYSICS
UNDAMPED NATURAL RESONANCE
w0 + I Radiansńsecond
Ǹ LC
Resonance determines dV and boosts the peak capacitor
dt
voltage when the snubber resistor is small. C and L are
related to one another by ω02. dV scales linearly with ω0
dt
when the damping factor is held constant. A ten to one
reduction in dV requires a 100 to 1 increase in either
component.
dt
DAMPING FACTOR
ρ+R
2
ǸCL
The damping factor is proportional to the ratio of the
circuit loss and its surge impedance. It determines the trade
circuit. It will have little influence on observed dV at the
dt
device. The following example illustrates the improvement
resulting from the addition of an inductor constructed by
winding 33 turns of number 18 wire on a tape wound core
(52000-1A). This core is very small having an outside
diameter of 3/4 inch and a thickness of 1/8 inch. The delay
time can be calculated from:
off between dV and peak voltage. Damping factors between
dt
0.01 and 1.0 are recommended.
The Snubber Resistor
Damping and dV
dt
When ρ t 0.5, the snubber resistor is small, and dV
(N A B 10 *8)
ts +
where:
E
dt
depends mostly on resonance. There is little improvement
in dV for damping factors less than 0.3, but peak voltage
dt
ts = time delay to saturation in seconds.
B = saturating flux density in Gauss
A = effective core cross sectional area in cm2
N = number of turns.
and snubber discharge current increase. The voltage wave
has a 1-COS (θ) shape with overshoot and ringing. Maximum dV occurs at a time later than t = 0. There is a time
dt
delay before the voltage rise, and the peak voltage almost
doubles.
When ρ u 0.5, the voltage wave is nearly exponential in
For the described inductor:
t s + (33 turns) (0.076 cm 2 ) (28000 Gauss)
(1 10 −8 ) ń (175 V) + 4.0 ms.
shape. The maximum instantaneous dV occurs at t = 0.
The saturation current of the inductor does not need to be
much larger than the TRIAC trigger current. Turn-off failure will result before recovery currents become greater than
this value. This criterion allows sizing the inductor with the
following equation:
depends mostly on its value. There is some overshoot even
through the circuit is overdamped.
High load inductance requires large snubber resistors and
small snubber capacitors. Low inductances imply small
resistors and large capacitors.
dt
There is little time delay and moderate voltage overshoot.
When ρ u 1.0, the snubber resistor is large and dV
dt
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AN1048/D
Damping and Transient Voltages
Table 1 shows suggested minimum resistor values estimated (Appendix A) by testing a 20 piece sample from the
four different TRIAC die sizes.
Figure 14 shows a series inductor and filter capacitor
connected across the ac main line. The peak to peak voltage
of a transient disturbance increases by nearly four times.
Also the duration of the disturbance spreads because of
ringing, increasing the chance of malfunction or damage to
the voltage sensitive circuit. Closing a switch causes this
behavior. The problem can be reduced by adding a damping
resistor in series with the capacitor.
100 μH
TRIAC Type
0.05
0.1
μF
V
Rs
Ohms
dI
dt
A/μs
200
300
400
600
800
3.3
6.8
11
39
51
170
250
308
400
400
VOLTAGE
SENSITIVE
CIRCUIT
Reducing dI
dt
+700
V (VOLTS)
Peak VC
Volts
Non-Sensitive Gate
(IGT u 10 mA)
8 to 40 A(RMS)
340 V
0 10 μs
Table 1. Minimum Non-inductive Snubber Resistor
for Four Quadrant Triggering.
TRIAC dI can be improved by avoiding quadrant 4
dt
triggering. Most optocoupler circuits operate the TRIAC in
quadrants 1 and 3. Integrated circuit drivers use quadrants 2
and 3. Zero crossing trigger devices are helpful because
they prohibit triggering when the voltage is high.
Driving the gate with a high amplitude fast rise pulse
0
-700
0
10
TIME (μs)
20
increases dI capability. The gate ratings section defines the
dt
Figure 6.14. Undamped LC Filter Magnifies and
Lengthens a Transient
maximum allowed current.
Inductance in series with the snubber capacitor reduces
dI. It should not be more than five percent of the load
dt
inductance to prevent degradation of the snubber’s dV
dt
dI
dt
Non-Inductive Resistor
suppression capability. Wirewound snubber resistors
sometimes serve this purpose. Alternatively, a separate
inductor can be added in series with the snubber capacitor.
It can be small because it does not need to carry the load
current. For example, 18 turns of AWG No. 20 wire on a
T50-3 (1/2 inch) powdered iron core creates a non-saturating 6.0 μH inductor.
A 10 ohm, 0.33 μF snubber charged to 650 volts resulted
The snubber resistor limits the capacitor discharge
current and reduces dI stress. High dI destroys the thyristor
dt
dt
even though the pulse duration is very short.
The rate of current rise is directly proportional to circuit
voltage and inversely proportional to series inductance.
The snubber is often the major offender because of its low
inductance and close proximity to the thyristor.
With no transient suppressor, breakdown of the thyristor
sets the maximum voltage on the capacitor. It is possible to
exceed the highest rated voltage in the device series
because high voltage devices are often used to supply low
voltage specifications.
The minimum value of the snubber resistor depends on
the type of thyristor, triggering quadrants, gate current
amplitude, voltage, repetitive or non-repetitive operation,
and required life expectancy. There is no simple way to predict the rate of current rise because it depends on turn-on
speed of the thyristor, circuit layout, type and size of snubber capacitor, and inductance in the snubber resistor. The
equations in Appendix D describe the circuit. However, the
values required for the model are not easily obtained except
by testing. Therefore, reliability should be verified in the
actual application circuit.
in a 1000 A/μs dI. Replacement of the non-inductive snubdt
ber resistor with a 20 watt wirewound unit lowered the rate
of rise to a non-destructive 170 A/μs at 800 V. The inductor
gave an 80 A/μs rise at 800 V with the non−inductive
resistor.
The Snubber Capacitor
A damping factor of 0.3 minimizes the size of the snubber capacitor for a given value of dV. This reduces the cost
dt
and physical dimensions of the capacitor. However, it raises
voltage causing a counter balancing cost increase.
Snubber operation relies on the charging of the snubber
capacitor. Turn-off snubbers need a minimum conduction
angle long enough to discharge the capacitor. It should be at
least several time constants (RS CS).
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STORED ENERGY
snubber inductor and limits the rate of inrush current if the
Inductive Switching Transients
device does turn on. Resistance in the load lowers dV and
E + 1 L I 0 2 Watt−seconds or Joules
2
VPK (Figure 16).
current in Amperes flowing in the
inductor at t = 0.
Resonant charging cannot boost the supply voltage at
turn-off by more than 2. If there is an initial current flowing
in the load inductance at turn-off, much higher voltages are
possible. Energy storage is negligible when a TRIAC turns
off because of its low holding or recovery current.
The presence of an additional switch such as a relay, thermostat or breaker allows the interruption of load current and
the generation of high spike voltages at switch opening. The
energy in the inductance transfers into the circuit capacitance
and determines the peak voltage (Figure 15).
1.4
2.2
E
1.2
dV
dt
2
VPK
1.9
1
NORMALIZED dV
dt
1.8
M = 0.75
M=1
(dVdt)/ (E W0 )
2.1
1.7
0.8
1.6
1.5
M = 0.5
0.6
1.4
1.3
M = 0.25
0.4
L
1.2
M=0
I
R
VPK
M = RS / (RL + RS)
dV + I V
+ I
dt
C PK
0
ǒ
Ǹ
L
C
0.4
0.6
DAMPING FACTOR
I
0.8
RRM
+ 0
1
RS
R L ) RS
Ǔ
Figure 6.16. 0 To 63% dV
dt
(b.) Unprotected Circuit
Figure 6.15. Interrupting Inductive Load Current
CHARACTERISTIC VOLTAGE WAVES
Damping factor and reverse recovery current determine
the shape of the voltage wave. It is not exponential when
the snubber damping factor is less than 0.5 (Figure 17) or
when significant recovery currents are present.
Capacitor Discharge
T h e e n e rg y s t o r e d i n t h e s n u b b e r c a p a c i t o r
transfers to the snubber resistor and
V MT (VOLTS)
2‐1
thyristor every time it turns on. The power loss is proportional to frequency (PAV = 120 Ec @ 60 Hz).
CURRENT DIVERSION
The current flowing in the load inductor cannot change
instantly. This current diverts through the snubber resistor
causing a spike of theoretically infinite dV with magnitude
dt
equal to (IRRM R) or (IH R).
500
400
300
200
1
0.3
ƪ
at turn-off. However, they help to protect the
ǒ dt Ǔ . The load serves as the
ρ = 0.1
ρ = 0.3
ρ=1
0
0
Highly inductive loads cause increased voltage and
ρ=0
0.1
100
0
LOAD PHASE ANGLE
thyristor from transients and dV
0.2
M + RESISTIVE DIVISION RATIO +
(a.) Protected Circuit
c
0.9
0
SLOW
ǒdV
Ǔ
dt
1
OPTIONAL
C
ǒEc + 12 C V2Ǔ
1.1
0.2
FAST
NORMALIZED PEAK VOLTAGE
VPK /E
I0 =
dt
0.7
1.4
ǒ Ǔ
2.1
2.8 3.5 4.2
TIME (μs)
4.9
5.6
0*63% dV
+ 100 Vńms, E + 250 V,
dt s
R + 0, I RRM + 0
L
ƫ
Figure 6.17. Voltage Waves For Different
Damping Factors
s
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6.3
7
NORMALIZED PEAK VOLTAGE AND
dV
dt
AN1048/D
COMPLEX LOADS
2.8
2.6
2.4
E
ǒdVdtǓ MAX
2.2
2
Many real-world inductances are non-linear. Their core
materials are not gapped causing inductance to vary with
current amplitude. Small signal measurements poorly characterize them. For modeling purposes, it is best to measure
them in the actual application.
Complex load circuits should be checked for transient
voltages and currents at turn-on and off. With a capacitive
load, turn-on at peak input voltage causes the maximum
surge current. Motor starting current runs 4 to 6 times the
steady state value. Generator action can boost voltages
above the line value. Incandescent lamps have cold start
currents 10 to 20 times the steady state value. Transformers
generate voltage spikes when they are energized. Power
factor correction circuits and switching devices create
complex loads. In most cases, the simple CRL model
allows an approximate snubber design. However, there is
no substitute for testing and measuring the worst case load
conditions.
0-63%
dV
dt
1.8
10-63%
1.6
1.4
1.2
1
VPK
10-63
dV
%
dt
0.8
0.6
ǒdVdtǓ
0.4
0.2
0
o
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
DAMPING FACTOR (ρ)
(R L + 0, M + 1, I RRM + 0)
V PK
dVńdt
NORMALIZED V PK +
NORMALIZED dV +
E
dt
E w0
SURGE CURRENTS IN INDUCTIVE CIRCUITS
Figure 6.18. Trade-Off Between VPK and dV
dt
Inductive loads with long L/R time constants cause
asymmetric multi-cycle surges at start up (Figure 20). Triggering at zero voltage crossing is the worst case condition.
The surge can be eliminated by triggering at the zero current crossing angle.
A variety of wave parameters (Figure 18) describe dV
dt
Some are easy to solve for and assist understanding. These
include the initial dV, the maximum instantaneous dV, and
dt
dt
the average dV to the peak reapplied voltage. The 0 to 63%
ǒdV
Ǔ
dt
dt
s
ǒ dt Ǔ
and 10 to 63% dV
c
definitions on device data
240
VAC
sheets are easy to measure but difficult to compute.
20 MHY
i
0.1
Ω
NON-IDEAL BEHAVIORS
i (AMPERES)
CORE LOSSES
The magnetic core materials in typical 60 Hz loads
introduce losses at the snubber natural frequency. They
appear as a resistance in series with the load inductance and
winding dc resistance (Figure 19). This causes actual dV to
dt
90
0
ZERO VOLTAGE TRIGGERING, IRMS = 30 A
be less than the theoretical value.
L
40
R
80
120
TIME (MILLISECONDS)
160
200
Figure 6.20. Start-Up Surge For Inductive Circuit
Core remanence and saturation cause surge currents.
They depend on trigger angle, line impedance, core characteristics, and direction of the residual magnetization. For
example, a 2.8 kVA 120 V 1:1 transformer with a 1.0
ampere load produced 160 ampere currents at start-up. Soft
starting the circuit at a small conduction angle reduces this
current.
Transformer cores are usually not gapped and saturate
easily. A small asymmetry in the conduction angle causes
magnetic saturation and multi-cycle current surges.
C
L DEPENDS ON CURRENT AMPLITUDE, CORE
SATURATION
R INCLUDES CORE LOSS, WINDING R. INCREASES
WITH FREQUENCY
C WINDING CAPACITANCE. DEPENDS ON
INSULATION, WIRE SIZE, GEOMETRY
Figure 6.19. Inductor Model
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AN1048/D
resistor. The non-inductive snubber circuit is useful when
the load resistance is much larger than the snubber resistor.
Steps to achieve reliable operation include:
1. Supply sufficient trigger current amplitude. TRIACs
have different trigger currents depending on their
quadrant of operation. Marginal gate current or
optocoupler LED current causes halfwave operation.
2. Supply sufficient gate current duration to achieve
latching. Inductive loads slow down the main terminal
current rise. The gate current must remain above the
specified IGT until the main terminal current exceeds
the latching value. Both a resistive bleeder around the
load and the snubber discharge current help latching.
ǒ dt Ǔ
3. Use a snubber to prevent TRIAC dV
c
RL
RS
e
E
CS
e
τ = (RL + RS) CS
E
V step + E
failure.
t=0
4. Minimize designed-in trigger asymmetry. Triggering
must be correct every half-cycle including the first. Use
a storage scope to investigate circuit behavior during the
first few cycles of turn-on. Alternatively, get the gate
circuit up and running before energizing the load.
5. Derive the trigger synchronization from the line instead
of the TRIAC main terminal voltage. This avoids
regenerative interaction between the core hysteresis
and the triggering angle preventing trigger runaway,
halfwave operation, and core saturation.
6. Avoid high surge currents at start-up. Use a current
probe to determine surge amplitude. Use a soft start
circuit to reduce inrush current.
e(t + o)) + E
R
S
R ) RL
S
ƪǒ
TIME
ƫ
Ǔ
RS
e*tńt ) (1 * e *tńt)
R S ) RL
CAPACITOR
COMPONENT
RESISTOR
COMPONENT
Figure 6.21. Non-Inductive Snubber Circuit
Opto-TRIAC Examples
Single Snubber, Time Constant Design
Figure 22 illustrates the use of the RC time constant
design method. The optocoupler sees only the voltage
across the snubber capacitor. The resistor R1 supplies the
trigger current of the power TRIAC. A worst case design
procedure assumes that the voltage across the power
TRIAC changes instantly. The capacitor voltage rises to
63% of the maximum in one time constant. Then:
DISTRIBUTED WINDING CAPACITANCE
There are small capacitances between the turns and layers of a coil. Lumped together, they model as a single shunt
capacitance. The load inductor behaves like a capacitor at
frequencies above its self-resonance. It becomes ineffective
R1 CS + t +
in controlling dV and VPK when a fast transient such as that
dt
0.63 E
ǒ Ǔ
dV
dt s
ǒ Ǔ
where dV is the rated static dV
dt s
dt
for the optocoupler.
resulting from the closing of a switch occurs. This problem
can be solved by adding a small snubber across the line.
1 A, 60 Hz
SELF-CAPACITANCE
A thyristor has self-capacitance which limits dV when the
dt
VCC
load inductance is large. Large load inductances, high power
factors, and low voltages may allow snubberless operation.
Rin 1
2
L = 318 MHY
10 V/μs
6
MOC
3021
4
180
0.1 μF
170 V
2.4 k
2N6073A
1 V/μs
C1
φ CNTL
SNUBBER EXAMPLES
(0.63)(170)
DESIGN dV +
+ 0.45Vńms
dt
(2400)(0.1mF)
0.63 (170)
WITHOUT INDUCTANCE
Power TRIAC Example
240 μs
Figure 21 shows a transient voltage applied to a TRIAC
controlling a resistive load. Theoretically there will be an
instantaneous step of voltage across the TRIAC. The only
elements slowing this rate are the inductance of the wiring
and the self-capacitance of the thyristor. There is an exponential capacitor charging component added along with a
decaying component because of the IR drop in the snubber
TIME
dV
(Vńms)
dt
Power TRIAC
Optocoupler
0.99
0.35
Figure 6.22. Single Snubber For Sensitive Gate TRIAC
and Phase Controllable Optocoupler (ρ = 0.67)
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AN1048/D
The optocoupler conducts current only long enough to
trigger the power device. When it turns on, the voltage
between MT2 and the gate drops below the forward threshold voltage of the opto-TRIAC causing turn-off. The optos
80
when the power TRIAC turns off later
70
LOAD CURRENT (mA RMS)
ǒ dt Ǔ
coupler sees dV
However a power TRIAC along with the optocoupler
should be used for higher load currents.
in the conduction cycle at zero current crossing. Therefore,
it is not necessary to design for the lower optocoupler
ǒdV
Ǔ
dt
c
rating. In this example, a single snubber designed
for the optocoupler protects both devices.
MOC3031
2
3
40
30
CS = 0.001
20
10
100
1
CS = 0.01
50
NO SNUBBER
1 MHY
VCC
60
0
4
1N4001
5
6
51
MCR265-4
MCR265-4
100 1N4001
430 120 V
400 Hz
20
30
40
50
60
70
80
TA, AMBIENT TEMPERATURE (°C)
90
100
(RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5)
0.022
μF
Figure 6.24. MOC3062 Inductive Load Current versus TA
A phase controllable optocoupler is recommended with a
power device. When the load current is small, a MAC97A
TRIAC is suitable.
Unusual circuit conditions sometimes lead to unwanted
(50 V/μs SNUBBER, ρ = 1.0)
Figure 6.23. Anti-Parallel SCR Driver
ǒ dt Ǔ
operation of an optocoupler in dV
Optocouplers with SCRs
c
mode. Very large cur-
rents in the power device cause increased voltages between
MT2 and the gate that hold the optocoupler on. Use of a
larger TRIAC or other measures that limit inrush current
solve this problem.
Very short conduction times leave residual charge in the
optocoupler. A minimum conduction angle allows recovery
before voltage reapplication.
Anti-parallel SCR circuits result in the same dV across
dt
the optocoupler and SCR (Figure 23). Phase controllable
opto-couplers require the SCRs to be snubbed to their lower
dV rating. Anti-parallel SCR circuits are free from the
dt
charge storage behaviors that reduce the turn-off capability
of TRIACs. Each SCR conducts for a half-cycle and has the
next half cycle of the ac line in which to recover. The turn-
THE SNUBBER WITH INDUCTANCE
off dV of the conducting SCR becomes a static forward
dt
blocking dV for the other device. Use the SCR data sheet
dt
dV rating in the snubber design.
dt s
Consider an overdamped snubber using a large capacitor
whose voltage changes insignificantly during the time
under consideration. The circuit reduces to an equivalent
L/R series charging circuit.
The current through the snubber resistor is:
ǒ Ǔ
A SCR used inside a rectifier bridge to control an ac load
will not have a half cycle in which to recover. The available
time decreases with increasing line voltage. This makes the
circuit less attractive. Inductive transients can be suppressed by a snubber at the input to the bridge or across the
SCR. However, the time limitation still applies.
i+ V
Rt
ǒ1 * e*ttǓ ,
and the voltage across the TRIAC is:
e + i R S.
The voltage wave across the TRIAC has an exponential
rise with maximum rate at t = 0. Taking its derivative gives
its value as:
ǒ Ǔ
OPTO dV
dt c
ǒdV
Ǔ
dt
Zero-crossing optocouplers can be used to switch
inductive loads at currents less than 100 mA (Figure 24).
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11
0
+
V RS
L
.
AN1048/D
φ = measured phase angle between line V and load I
RL = measured dc resistance of the load.
Then
Highly overdamped snubber circuits are not practical
designs. The example illustrates several properties:
1. The initial voltage appears completely across the circuit
inductance. Thus, it determines the rate of change of
current through the snubber resistor and the initial dV.
V RMS
Z+
dt
This result does not change when there is resistance in
the load and holds true for all damping factors.
2. The snubber works because the inductor controls the
rate of current change through the resistor and the rate
of capacitor charging. Snubber design cannot ignore
the inductance. This approach suggests that the snubber
capacitance is not important but that is only true for
this hypothetical condition. The snubber resistor shunts
the thyristor causing unacceptable leakage when the
capacitor is not present. If the power loss is tolerable,
I RMS
ǸRL2 ) XL2
XL
L+
2 p f Line
XL +
ǸZ2 * RL2 and
.
If only the load current is known, assume a pure inductance.
This gives a conservative design. Then:
L+
V RMS
2 p f Line I RMS
where E + Ǹ2 V RMS.
For example:
E + Ǹ2 120 + 170 V; L +
dV can be controlled without the capacitor. An
dt
120
+ 39.8 mH.
(8 A) (377 rps)
Read from the graph at ρ = 0.6, VPK = (1.25) 170 = 213 V.
example is the soft-start circuit used to limit inrush
current in switching power supplies (Figure 25).
Use 400 V TRIAC. Read dV
dt (ρ+0.6)
+ 1.0.
2. Apply the resonance criterion:
ǒ
RS
E
AC LINE SNUBBER
L
RECTIFIER
BRIDGE
C1
G
C+
ǒ Ǔ
G
10 3 r ps.
1 + 0.029 m F
w0 2 L
3. Apply the damping criterion:
RS
AC LINE SNUBBER
L
Ǔ
5 10 6 VńS
w0 +
+ 29.4
(1) (170 V)
ER
dV + S
dt f
L
E
Ǔ ǒ
w0 + spec dV ń dV E .
dt
dt (P)
Snubber With No C
RECTIFIER
BRIDGE
RS + 2 ρ
C1
Figure 26 shows a MAC15 TRIAC turn-off safe
operating area curve. Turn-off occurs without problem
ǒ Ǔ
under the curve. The region is bounded by static dV at low
TRIAC DESIGN PROCEDURE dV
dt c
1. Refer to Figure 18 and select a particular damping
dt
dI
values of
and delay time at high currents. Reduction
dt c
ǒ Ǔ
factor (ρ) giving a suitable trade-off between VPK and dV.
dt
Determine the normalized dV corresponding to the chosen
dt
of the peak current permits operation at higher line
frequency. This TRIAC operated at f = 400 Hz, TJ = 125°C,
and ITM = 6.0 amperes using a 30 ohm and 0.068 μF
snubber. Low damping factors extend operation to higher
damping factor.
The voltage E depends on the load phase angle:
ǒ Ǔ
10 *3 + 1400 ohms.
10 *6
ǒdV
Ǔ SAFE AREA CURVE
dt c
Figure 6.25. Surge Current Limiting For
a Switching Power Supply
XL
E + Ǹ2 VRMS Sin (f) where f + tan*1
RL
39.8
ǸCL + 2 (0.6) Ǹ0.029
ǒdIdtǓ , but capacitor sizes increase. The addition of a small,
c
saturable commutation inductor extends the allowed
current rate by introducing recovery delay time.
where
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AN1048/D
One hundred μH is a suggested value for starting the
design. Plug the assumed inductance into the equation for
C. Larger values of inductance result in higher snubber
-ITM = 15 A
resistance and reduced dI. For example:
100
dt
ǒǓ
( dVdt )c (V/ μs)
dI + 6fITM
dt c
Given E = 240 Ǹ2 + 340 V.
10 *3Ańms
Pick ρ = 0.3.
Then from Figure 18, VPK = 1.42 (340) = 483 V.
Thus, it will be necessary to use a 600 V device. Using the
previously stated formulas for ω0, C and R we find:
10
WITH COMMUTATION L
50 10 6 VńS
w0 +
+ 201450 rps
(0.73) (340 V)
1
C+
0.1
10
14
18
22
26
30
34
38
ǒdIdtǓ AMPERESńMILLISECOND
42
46
50
R + 2 (0.3)
c
ǒ
1
(201450) 2 (100
100 10 *6 + 12 ohms
0.2464 10 *6
Ǔ
ǒdV
Ǔ versus ǒdtdIǓ T
dt
c
c
J
VARIABLE LOADS
The snubber should be designed for the smallest load
= 125°C
inductance because dV will then be highest because of its
dt
dependence on ω0. This requires a higher voltage device for
operation with the largest inductance because of the corresponding low damping factor.
STATIC dV DESIGN
dt
Figure 28 describes dV for an 8.0 ampere load at various
There is usually some inductance in the ac main and
power wiring. The inductance may be more than 100 μH if
there is a transformer in the circuit or nearly zero when a
shunt power factor correction capacitor is present. Usually
the line inductance is roughly several μH. The minimum
inductance must be known or defined by adding a series
inductor to insure reliable operation (Figure 27).
dt
power factors. The minimum inductance is a component
added to prevent static dV firing with a resistive load.
dt
8 A LOAD
R
BTA08-800CW3G
10
100 μH
20 A
L
68 Ω
0.33 μF
120 V
60 Hz
0.033 μF
t 50 V/μs
ǒdV
Ǔ
dt
LS
1
340
V
+ 0.2464 m F
Ǹ
MAC16-8, COMMUTATIONALL + 33TURNS# 18,
52000-1ATAPEWOUNDCORE3ń4INCHOD
Figure 6.26.
10 *6)
12 Ω
HEATER
ρ
Figure 6.27. Snubbing For a Resistive Load
s
+ 100 Vńms
R
L
Vstep
ǒdV
Ǔ
dt
c
VPK
+ 5 Vńms
dv
dt
V/μs
Ω
MHY
V
V
0.75
15
0.1
170
191
86
0.03
0
39.8
170
325
4.0
0.04
10.6
28.1
120
225
3.3
0.06
13.5
17.3
74
136
2.6
Figure 6.28. Snubber For a Variable Load
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AN1048/D
EXAMPLES OF SNUBBER DESIGNS
Table 2 describes snubber RC values for
1
ǒdV
Ǔ.
dt
s
80 A RMS
Figures 31 and 32 show possible R and C values for a 5.0
ǒ dt Ǔ
V/μs dV
c
assuming a pure inductive load.
40 A
0.1
dV
Designs
dt
(E = 340 V, Vpeak = 500 V, ρ = 0.3)
20 A
5.0 V/μs
L
μH
C
μF
47
100
220
500
1000
3.0
50 V/μs
R
Ohm
C
μF
11
0.33
0.15
0.068
0.033
C S ( μ F)
Table 2. Static
100 V/μs
R
Ohm
10
22
51
100
C
μF
R
Ohm
0.15
0.1
0.033
0.015
10
20
47
110
5A
0.01
0.001
0
R S (OHMS)
5A
40 A
80 A
100
10
0
0.1
ǒ
0.2
0.3
0.4
0.5
0.6
0.7
DAMPING FACTOR
0.8
0.9
1
Ǔ
0.4
0.5
0.6
0.7
DAMPING FACTOR
0.8
0.9
1
Ǔ
PURE INDUCTIVE LOAD, V + 120 V RMS,
I RRM + 0
ǒ Ǔ
causes a high dV step when series inductance is added to the
PURE INDUCTIVE LOAD, V + 120 V RMS,
I RRM + 0
ǒ Ǔ
0.3
The natural frequencies and impedances of indoor ac
wiring result in damped oscillatory surges with typical frequencies ranging from 30 kHz to 1.5 MHz. Surge amplitude depends on both the wiring and the source of surge
energy. Disturbances tend to die out at locations far away
from the source. Spark-over (6.0 kV in indoor ac wiring)
sets the maximum voltage when transient suppressors are
not present. Transients closer to the service entrance or in
heavy wiring have higher amplitudes, longer durations, and
more damping because of the lower inductance at those
locations.
The simple CRL snubber is a low pass filter attenuating
frequencies above its natural resonance. A steady state
sinusoidal input voltage results in a sine wave output at the
same frequency. With no snubber resistor, the rate of roll
off approaches 12 dB per octave. The corner frequency is at
the snubber’s natural resonance. If the damping factor is
low, the response peaks at this frequency. The snubber
resistor degrades filter characteristics introducing an
up-turn at ω = 1 / (RC). The roll-off approaches 6.0
dB/octave at frequencies above this. Inductance in the
snubber resistor further reduces the roll-off rate.
Figure 32 describes the frequency response of the circuit
in Figure 27. Figure 31 gives the theoretical response to a
3.0 kV 100 kHz ring-wave. The snubber reduces the peak
voltage across the thyristor. However, the fast rise input
2.5 A
20 A
0.2
Figure 6.30. Snubber Capacitor For dV = 5.0 V/μs
dt c
10K
10 A
0.1
ǒ
Transients arise internally from normal circuit operation
or externally from the environment. The latter is particularly frustrating because the transient characteristics are
undefined. A statistical description applies. Greater or
smaller stresses are possible. Long duration high voltage
transients are much less probable than those of lower
amplitude and higher frequency. Environments with infrequent lightning and load switching see transient voltages
below 3.0 kV.
1000
2.5 A
0.6 A
TRANSIENT AND NOISE SUPPRESSION
0.6 A RMS
10 A
dt
snubber resistor. Limiting the input voltage with a transient
suppressor reduces the step.
Figure 6.29. Snubber Resistor For dV
= 5.0 V/μs
dt c
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AN1048/D
VMT (VOLTS)
2‐1
400
In Figure 32, there is a separate suppressor across each
thyristor. The load impedance limits the surge energy delivered from the line. This allows the use of a smaller device
but omits load protection. This arrangement protects each
thyristor when its load is a possible transient source.
WITHOUT 5 μHY
WITH 5 μHY AND
450 V MOV
AT AC INPUT
0
WITH 5 μHY
-400
0
1
2
3
4
5
6
TIME (μs)
Figure 6.31. Theoretical Response of Figure 33 Circuit
to 3.0 kV IEEE 587 Ring Wave (RSC = 27.5 Ω)
VMAX
+10
Figure 6.33. Limiting Line Voltage
VOLTAGE GAIN (dB)
0
-10
100 μH
-20
Vin
-30
-40
10K
WITH 5 μHY
5 μH
10
12
Vout
0.33 μF
WITHOUT 5μHY
100K
FREQUENCY (Hz)
Figure 6.32. Snubber Frequency Response
1M
ǒ Ǔ
V out
V in
Figure 6.34. Limiting Thyristor Voltage
It is desirable to place the suppression device directly
across the source of transient energy to prevent the induction of energy into other circuits. However, there is no
protection for energy injected between the load and its controlling thyristor. Placing the suppressor directly across
each thyristor positively limits maximum voltage and snub-
The noise induced into a circuit is proportional to dV
dt
dI
when coupling is by stray capacitance, and
when the
dt
coupling is by mutual inductance. Best suppression
requires the use of a voltage limiting device along with a
rate limiting CRL snubber.
The thyristor is best protected by preventing turn-on
ber discharge dI .
dt
from dV or breakover. The circuit should be designed for
dt
EXAMPLES OF SNUBBER APPLICATIONS
defines the maximum input voltage and dI through the load.
In Figure 35, TRIACs switch a 3 phase motor on and off
and reverse its rotation. Each TRIAC pair functions as a
SPDT switch. The turn-on of one TRIAC applies the differential voltage between line phases across the blocking
device without the benefit of the motor impedance to
constrain the rate of voltage rise. The inductors are added to
what can happen instead of what normally occurs.
In Figure 30, a MOV connected across the line protects
many parallel circuit branches and their loads. The MOV
dt
dV
With the snubber, it sets the maximum
and peak voltage
dt
across the thyristor. The MOV must be large because there
is little surge limiting impedance to prevent its burn-out.
prevent static dV firing and a line-to-line short.
dt
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AN1048/D
SNUBBER
φ1
2
1
100 μH
G
300
4
22 Ω
2W
WIREWOUND
MOC
3081
91
6
0.15
μF
FWD
SNUBBER
1
G
300
4
MOC
3081
91
6
1/3 HP
208 V
3 PHASE
REV
SNUBBER
φ2
2
SNUBBER
ALL MOV’S ARE 275
VRMS
ALL TRIACS ARE
BTA08−8003W3G
91
G
1
1
6
100 μH
G
300
4
MOC
3081
91
6
MOC
3081
2
4
FWD
43
SNUBBER
2
1
G
300
6
φ3
MOC
3081
91
4
REV
N
Figure 6.35. 3 Phase Reversing Motor
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SNUBBER
2
AN1048/D
Figure 36 shows a split phase capacitor-run motor with
reversing accomplished by switching the capacitor in series
with one or the other winding. The forward and reverse
TRIACs function as a SPDT switch. Reversing the motor
applies the voltage on the capacitor abruptly across the
blocking thyristor. Again, the inductor L is added to prevent
ǒdV
Ǔ
dt
s
less dV capability than similar non-sensitive devices. A
dt
non-sensitive thyristor should be used for high dV .
dt
dV
TRIAC commutating
ratings are 5 to 20 times less
dt
dV
ratings.
than static
dt
firing of the blocking TRIAC. If turn-on occurs, the
forward and reverse TRIACs short the capacitors (Cs)
resulting in damage to them. It is wise to add the resistor RS
to limit the discharge current.
SNUBBER INDUCTOR
D1
D2
120 VAC
OR
240 VAC
REV
0.1
91
91
FWD
0.1
RS
CS
D3
D4
240 V
0
500 μH 5.6
120 V
MOTOR
1/70 HP
0.26 A
RS
115
+
-
RL
3.75
LS 330 V
46 V/μs
MAX
C1
G
C2
+
-
CS
2N6073
Figure 6.37. Tap Changer For Dual Voltage
Switching Power Supply
Phase controllable optocouplers have lower dV ratings
dt
Figure 6.36. Split Phase Reversing Motor
than zero crossing optocouplers and power TRIACs. These
should be used when a dc voltage component is present, or
to prevent turn-on delay.
Figure 37 shows a “tap changer.” This circuit allows the
operation of switching power supplies from a 120 or 240
vac line. When the TRIAC is on, the circuit functions as a
conventional voltage doubler with diodes D1 and D2 conducting on alternate half-cycles. In this mode of operation,
Zero crossing optocouplers have more dV capability than
dt
power thyristors; and they should be used in place of phase
controllable devices in static switching applications.
inrush current and dI are hazards to TRIAC reliability.
APPENDIX A
dt
ǒ dt Ǔ
MEASURING dV
Series impedance is necessary to prevent damage to the
TRIAC.
The TRIAC is off when the circuit is not doubling. In this
state, the TRIAC sees the difference between the line voltage and the voltage at the intersection of C1 and C2. Tran-
ǒ dt Ǔ
sients on the line cause dV
s
s
Figure 38 shows a test circuit for measuring the static dV
dt
of power thyristors. A 1000 volt FET switch insures that the
voltage across the device under test (D.U.T.) rises rapidly
from zero. A differential preamp allows the use of a
N-channel device while keeping the storage scope chassis
at ground for safety purposes. The rate of voltage rise is
adjusted by a variable RC time constant. The charging
resistance is low to avoid waveform distortion because of
the thyristor’s self-capacitance but is large enough to pre-
firing of the TRIAC. High
inrush current, dI, and overvoltage damage to the filter
dt
capacitor are possibilities. Prevention requires the addition
of a RC snubber across the TRIAC and an inductor in series
with the line.
vent damage to the D.U.T. from turn-on dI. Mounting the
dt
THYRISTOR TYPES
miniature range switches, capacitors, and G-K network
close to the device under test reduces stray inductance and
allows testing at more than 10 kV/μs.
Sensitive gate thyristors are easy to turn-on because of
their low trigger current requirements. However, they have
http://onsemi.com
17
AN1048/D
27
VDRM/VRRM SELECT
2W
1000
10 WATT
WIREWOUND
2
X100 PROBE
DUT
DIFFERENTIAL
PREAMP
G
X100 PROBE
20 k
2W
0.33 1000 V
0.047
1000 V
1
RGK
470 pF
dV
dt
VERNIER
MOUNT DUT ON
TEMPERATURE CONTROLLED
Cμ PLATE
0.001
100
2W
0.005
82
2W
1 MEG
0.01
2W
POWER
0.047
1N914
TEST
0.1
MTP1N100
20 V
f = 10 Hz
PW = 100 μs
50 Ω PULSE
GENERATOR
2 W EACH
1.2 MEG
0.47
56
2W
1000
1/4 W
0-1000 V
10 mA
1N967A
18 V
ALL COMPONENTS ARE NON‐INDUCTIVE UNLESS OTHERWISE SHOWN
Figure 6.38. Circuit For Static dV Measurement of Power Thyristors
dt
APPENDIX B
ǒ dt Ǔ
MEASURING dV
Commercial chokes simplify the construction of the necessary inductors. Their inductance should be adjusted by
increasing the air gap in the core. Removal of the magnetic
pole piece reduces inductance by 4 to 6 but extends the current without saturation.
The load capacitor consists of a parallel bank of 1500
Vdc non-polar units, with individual bleeders mounted at
each capacitor for safety purposes.
An optional adjustable voltage clamp prevents TRIAC
breakdown.
c
A test fixture to measure commutating dV is shown in
dt
Figure 39. It is a capacitor discharge circuit with the load
series resonant. The single pulse test aids temperature control and allows the use of lower power components. The
limited energy in the load capacitor reduces burn and shock
hazards. The conventional load and snubber circuit provides recovery and damping behaviors like those in the
application.
The voltage across the load capacitor triggers the D.U.T.
It terminates the gate current when the load capacitor voltage crosses zero and the TRIAC current is at its peak.
Each VDRM, ITM combination requires different components. Calculate their values using the equations given in
Figure 39.
ǒ dt Ǔ , synchronize the storage scope on the
To measure dV
c
current waveform and verify the proper current amplitude
and period. Increase the initial voltage on the capacitor to
compensate for losses within the coil if necessary. Adjust
the snubber until the device fails to turn off after the first
half-cycle. Inspect the rate of voltage rise at the fastest
passing condition.
http://onsemi.com
18
AN1048/D
HG = W AT LOW
+ CLAMP
- CLAMP
TRIAD C30X
50 H, 3500 Ω
910 k
2N3906
51
dV
dt
SYNC
ǒ
CL +
-
6.2 MEG
2N3904
150 k
2W
Q3
-5
PEARSON
301 X
+5
360
1/2 W
360
1/2 W
2N3906
2W
51
2
CASE
CONTROLLED
HEATSINK
G
56
2 WATT
1
2W -5
2.2 k
1/2
Ip T
I PK
+
W 0 V Ci
2 p V Ci
TRIAC
UNDER
TEST
LL +
1k
-
270 k
L
+
W0 +
2N3906
Q1
Q3
0.22
V Ci
2
+ T
W 0 I PK
4 p 2C
Figure 6.39.
1k
2N3904
1N5343
7.5 V
I
ǸLL
ǒdIdtǓ
c
+ 6f I PK
0.22
270 k
Ǔ
10 *6
Ańms
ǒdV
Ǔ Test Circuit For Power TRIACs
dt
c
http://onsemi.com
19
Q1
MR760
2.2 M
2W
MR760
+
6.2 MEG
2N3906
0.1
2N3904
+5
62 μF
1 kV
2N3904
0.1
CS
2.2 M
2.2 M
1/2 W
120
910 k
2W
Q1
2.2 M
120
1/2 W
0.01
2N3906
0‐1 kV 20 mA
2W
2N3904
0.01
CAPACITOR DECADE 1-10 μF, 0.01-1 μF, 100 pF- 0.01 μF
51 k
RS
Q3
2W
MR760
C L (NON‐POLAR)
51 k
2W
RL
LL
2.2 M, 2W
2.2 M, 2W
NON‐INDUCTIVE
RESISTOR DECADE
0-10 k, 1 Ω STEP
LD10‐1000‐1000
+ 1.5 kV
- 70 mA
AN1048/D
APPENDIX C
dV DERIVATIONS
dt
CONSTANTS (depending on the damping factor):
DEFINITIONS
2.1 No Damping (ρ + 0)
w + w0
RT + a + ρ + 0
1.0 R T + R L ) R S + Total Resistance
2.2 Underdamped (0 t ρ t 1)
RS
1.1 M +
RT
Ǹ
w + w0 2 * a 2 + w0
+ Snubber Divider Ratio
2.3 Critical Damped (ρ + 1)
a + w0, w + 0, R + 2
1
+ Undamped Natural Frequency
ǸL CS
1.2 w0 +
w + Damped Natural Frequency
1.3 a +
RT
2L
1.4 χ 2 +
1.6 ρ +
2.4 Overdamped (ρ u 1)
Ǹ
w + a 2 * w0 2 + w0
+ Wave Decrement Factor
3.0 i (S) +
ǸCL + Initial Current Factor
ǸCL + wa0 + Damping Factor
2
RT
0
RT
L
L
t=0
RS
I
e
CS
INITIALCONDITIONS
I + I RRM
VC + 0
S
ǒ Ǔ
+ V OL
2
a RT
Ǹρ2 * 1
RL
E RL
1.8 c + I *
L
CS
dV + Initial instantaneous dV at t + 0, ignoring
dt 0
dt
any initial instantaneous voltage step at
t + 0 because of I RRM
ǒdV
Ǔ
dt
C+
S V 0 L* c
EńL)SI
; e +E *
S
RT
RT
S 2)
) 1
S) 1
S 2)S
L
L
LC
LC
1.7 V 0 + E * R S I + Initial Voltage drop at t + 0
L
across the load
1.9
ǸCL ,
Laplace transforms for the current and voltage in Figure 40
are:
1ń2 LI2
Initial Energy In Inductor
+
2
Final
Energy In Capacitor
1ń2 CV
1.5 χ + I
E
Ǹ1 * ρ2
Figure 6.40. Equivalent Circuit for Load and Snubber
The inverse laplace transform for each of the conditions
gives:
UNDERDAMPED (Typical Snubber Design)
) c. For all damping conditions
4.0 e + E * V 0
ǒ Ǔ
L
ƪCos (wt) * wa
sin (wt)ƫe * at )
c
*at
w sin (wt) e
E RS
2.0 When I + 0, dV +
dt 0
L
dV
+ Maximum instantaneous dV
dt max
dt
ǒ Ǔ
ƪ
ƫ
(w 2 * a 2)
4.1 de + V0 2a Cos (wt) )
sin (wt) e−at)
w
L
dt
tmax + Time of maximum instantaneous dV
dt
tpeak + Time of maximum instantaneous peak
voltage across thyristor
c ƪ Cos (wt) * a sin (wt) ƫ e −at
w
Average dV + V PKń tPK + Slope of the secant line
dt
from t + 0 through V PK
4.2
V PK + Maximum instantaneous voltage across the
thyristor.
ȱ
ȳ
2a V0 L ) c
1 tan*1 *
t PK + w
ȧ
ȧ
ȧ
2
2
caȧ
Ǔ
V 0 ǒw *a
*
wȴ
Ȳ L w
When M + 0, R S + 0, I + 0 : w t PK + p
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20
AN1048/D
Ǹ
6.3 V PK + E * ƪ V0 (1−a t PK)−c tPK ƫ e−a t PK
L
2
2
2
4.3 V PK + E ) a * a tPK w0 V0 L ) 2ac V0 L) c
w0
When I + 0, R L + 0, M + 1:
4.4
V PK
E
V PK
6.4 Average dV +
tPK
dt
+ (1 ) e * a t PK)
When I + 0, R S + 0, M + 0
e(t) rises asymptotically to E. t PK and average dV
dt
do not exist.
V PK
Average dV +
t PK
dt
1 ATN
4.5 t max + w
4.6
ƪ
w (2ac * V0 (w 2 * 3a 2))
L
V0 (a 3 * 3aw 2) ) c(a 2 * w 2)
L
ƫ
3aV0 ) 2c
L
a 2V0 ) ac
L
When I + 0, t max + 0
RS
y3ń4,
For
RT
+ dV
then dV
dt 0
dt max
6.5 t max +
ǒdV
Ǔ +ǸV0L2 w02) 2ac V0L ) c2 e−atmax
dt max
ǒ Ǔ
NO DAMPING
5.0 e + E (1 * Cos (w0t)) )
I sin (w t)
0
C w0
5.1
de + E w sin (w t) ) I Cos (w t)
0
0
0
dt
C
5.2
ǒ Ǔ
5.3 t PK +
ǒCEIw0Ǔ
Ǹ
E2 )
I2
w 0 2C 2
OVERDAMPED
V PK
ǒdV
Ǔ
+
t
dt AVG
1.0 i +
PK
ƪ
ǒ
ǒdV
Ǔ
dt
max
+ I
C
1.1 i PK + VC
S
ǸE2w02 C2)I2 + w0E when I+0
2.0 i +
de + ƪ a V
*at
O L (2 * at) ) c(1 * at) ƫe
dt
6.2 t PK +
VC
S te −at
LS
VC
S
2.1 i PK + 0.736
RS
c
2 V 0L
a)
LS
CRITICAL DAMPED
6.0 e + E * V0 (1 * at)e *at ) cte *at
L
2)
CS
1 tanh −1 ƪwƫ
1.2 t PK + w
a
CRITICAL DAMPING
6.1
VC
S a −at sinh (wt)
w LS
Ǹ
Ǔƫ + w10 p2 when I + 0
w0 EC
5.6 t max + 1 tan *1
w0
I
5.7
max
APPENDIX D
SNUBBER DISCHARGE dI DERIVATIONS
dt
w0
5.4 V PK + E )
ǒdV
Ǔ
dt
+ ƪa V0 (2−a t max) ) c (1−a t max) ƫe −a t max
L
dV + I + 0 when I + 0
dt 0
C
p * tan *1
5.5
6.6
c
V0
L
1
2.2 t PK + a
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21
e −a t
PK
AN1048/D
UNDERDAMPED
VC
S e −at sin (wt)
3.0 i +
w LS
3.1 i PK + VC
S
Ǹ
CS
LS
NO DAMPING
4.0 i +
e −a t
PK
VC
S sin (wt)
w LS
4.1 i PK + VC
S
1 tan −1 ǒwǓ
3.2 t PK + w
a
Ǹ
CS
LS
4.2 t PK + p
2w
RS
LS
t=0
VC
S
CS
i
INITIALCONDITIONS :
i + 0, V C + INITIALVOLTAGE
S
Figure 6.41. Equivalent Circuit for Snubber Discharge
BIBLIOGRAPHY
Bird, B. M. and K. G. King. An Introduction To Power
Electronics. John Wiley & Sons, 1983, pp. 250−281.
Kervin, Doug. “The MOC3011 and MOC3021,” EB-101,
Motorola Inc., 1982.
Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976.
McMurray, William. “Optimum Snubbers For Power
Semiconductors,” IEEE Transactions On Industry Applications, Vol. IA-8, September/October 1972.
Gempe, Horst. “Applications of Zero Voltage Crossing
Optically Isolated TRIAC Drivers,” AN982, Motorola Inc.,
1987.
“Guide for Surge Withstand Capability (SWC) Tests,”
ANSI 337.90A-1974, IEEE Std 472−1974.
Rice, L. R. “Why R-C Networks And Which One For Your
Converter,” Westinghouse Tech Tips 5-2.
“IEEE Guide for Surge Voltages in Low-Voltage AC Power
Circuits,” ANSI/IEEE C62.41-1980, IEEE Std 587−1980.
“Saturable Reactor For Increasing Turn-On Switching
Capability,” SCR Manual Sixth Edition, General Electric,
1979.
Ikeda, Shigeru and Tsuneo Araki. “The dI Capability of
dt
Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8,
August 1967.
Zell, H. P. “Design Chart For Capacitor-Discharge Pulse
Circuits,” EDN Magazine, June 10, 1968.
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