SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 FEATURES D 2-MHz High Frequency Oscillator with 1-MHz D D D D D D D D D APPLICATIONS D High Output Current (50-A to 100-A) Operation Per Channel Matched Internal Slope Compensation Circuits Programmable Maximum Duty Cycle Clamp 60% to 90% Per Channel Peak Current Mode Control with Cycle-by-Cycle Current Limit Current Sense Discharge Transistor for Improved Noise Immunity Accurate Line Under and Over-Voltage Sense with Programmable Hysteresis Opto-Coupler Interface 110-V Internal Start-Up JFET (UCC28221) Operates from 12-V Supply (UCC28220) Programmable Soft-Start D D D Converters Maximum Power Density Designs High Efficiency 48-V Input with Low Output Ripple Converters High Power Offline, Telecom and Datacom Power Supplies DESCRIPTION The UCC28220 and UCC28221 are a family of BiCMOS interleaved dual channel PWM controllers. Peak current mode control is used to ensure current sharing between the two channels. A precise maximum duty cycle clamp can be set to any value between 60% and 90% duty cycle per channel. UCC28220 has an UVLO turn-on threshold of 10 V for use in 12-V supplies while UCC28221 has a turn-on threshold of 13 V for systems needing wider UVLO hysteresis. Both have 8-V turn-off thresholds. TYPICAL APPLICATION VIN (+48V) CS1 UCC28221 1 LINEOV VIN 16 Bias 2 LINE HYS LINEUV 15 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 VOUT 1/2 UCC27324 6 CS2 GND 11 7 SS CHG 10 CS2 REF 8 CTRL DISCHG 9 1/2 UCC27324 E/A NOTE: Pin 16 is a no connect (N/C) on UCC28220 which does not include the JFET option. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ Copyright 2004, Texas Instruments Incorporated www.ti.com 1 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 DESCRIPTION (CONTINUED) Additional features include a programmable internal slope compensation with a special circuit which is used to ensure exactly the same slope is added to each channel and a high voltage 110-V internal JFET for easier startup for the wider hysteresis UCC28221 version. The UCC28220 is available in both 16-pin SOIC and low-profile TSSOP packages. The UCC28221 also comes in 16-pin SOIC package and a slightly larger 20-pin TSSOP package to allow for high voltage pin spacing to meet UL1950 creepage clearance safety requirements. ORDERING INFORMATION TEMPERATURE RANGE TA = TJ −40°C to +105°C 110-V HV JFET STARTUP CIRCUIT SOIC−16 (D) TSSOP-16 (PW) 10 V on / 8 V off NO UCC28220D UCC28220PW − 13 V on / 8 V off YES UCC28221D − UCC28221PW UVLO THRESHOLDS PACKAGED DEVICES TSSOP-20 (PW) NOTE: D (SOIC) and PW (TSSOP) packages are available taped and reeled. Add R suffix to device type, e.g. UCC28220DR or UCC28221PWR. The reel quanities are 2,500 devices per reel for D package and 2,000 devices per reel for the PW package. CONNECTION DIAGRAM UCC28220D, UCC28220PW and UCC28221D PACKAGE (TOP VIEW) LINEOV LINEHYS VDD CS1 SLOPE CS2 SS CTRL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 UCC28221PW PACKAGE (TOP VIEW) VIN (for UCC28221) N/C (for UCC28220) LINEUV REF OUT1 OUT2 GND CHG DISCHG 1 2 3 4 5 6 7 8 9 10 N/C LINEOV LINEHYS VDD CS1 SLOPE CS2 SS CTRL N/C 20 19 18 17 16 15 14 13 12 11 VIN N/C LINEUV REF OUT1 OUT2 GND CHG DISCHG N/C RECOMMENDED OPERATION CONDITIONS Parameter High voltage start-up input Supply voltage 2 www.ti.com Symbol Condition VIN VDD 36 V to 76 V 8 V to 14.5 V SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted)†} Parameter High voltage start-up input, VIN UCC2822X UNIT 110 V Supply voltage, VDD 15 V Output current (OUT1, OUT2) dc , IOUT(dc) ±10 mA OUT1/ OUT2 capacitive load 200 pF REF output current, IREF 10 mA Current sense inputs, CS1, CS2 −1.0 to 2.0 V Analog inputs (CHG, DISCHG, SLOPE, REF, CNTRL) −0.3 to 3.6 V Analog inputs (SS, LINEOV, LINEUV, LINEHYS) −0.3 to 7.0 V 400 mW Power dissipation at TA = 25°C (PW package) Power dissipation at TA = 25°C (D package) 650 mW Junction operating temperature, TJ −55 to 150 °C Storage temperature, Tstg −65 to 150 °C °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute−maximum−rated conditions for extended periods may affect device reliability. ‡ All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. Lead temperature (soldering, 10 sec.), Tsol 300 ELECTRICAL CHARACTERISTICS: VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to 105°C, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS 14 V Overall Section Operating VDD range 8 Quiescent current SS = 0 V, no switching, Fosc = 1 MHz 1.5 3 4 Operating current Outputs switching, Fosc = 1 MHz 1.6 3.5 6 mA Startup Section Startup current UCC28220 VDD < (UVLO−0.8) 200 Startup current UCC28221 VDD < (UVLO−0.8) 500 UVLO start threshold UCC28220 9.5 10 10.5 UVLO start threshold UCC28221 12.3 13 13.7 7.6 8 8.4 2 2.2 UVLO stop threshold UVLO hysteresis UCC28220 1.8 UVLO hysteresis UCC28221 4.8 5 5.2 JFET ON threshold SS = 0, outputs not switching, VDD decreasing 9.5 10 10.5 JFET ON threshold SS = 2 V,Cntrl = 2 V, output switching, VDD decreasing; same threshold as UVLO stop 7.6 8 8.4 High voltage JFET current VIN = 36 V to 76 V, VDD = 0 V 16 48 100 High voltage JFET current VIN = 36 V to 76 V, VDD = 10 V 4 16 40 High voltage JFET current VIN = 36 V to 76 V, VDD < UVLO 4 12 40 JFET leakage VIN = 36 V to 76 V, VDD = 14 V www.ti.com 100 A µA V V V mA µA 3 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS: VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to 105°C, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX 3.15 3.3 3.45 UNITS Reference Output voltage 8 V < VDD < 14 V, ILOAD=0 mA to −10 mA Output current Outputs not switching; CNTRL = 0 V Ouput short circuit current VREF = 0 V VREF UVLO Soft-Start 10 −40 −20 −10 mA 2.55 3 3.25 V SS charge current RCHG=10.2 kΩ, SS = 0 V −70 −100 −130 SS discharge current RCHG=10.2 kΩ, SS = 2 V 70 100 130 SS initial voltage LINEOV=2 V, LINEUV = 0 V 0.5 1 1.5 SS voltage at 0% dc Point at which output starts switching 0.5 1.2 1.8 75% 90% 100% 3 3.5 4 SS voltage ratio SS Max voltage LINEOV = 0 V, LINEUV = 2 V V mA µA A V V Oscillator and PWM Output frequency RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ 450 500 550 Oscillator frequency RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ 900 1000 1100 Output maximum duty cycle RCHG = 10.2 kΩ, RDISCHG = 10.2 kΩ, measured at OUT1 and OUT2 73% 75% 77% CHG voltage 2 2.5 3 DISCHG voltage 2 2.5 3 140 200 260 0% 10% kHz % V Slope Compensation Slope RSLOPE = 75 kΩ, RCH = 66 kΩ, RDISCHG = 44 kΩ, Csx = 0 V to 0.5 V Channel matching RSLOPE = 75 kΩ, Csx = 0 V mV/us Current Sense CS1, CS2 bias current CS1 = 0, CS2 = 0 Prop delay CSx to OUTx CSx input 0 V to 1.5 V step −500 CS1, CS2 sink current CSx = 2 V 2.3 CNTRL Section Resistor ratio(1) 500 85 nA ns 4.5 7 mA 0.6 Ctrl input current CTRL = 0 V and 3.3 V Ctrl voltage at 0% dc CSx = 0 V, Point at which output starts switching (checks resistor ratio) NOTES: (1). Ensured by design. Not 100% tested in production. 4 0 40 www.ti.com −100 0 100 nA 0.5 1.2 1.8 V SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS: VDD = 12 V, 0.1-µF capacitor from VDD to GND, 0.1-µF capacitor from REF to GND, FOSC = 1 MHz, TA = −40°C to 105°C, TA = TJ, (unless otherwise noted). PARAMETER TEST CONDITION MIN TYP MAX UNITS Output Section (OUT1, OUT2) Low level IOUT = 10 mA IOUT = −10 mA, VREF – VOUT 0.4 1 High level 0.4 1 Rise time CLOAD = 50 pF 10 20 Fall time CLOAD = 50 pF 10 20 V ns LINE Sense section LINEOV threshold TA = 25°C TA =−40°C to 105°C 1.240 1.260 1.280 1.235 1.260 1.285 1.240 1.260 1.280 LINEUV threshold TA = 25°C TA =−40°C to 105°C 1.235 1.260 1.285 LINEHYST pull up voltage LINEOV = 2 V, LINEUV = 2 V 3.1 3.25 3.4 LINEHYST off leakage LINEOV = 0 V, LINEUV = 2 V −500 0 500 LINEHYS pull-up resistance I = −20 µA 100 500 LINEHYS pull-down resistance I = 20 µA 100 500 LINEOV, LINEUV bias I LINEOV = 1.25 V, LINEUV = 1.25 V LINEOV threshold LINEUV threshold −500 500 V nA Ω nA NOTES: (1). Ensured by design. Not 100% tested in production. www.ti.com 5 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 FUNCTIONAL BLOCK DIAGRAM REF RUN REFERENCE 14 16 VIN (N/C on UCC28220) UVLO/ JFET CONTROL P2 CHG 10 T OSC DISCHG 9 CLK1 Q FF + 4 VDD CLK2 Q CS1 3 CLK1 + S Q LATCH R 0.5 V VREF 13 OUT1 Q RUN 11 SLOPE COMPENSATION 0.5 V 6 + CS2 CLK2 + S Q LATCH R GND VREF 12 OUT2 Q RUN SLOPE 5 CTRL 8 + + − 20 kΩ 1 LINEOV 30 kΩ 1 pF LINE OV/UV 2 LINEHYS 15 LINEUV Soft−Start SS 7 RUN NOTE: Pinout for 16 pin option shown. See the 20-pin connection to UCC28221PW in the Terminal Functions table on the next page. 6 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 Terminal Functions TERMINAL PIN NUMBER FUNCTION NAME I/O 2 LINEOV I Input for line over voltage comparator 2 3 LINEHYS I Sets line comparator hysteresis 3 4 VDD I Device supply input 4 4 5 CS1 I Channel 1 current sense input 5 5 6 SLOPE I Sets slope compensation 6 6 7 CS2 I Channel 2 current sense input 7 7 8 SS I Soft-start input 8 8 9 CTRL I Feedback control input 9 9 12 DISCHG I Sets oscillator discharge current 10 10 13 CHG I Sets oscillator charge current 11 11 14 GND − Device ground 12 12 15 OUT2 O PWM output from channel 2 13 13 16 OUT1 O PWM output from channel 1 14 14 17 REF O Reference voltage output 15 15 18 LINEUV I Input for line under voltage comparator − 16 20 VIN I High voltage start-up input 16 − 1, 10, 11, 19 N/C − No connection UCC28220D UCC28220PW UCC28221D UCC28221PW 1 1 2 3 PIN DESCRIPTIONS VDD: This is used to supply power to the device, monitoring this pin is a the UVLO circuit. This is used to insure glitch-free startup operation. Until VDD reaches its UVLO threshold, it remains in a low power mode, drawing approximately 150 µA of current and forcing pins, SS, CS1, CS2, OUT1, and OUT2 to logic 0 states. If the VDD falls below 8 V after reaching turn-on, it will go back into this low power state. In the case of the UCC28221, the UVLO threshold is 13 V. It is 10 V for the UCC28220. Both versions have a turn-off threshold of 8 V. VIN (UCC28221 only): This pin has an internal high voltage JFET used for startup. The drain is connected to VIN, while its’ source is connected to VDD. During startup, this JFET delivers 12 mA typically with a minimum of 4 mA to VDD, which in turn, charges up the VDD bypass capacitor. When VDD gets to 13 V, the JFET is turned off. CS1 and CS2: These 2 pins are the current sense inputs to the device. The signals are internally level shifted by 0.5 V before the signal gets to the PWM comparator. Internally the slope compensation ramp is added to this signal. The linear operating range on this input is 0 to 1.5 V. Also, this pin gets pulled to ground each time its respective output goes low. (ie: OUT1 and OUT2). SLOPE: This pin sets up a current used for the slope compensation ramp. A resistor to ground sets up a current, which is internally divided by 25 and then applied to an internal 10-pF capacitor. Under normal operation th dc voltage on this pin is 2.5 V.. SS: A capacitor to ground sets up the soft-start time for the open loop soft-start function. The source and sink current from this pin is equal to 3/7th of the oscillator charge current set by the resistor on the CHG pin. The soft start capacitor is held low during UVLO and during a Line OV or UV condition. Once an OV or UV fault occurs, the soft-start capacitor is discharged by a current equal to its charging current. The capacitor does NOT quickly discharge during faults. In this way, the controller has the ability to recover quickly from very short line transients. This pin can also be used as an Enable/Disable function. www.ti.com 7 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 CHG: A resistor from this pin to GND sets up the charging current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the DISCHG pin is used to set up the operating frequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V. DISCHG: A resistor from this pin to GND sets up the discharge current of the internal CT capacitor used in the oscillator. This resistor, in conjunction with the resistor on the CHG pin is used to set up the operating frequency and maximum duty cycle. Under normal operation the dc voltage on this pin is 2.5 V. OUT1 and OUT2: These output buffers are intended to interface with high current MOSFET drivers. The output drive capability is approximately 33 mA and has an output impedance of 100 Ω. The outputs swing between GND and REF. LINEOV: This pin is connected to a comparator and used to monitor the line voltage for an over voltage condition. The typical threshold is 1.26 V. LINEUV: This pin is connected to a comparator and used to monitor the line voltage for an under voltage condition. The typical threshold is 1.26 V. LINEHYST: This pin is controlled by both the LINEOV and LINEUV pins. It is used to control the hysteresis values for both the over and under voltage line detectors. REF: REF is a 3.3-V output used primarily as a source for the output buffers and other internal circuits. It is protected from accidental shorts to ground. For improved noise immunity it is recommended that the reference pin be bypassed with a minimum of 0.1 µF of capacitance to GND. APPLICATION INFORMATION General The device is comprised of several housekeeping blocks as well as two slope compensated PWM channels that are interleaved. The circuit is intended to run from an external VDD supply voltage between 8 V and 14 V, however, the UCC28221 has the addition of a high voltage startup JFET with control circuitry which can be used for system startup. Other functions contained in the device are supply UVLO, 3.3-V reference, accurate line OV and UV functions, a high speed programmable oscillator for both frequency and duty cycle, programmable slope compensation, and programmable soft start functions. The UCC28220/1 is a primary side controller for a two channel interleaved power converter. The device is compatible with forward or flyback converters as long as a duty cycle clamp between 60 and 90 percent is required. The active clamp forward and flyback converters as well as the RCD and resonant reset forward converters are therefore compatible with this device. To ensure the two channels share the total converter output current, current mode control with internal slope compensation is used. Slope compensation is user programmable via a dedicated pin and can be set over a 50:1 range, ensuring good small-signal stability over a wide range of applications. 8 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION LINE Over Voltage and Under Voltage Three pins are provided to turn-off the output drivers and reset the soft-start capacitor when the converter input voltage is outside a prescribed range. The under-voltage set point and under-voltage hysteresis are accurately set via external resistors. The over-voltage set point is also accurately set via a resistor ratio, but the hysteresis is fixed by the same resistor that sets the u*nder-voltage hysteresis. Figure 1 and 2 show detailed functional diagram and operation of the under voltage lockout (UVLO) and over-voltage lockout (OVLO) features. The equations for setting the thresholds defined in Figure 2 are: V1 + 1.26 R1 ) 1.26 (R2 ) R3) (1) V2 + 1.26 (R1 ) Rx) , where Rx + R4 Ŧ (R2 ) R3) Rx (2) V4 + 1.26 (R1 ) R2 ) R3) R3 (3) ǒR1 Ǔ R4 (4) V3 + V4 * 1.26 The UVLO hysteresis and the OVLO hysteresis can then be calculated as V2 − V1 and V4 − V3, respectively. By examining the design equations it becomes apparent that the value of R4 sets the amount of hysteresis at both thresholds. By realizing this fact, the designer can then set the value of R4 based on the most critical hysteresis specification either at high line or at low line. In most designs the value of R4 will be determined by the desired amount of hysteresis around the UVLO threshold. As an example consider a telecom power supply with the following input UVLO and OVLO design specifications: • • • • V1 = 32.0 V V2 = 34.0 V V3 = 83.0 V V4 = 84.7 V Then, • • • R1 = 976 kΩ R2 = 24.9 kΩ R3 = 15.0 kΩ and • R4 = 604 kΩ www.ti.com 9 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION Input Voltage R1 UV 15 + 1.26 V 1.26 V + S1 OPEN HYS 2 R4 S2 CLOSED LINE_GOOD R2 OV 1 + R3 1.26 V Figure 1. Line UVLO and OVLO Functional Diagram ENABLE LINE_GOOD OFF V1 V2 V3 V4 Figure 2. Line UVLO and OVLO Operation VDD Because the driver output impedance is high the energy storage requirements on the VDD capacitor is low. For improved noise immunity it is recommended that the VDD pin, be bypassed with a minimum of 0.1 µF of capacitance to GND. In most typical applications the bias voltage for the MOSFET drivers will also be used as the VDD supply voltage for the chip. In the aforementioned applications it is beneficial to add a low valued resistor between the bulk storage capacitor of the driver and the VDD capacitor for the UCC28220/1. By adding a resistor in series with the bias supply any noise that is present on the bias supply will be filtered out before getting to the VDD pin of the controller. 10 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION Reference For improved noise immunity it is recommended that the reference pin, REF, be bypassed with a minimum of 0.1uF of capacitance to GND. Oscillator Operation and Maximum Duty Cycle Setpoint The oscillator uses an internal capacitor to generate the time base for both PWM channels. The oscillator is programmable over a 200 kHz to 2MHz frequency range with 20% to 80% maximum duty cycle range. Both the dead time and the frequency of the oscillator are divided by 2 to generate the PWM clock and off-time information for each of the outputs. In this way, a 20% oscillator duty cycle corresponds to a 60% maximum duty cycle at each output, where an 80% oscillator duty cycle yields a 90% duty cycle clamp at each output. The design equations for the oscillator and maximum duty cycle set point are given by: F OSC + 2 F OUT D MAX(osc) + 1 * 2 R CHG + K OSC R DISCHG + K OSC (5) ǒ1 * DMAX(out)Ǔ (6) D MAX(osc) F OSC (7) ǒ1 * DMAX(osc)Ǔ F OSC (8) Where: • • • • • • • KOSC = 2.04 x 1010 [Ω/s] FOUT = Switching frequency at the outputs of the chip [Hz] DMAX(out) = Maximum duty cycle limit at the outputs of the chip DMAX(osc) = Maximum duty cycle of the Oscillator for the desired maximum duty cycle at the outputs FOSC = Oscillator frequency for desired output frequency [Hz] RCHG = External oscillator resistor which sets the charge current − [Ω] RDISCHG = External oscillator resistor which sets the discharge current − [Ω] Start-Up JFET Section A 110-V start-up JFET is included to start the device from a wide range (36 V−75 V) telecom input source. When VDD is lower than 13 V the JFET is on, behaving as a current source charging the bias capacitors on VDD and supplying current to the device. In this way, the VDD bypass capacitors are charged to 13 V where the outputs start switching and the JFET is turned off. To enable a constant bias supply to the device during a pulse skipping condition, the JFET is turned back on whenever VDD decreases below 10 V and the outputs are not switching. Thus, the current from the JFET can overcome the internal bias currents, as long as the device is not actively switching the output drivers. See Figure 2 below for a graphical representation of the JFET/VDD operation. The UCC28220 does not contain an internal JFET and has a startup threshold of 10 V which makes it capable of directly operating off a 12 V dc bus www.ti.com 11 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION VDD 13 V 13 V 8 − 14 V 10 V NORMAL OPERATION 8 V (UVLO off) 0V OUTx GATE DRV OFF ON ON HV JFET OFF Figure 3. JFET Device Operation with VDD Voltage Soft-Start A current is forced out of the SS pin, equal to 3/7 of the current set by RCHG, to provide a controlled ramp voltage. The current set by the RCHG resistor is equal to 2.5 V divided by RCHG. This ramp voltage overrides the commanded duty cycle on the CTRL pin, allowing a controlled start-up. Assuming the UCC28221 is biased on the primary side, the soft start should be quite quick to allow the secondary bias to be generated and the secondary side control can then take over. Once the soft-start time interval is complete, a closed loop soft-start on the secondary side can be executed. ISS + 3 7 2.5 R CHG (9) where, ISS = current which is sourced out of the SS pin during the soft-start time − [Amps] Current Sense The current sense signals CS1 and CS2 are level shifted by 0.5 V and have the slope compensation ramps added to them before being compared to the control voltage at the input of the PMW comparators. The amplitude of the current sense signal at full load should be selected such that it is very close to the maximum control voltage in order to limit the peak output current during short circuit operation. Output Drivers The UCC28220/1 is intended to interface with the UCC27323/4/5 family of MOSFET drivers. As such, the output drive capability is low, effectively 100 Ω and the driver outputs swing between GND and REF. 12 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION Slope Compensation The slope compensation circuit in the UCC28220/1 operates on a cycle-by-cycle basis. The two channels have separate slope compensation circuits. These are fabricated in precisely the same way so as current sharing is unaffected by the slope compensation circuit. For each channel, an internal capacitor is reset whenever that channel’s output is off. At the beginning of the PWM cycle, a current is mirrored off the SLOPE pin into the capacitor, developing an independent ramp. Since the two channel’s ramps will start when the channel’s output changes from a low to high state, the ramps are thus interleaved. These internal ramps are added to the voltages on the current sense pins, CS1 and CS2 and the result forms an input to the PWM comparators. REF SLOPE (5) 2.5/(25*R_SLOPE) = I_SC R_SLOPE CTRL (8) PWM − + + TO RESET of PWM LATCH 0.5V C_SC OUT 1 ON S1 10 pF OFF CS1 (4) S2 Figure 4. Slope Compensation Detail for Channel 1. Duplicate Matched Circuitry Exists for Channel 2. To ensure stability, the slope compensation circuit must add between 1/5 and 1 times the inductor downslope to each of the current sense signals prior to being applied to the PWM comparator’s input. www.ti.com 13 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION Determining the value for the slope compensation resistor: Design Example: NCT(p) = 1 VOUT = 12 LOUT = 3.2 x 10 −6 NCT(s) = 50 Np = 7 RSENSE = 5.23 Ns = 5 VEA(cl) = 1.98 FS(out) = 500000 Where, • • • • • • • • • NCT(p) = Number of primary turns on the Current Transformer − [Turns] NCT(s) = Number of Secondary turns on the current transformer − [Turns] VOUT = Nominal output voltage of the converter − [V] LOUT = Inductance value of each output inductor − [H] NP = Number of primary turns on the main transformer − [Turns] NS = Number of secondary turns on the main transformer − [Turns] RSENSE = Value of current sense resistor on secondary of current sense transformer − [Ohms] VEA(cl) = Maximum Value of the E/A output voltage − [Volts] FS(out) = Switching frequency of each output − [Hz] Determine the correct value for the slope resistor, RSLOPE, to provide the desired amount of slope compensation. N CT + N CT(p) N CT(s) , Current Transformer Turns Ratio 1. Transform the Secondary Inductor Downslope to the Primary S L(prime) + V OUT L OUT Ns , Np S L(prime) + 2.679 Ańms 2. Calculate the Transformed Slope Voltage at Sense Resistor: VS L(prime) + S L(prime) N CT R SENSE, VS L(prime) + 2.281 Vńms 3. Calculate the RSLOPE value to give a compensating ramp equal to the transformed slope voltage given above.: M + 1.0 Desired ratio between the compensating ramp and the output inductor downslope ramp, transformed to the primary sense resistor R SLOPE + 14 ǒM 10 4 VS L(prime) Ǔ 10 *6 , R SLOPE + 35.556 kW www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 TYPICAL APPLICATION CIRCUITS VIN CS1 UCC28221 1 OV VIN 16 2 HYS UV 15 3 VDD REF 14 Bias VOUT 1/2 UCC27424 4 CS1 OUT1 13 5 SLOPE OUT2 12 CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL DISCHG 9 1/2 UCC27424 REF E/A Figure 5. Interleaved Flyback Application Circuit Using the UCC28221 www.ti.com 15 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 VIN CS1 UCC28220 1 OV 2 HYS UV 15 3 VDD REF 14 4 CS1 OUT1 13 5 SLOPE OUT2 12 N/C 16 Bias 1/2 UCC27424 VOUT CS2 6 CS2 GND 11 7 SS CHG 10 8 CTRL 1/2 UCC27424 DISCHG 9 E/A Figure 6. Interleaved Boost Application Circuit Using the UCC28220 16 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs SUPPLY VOLTAGE UVLO THRESHOLDS vs TEMPERATURE 4.0 13.5 3.5 11.5 UCC28220 UVLO on threshold and UCC28221 JFET on threshold (when not switching) 10.5 9.5 8.5 UCC28221 EXCLUDES JFET CURRENT 3.0 2.5 2.0 1.5 1.0 UCC28220 and UCC28221 UVLO off threshold and UCC28221 JFET on threshold (when switching) 0.5 7.5 0.0 −50 −25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 VDD − Supply Voltage − V Tj − Temperature − °C Figure 7 Figure 8 SUPPLY CURRENT vs SUPPLY VOLTAGE REFERENCE VOLTAGE vs TEMPERATURE 3.45 30 VIN = 36 V 3.40 VREF − ReferenceVoltage − V 20 IDD − Supply Current − mA UCC28221 12.5 UCC28220 IDD − Quiescent Current − mA VUVLO − UVLO Thresholds− V UCC28221 UVLO on threshold UCC28221 10 0 −10 −20 −30 3.35 3.30 No Load 3.25 Load 3.20 −40 JFET source current 3.15 −50 0 2 4 6 8 10 12 14 16 −50 −25 0 25 50 75 100 125 Tj − Temperature − °C VDD − Supply Voltage − V Figure 9 Figure 10 www.ti.com 17 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS LINEOV AND LINEUV THRESHOLDS vs TEMPERATURE SLOPE COMPENSATION vs TEMPERATURE 1.270 230 225 LINEOV 1.260 Vth − Trip Threshold − V SLOPE − Slope Compensation − mV per µs 1.265 1.255 1.250 LINEUV 1.245 1.240 1.235 1.230 RSLOPE = 75 kΩ 220 215 210 205 CS1 = 0 V 200 195 190 CS1 = 0.5 V 185 180 175 170 −50 −25 0 25 50 75 100 125 −50 Tj − Temperature − °C −25 0.0 75 100 125 Figure 12 CHANNEL1 AND CHANNEL2 SLOPE MATCHING vs TEMPERATURE PROGRAMMING RESISTOR vs SLOPE COMPENSATION 10 106 8 6 4 105 Mismatch − % RSLOPE − Slope Programming Resistor − Ω 50 Tj − Temperature − °C Figure 11 2 0 RSLOPE = 75 kΩ CS0 = 0 V CS1 = 0 V −2 104 −4 −6 −8 −10 103 10 100 SLOPE − Slope Compensation − mV per µs 1000 −50 −25 0.0 25 50 Tj − Temperature − °C Figure 14 Figure 13 18 25 www.ti.com 75 100 125 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS RISE AND FALL TIME vs TEMPERATURE (CL = 50 pf) VOH AND VOL vs TEMPERATURE 1.0 0.9 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IOUT = 10 mA 0.8 VO -Output Voltage − V Tr and Tf − Rise and Fall Time − ns 20 19 18 17 Fall Time Rise Time 0.7 VREF − VOUT (VOH) 0.6 0.5 0.4 VOL 0.3 0.2 0.1 −50 −25 0 25 50 75 100 0.0 125 −50 −25 0 25 50 75 Tj − Temperature − °C Tj − Temperature − °C Figure 15 100 125 Figure 16 SOFTSTART DISCHARGE CURRENT vs TEMPERATURE SOFTSTART CHARGE CURRENT vs TEMPERATURE 130 −70 120 −80 ISSdis − Charge Current − µA ISSCH − Charge Current − µA RCHG = 10.2 kΩ −90 −100 −110 110 100 90 −120 80 −130 70 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 Tj − Temperature − °C Tj − Temperature − °C Figure 18 Figure 17 www.ti.com 19 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS PROGRAMMING RESISTORS vs SWITCHING FREQUENCY OSCILLATOR FREQUENCY vs TEMPERATURE 1M 550 RCHRG = RDISRG = 10.2 kΩ 530 RCHRG = RDISRG DMAX = 75% 100K fS - Oscillator Frequency − kHz RCHRG RDISRG − Resistance − Ω 540 10K 1K 520 510 500 490 480 470 460 450 10K 100K 1M 10M −50 fS - Switching Frequency − Hz −25 0 25 50 75 100 125 Tj − Temperature − °C Figure 19 Figure 20 CSx to OUTx delay vs CSx Peak Voltage PROGRAMMABLE MAX DUTY CYCLE vs TEMPERATURE 100 77 90 CSx to OUTx delay − ns RCHRG = RDISRG = 10.2 kΩ DC − Duty Cycle − % 76 75 105°C 80 70 60 25°C 50 −40°C 40 30 74 20 10 0 73 −50 −25 0 25 50 75 100 125 Tj − Temperature − °C 0.2 0.4 0.6 0.8 1.0 1.2 CSx − Peak Voltage − V Figure 22 Figure 21 20 0 www.ti.com 1.4 1.6 1.8 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 APPLICATION INFORMATION Related Products DEVICE DESCRIPTION PACKAGE OPTION UCC27323/4/5 Dual 4-A High Speed Low Side MOSFET Drivers SOIC-8, PowerPAD MSOP-8, PDIP-8 UCC27423/4/5 Dual 4-A High Speed Low Side MOSFET Drivers with Enable SOIC-8, PowerPAD MSOP-8, PDIP-8 TPS2811/12/13 Dual 2.4-A High Speed Low Side MOSFET Drivers SOIC-8, TSSOP-8, PDIP-8 UC3714/15 Dual 2.4-A High Speed Low Side MOSFET Drivers SOIC-8, PowerSOIC-14, PDIP-8 References and Resources: An evaluation module and an associated user’s guide are available. The UCC28221 is used in a two-channel interleaved Forward design converting from 36-V to 76-V dc input voltage to a regulated 12-V dc output. The power module has two isolated 100 W forward power stages operating at 500 kHz, which are operating 180 degrees out of phase with each other allowing for output current ripple cancellation and smaller magnetic design. This design also takes advantage of the UCC28221’s on-board 110-V internal JFET start up circuit that removes the need of an external trickle charge resistor for boot strapping. This circuit turns off after auxiliary power is supplied to the device conserving power. D Evaluation Module, UCC28221EVM, 48 VIN, 12 VOUT, 200-W Interleaved Forward Converter D User’s Guide, UCC28221 Evaluation Module, Texas Instruments Literature Number SLUU173 www.ti.com 21 SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 MECHANICAL DATA D (R-PDSO-G**) PACKAGE PLASTIC SMALL-OUTLINE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°− 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012 22 www.ti.com SLUS544A − SEPTEMBER 2003 − REVISED AUGUST 2004 MECHANICAL DATA PW (R-PDSO-G**) PACKAGE PLASTIC SMALL-OUTLINE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°−ā 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 www.ti.com 23 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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