AND8281/D Implementing the NCP1605 to Drive the PFC Stage of a 19 V / 8 A Power Supply Prepared by: Joel Turchi ON Semiconductor http://onsemi.com APPLICATION NOTE Forward or half−bridge converters take a significant advantage of a narrow input voltage range. In such applications, the PFC stage is wished to start first and to keep on as long as the power supply is plugged in. Optimally, the downstream converter should turn on when the output of the PFC stage is nominal. In other words, the PFC must be the master… The NCP1605 is specially designed for these applications. It features a “pfcOK” pin to enable the downstream converter when the PFC stage is ready for operation. Practically, it is in high state when the PFC stage is in steady state and low otherwise (fault or start−up condition). In addition, the PFC stage having to still remain active in light load conditions, the NCP1605 integrates the skip cycle capability to lower the stand−by losses to a minimum. Rbo1 Rout2 This application note shows how to design a NCP1605 PFC driven. The dimensioning criteria / equations are presented in a general manner but for the sake of clarity, this process is illustrated in the following practical application: • Ac line range: 90 V up to 265 V • Output Voltage: 19 V / 8 A • IEC61000−3−2 Class D compliant The power supply consists of two stages: • A PFC pre−converter driven by the NCP1605 • The main power supply: 2 switches forward driven by the NCP1217A, 133 kHz Vout Rout1 Cbo Rovp1 Rbo2 CVctrl Rzcd AC Line EMI Filter Rocp Ct 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Rovp2 Icoil + CVCC Icoil L1 Rdelay D1 Vout Cdelay VCC CVref M1 LOAD pfcOK Cosc Cin Vin VCC Rdrv Cbulk + Rcs Figure 1. Generic Application Schematic The “pfcOK” signal enables the downstream converter when the PFC is ready © Semiconductor Components Industries, LLC, 2007 January, 2007 − Rev. 0 1 Publication Order Number: AND8281/D AND8281/D Introduction The NCP1605 is a PFC driver designed to operate in fixed frequency, Discontinuous Conduction Mode (DCM). In the most stressful conditions, Critical Conduction Mode (CRM) can be achieved without power factor degradation and the circuit could be viewed as a CRM controller with a frequency clamp (given by the oscillator). Finally, the NCP1605 tends to give the best of both modes without their respective drawbacks. Furthermore, the circuit incorporates protection features for a rugged operation together with some special circuitry to lower the power consumed by the PFC stage in no load conditions. More generally, the NCP1605 functions make it the ideal candidate in systems where cost−effectiveness, reliability, low stand−by power and high power factor are the key parameters: • Compactness and Flexibility: the controller requires few external components while offering a large variety of functions. Depending on the selected coil and oscillator frequency you select, the circuit can: 1. Mostly operate in Critical Conduction Mode and use the oscillator as a frequency clamp. 2. Mostly operate in fixed frequency mode and only run in CRM at high load and low line. 3. Permanently operate in fixed frequency mode (DCM). In all cases, the circuit provides near−unity power factor. • Skip−cycle Capability for Low Power Stand−by: among other applications, the circuit targets power supply where the PFC stage must keep alive even in stand−by. A continuous flow of pulses is not compatible with no−load standby power requirements. Instead, the controller slices the switching pattern in bunch of pulses to drastically reduce the overall losses. The skip cycle operation is initiated by applying to pin 1, a signal that goes below 300 mV in stand−by. Typically, this signal is drawn from the feed−back of the downstream converter. • Start−up Current Source and Large VCC Range: meeting low stand−by power specifications represents a difficult exercise when the controller requires an external, lossy resistor connected to the bulk capacitor. The controller disables the high−voltage current source after start−up which no longer hampers the consumption in no−load situations. In addition, the large VCC range (10 V to 20 V after start−up), highly eases the circuit biasing. • Fast Line / Load Transient Compensation: given the low bandwidth of the regulation block, the output voltage of PFC stages may exhibit excessive over and under−shoots because of abrupt load or input voltage variations (e.g. at start−up). If the output voltage is too far from the regulation level: • • • − The NCP1605 disables the drive to stop delivering power as long as the output voltage exceeds the over voltage protection (OVP) level. − The NCP1605 drastically speeds up the regulation loop when the output voltage is below 95.5% of its regulation level. This function is allowed only after the PFC stage has started up not to eliminate the soft−start effect. PFC OK: the circuit detects when the circuit is in normal situation or if on the contrary, it is in a start−up or fault condition. In the first case, pin12 is in high state and low otherwise. Pin12 serves to control the down− stream converter operation in response to the PFC state. Safety Protections: the NCP1605 permanently monitors the input and output voltages, the coil current and the die temperature to protect the system from possible over−stresses and make the PFC stage extremely robust and reliable. In addition to the aforementioned OVP protection, one can list: − Maximum Current Limit and Zero Current Detection: the circuit permanently senses the coil current and immediately turns off the power switch if it is higher than the set current limit. It also prevents any turn on of the power switch as long as some current flows through the coil, to ensure operation in discontinuous conduction mode. This feature also protects the MOSFET from the excessive stress that could result from the large in−rush currents that occurs during the start−up phases. − Under−Voltage Protection: the circuit turns off when it detects that the output voltage goes below 12% of the OVP level (typically). This feature protects the PFC stage from starting operation in case of too low ac line conditions or in case of a failure in the OVP monitoring network (e.g., bad connection). − Brown−Out Detection: the circuit detects too low ac line conditions and stop operating in this case. This protection protects the PFC stage from the excessive stress that could damage it in such conditions. − Thermal Shutdown: an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150°C typically. The circuit resumes operation once the temperature drops below about 100°C (50°C hysteresis). Output Stage Totem Pole: the NCP1605 incorporates a −0.5 A / +0.8 A gate driver to efficiently drive most TO220 or TO247 power MOSFETs. http://onsemi.com 2 AND8281/D Design of the PFC Stage Hence the total current cycle time is: Power Components T cycle + T on ) T demag + The selection of the oscillator frequency is a prerequisite step before dimensioning the PFC stage. For this application, we choose to clamp the switching frequency at around 130 kHz because this frequency is generally a good trade−off when considering the following aspects: • A high switching frequency reduces the size of the storage elements. In particular, it is well known that the higher the switching frequency, the lower the transformer core. That is why, one should set the switching frequency as high as possible, • On the other hand, increasing the switching frequency has two major drawbacks: L @ I coil,max @ V out V in,pk @ (V out * V in,pk) L u T osc @ T on + V in (eq. 5) 4 @ P IN,AVG @ V out in,pk Hence, L u 7.5 @ 127 2 @ (390 * 127) mH + 107 mH 4 @ 190 @ 390 In order to have a significant margin, a 150 mH coil is selected. As in the most stressful conditions, the PFC stage operates in CRM, the rms and peak coil currents are calculated as they would be computed with a full CRM circuit. • Maximum Peak Current: I coil,max + 2 @ Ǹ2 @ (P IN,AVG) max (eq. 6) V IN,rms,LL • RMS Coil Current: (P IN,AVG) max I coil,rms + 2 @ Ǹ3 V IN,rms,LL (eq. 7) Finally, the coil specification is: • L = 150 mH • Icoil,max = 6.0 A • Icoil,rms = 2.5 A (eq. 1) MOSFET and Diode Selection The following equation gives the MOSFET conduction losses (refer to the AND8123 application note available at http://www.onsemi.com/pub/Collateral/AND8123−D.PDF for further information): ǒ Ǔƪ ƫ 2 P in,av 8 @ Ǹ2 @ V in,rms 4 (eq. 8) p on + @ R dsON @ @ 1− 3 V in,rms 3p @ V out (eq. 2) The demagnetization time is: T demag + V in,pk 2 @ (V out * V in,pk) • Vout = 390 V • PIN,AVG = 190 W (80% global efficiency) The coil current ramps up to its peak value during the MOSFET on−time and then ramps down to zero during the diode conduction period (coil demagnetization time). In CRM, this cycle time must be longer than the oscillator period. The on−time duration is: L @ I coil,pk (eq. 4) In our application, • Tosc = 7.5 ms (133 kHz) •V = 127 V ( Ǹ2 @ 90 V) The coil is selected so that CRM operation is achieved in the most stressful conditions (full power, low line). In other words, its inductance must be large enough not to have dead−times at least at the top of the sine−wave. In CRM, the coil peak current is: P in,av u T osc Substitution of equation (1) into inequation (4) leads to: Coil Selection V in,rms (eq. 3) The necessity of having a cycle time longer than the oscillator period when at low line, the coil current is maximal, leads to: − The switching rate increasing, the associated losses grow up. In addition, all parasitic capacitors charge at a higher frequency and generate more heat… − EMI filtering is tougher: the switching generates high EMI rays at the switching frequency and close harmonic levels. Most power supplies have to meet the CISPR22 standard that applies to frequencies above 150 kHz. That is why SMPS designers often select FSW = 130 kHz so that the fundamental keeps below 150 kHz and then out of the regulation scope. Often, 65 kHz is also chosen to not to have to damp harmonic 2 too. The oscillator frequency will then be set to approximately 130 kHz. I coil,max + 2 @ Ǹ2 @ L @ I coil,pk @ V out V in @ (V out * V in) Hence, the losses are maximal at low line and full load. In our application, we can evaluate them as follows: L @ Icoil,pk V out * V in ǒ Ǔ (p on)max + 4 @ R dsON @ 190 90 3 http://onsemi.com 3 2 ƪ @ 1* ƫ 8 @ Ǹ2 @ 90 ^ 4.3 @ R dsON (eq. 9) 3p @ 390 AND8281/D Bulk Capacitor In our application, we use a MOSFET that according to the data sheet, exhibits a 0.4 W on−time resistance at 150°C. Hence: (P on)max ^ 1.7 W The main criteria / constraints in the bulk capacitor choice are generally: 1. Peak to peak Low Frequency Ripple: (eq. 10) The switching losses are more difficult to compute. As a rule of the thumb, we generally reserve a loss budget equal to that of the conduction ones. One can anyway note that the NCP1605 limits this source of dissipation by clamping the switching frequency (that can never exceed the oscillator one – 133 kHz in our case). To further improve the efficiency, the MOSFET opening can be accelerated using the schematic of Figure 2, where the Q2 npn transistor (TO92) amplifies the MOSFET turn off gate current. (dV OUT) pk*pk + h @ (P IN,AVG) max (eq. 11) C BULK @ w @ V OUT,nom where ω is the ac line angular frequency. This ripple must typically keep lower than 5% of the output voltage. This leads to: C BULK w 94% @ 190 + 37 mF 5% @ 2p @ 100 @ 390 2 (eq. 12) 2. Hold−up time specification: DRV (pin10) R12 D2 1N4148 47 R13 2.2 Q2 BC369 M1 PFC MOSFET C BULK w R10 10 k h @ (P IN,AVG) max @ tHOLD*UP V OUT,nom 2 * V OUT,min 2 . (eq. 13) Hence, a 10 ms hold−up time imposes: C BULK w 94% @ 2190 @ 102 m ^ 65 mF 390 * 350 Figure 2. Q2 Makes Steeper the Turn Off I C,rms + (eq. 14) 3. RMS capacitor Current: Ǹƪ ƫ ǒ Ǔ P IN,AVG 2 h PFC @ P IN,AVG 32 @ Ǹ2 @ * 9p V IN,rms @ V OUT,nom V OUT,nom 2 (eq. 15) We will consider that hPFC (hPFC is the PFC efficiency) is 94% in the most severe conditions where this rms current is maximal (low line, full load). Finally: I C,rms + Ǹƪ ƫ 2 32 @ Ǹ2 @ 190 * 94% @ 190 9p 90 @ 390 390 ǒ Ǔ 2 ^ Ǹ1.646 * 0.210 ^ 1.2 A (eq. 16) Oscillator Frequency Setting The oscillator frequency is given by the following formula: f OSC + 840 pF @ 60 kHz C pin8 ) 20 pF C pin8 + 359 pF Instead, a normalized 330 pF capacitor is chosen that leads to a 140 kHz frequency. (eq. 17) Brown−out Circuitry Hence, the pin8 capacitor must be selected in accordance to the following expression: C pin8 + 840 pF @ 60 kHz * 20 pF fOSC The brown−out terminal (pin2) receives a portion of the PFC input voltage (VIN). As during the PFC operation, VIN is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a portion of the (VIN) average value is applied to the brown−out pin. (eq. 18) In our application, we target 130 kHz, then: Vin AC Line Rbo1 EMI Filter Cin Rcs (eq. 19) 1 V/0.5 V BO Rbo2 Cbo2 Figure 3. Brown−out Block “BO_NOK” disables the NCP1605 drive when high. http://onsemi.com 4 + − BO_NOK AND8281/D As sketched by Figure 3, a portion of the average input voltage should be applied to pin2. The NCP1605 incorporates a comparator to monitor Vpin2 and inhibits the circuit when this voltage is lower than the internal brown−out threshold. More specifically, the internal comparator features a 50% hysteresis (VBOL = 50% VBOH) to take into account the change in the input voltage average level: 1. Before operation, the PFC stage is off and the input bridge acts as a peak detector (refer to Figure 4). As a consequence, the input voltage is approximately flat and nearly equates the ac line amplitude. Hence, the voltage applied to pin 2 is: V pin2 + Ǹ2 @ V in,rms @ The PFC can start operation when Vpin2 exceeds “VBOH” that is about 1 V. 2. After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to pin2 is: V pin2 + 2 @ Ǹ2 @ V in,rms Rbo2 , p Rbo1 ) Rbo2 i.e., about 64% of the previous value. Therefore, the same line magnitude leads to a Vpin2 voltage that is 36% lower when the PFC is working than when it is off. The PFC stops operating if this Vpin2 level goes below “VBOL” that is 0.5 V typically. Rbo2 . Rbo1 ) Rbo2 Figure 4. Typical Input Voltage of a PFC Stage Computation of Rbo1, Rbo2, Cbo2: In our case, 90 Vrms being the low level of our specification, let’s take 85 Vrms to have some headroom. Hence, following the aforementioned procedure: Rbo1 and Rbo2 should be selected so that Vpin2 is 1 V at the lowest line voltage at which the PFC stage is allowed to start operation. Hence: Rbo2 @ Ǹ2 @ V in,rms,LL + 1 ³ Rbo1 ) Rbo2 Rbo1 + Ǹ2 @ V in,rms,LL * 1 Rbo2 Rbo2 + 56 kW Rbo1 + 56 k @ Ǹ2 @ 85 ^ 6732 kW Cbo + 220 nF (eq. 20) Practically, four 1.8 MW are placed in series for Rbo1 (for safety reasons it is preferable to have several series resistors when applied to a high voltage rail), what leads to Rbo1 = 7200 kW instead of 6732 kW. Rbo2 is increased in the same ratio to 62 kW so that finally, the BO thresholds are: Rbo2 is generally chosen in the range of 50 kW to minimize the leakage current to about 10 mA at low line. The capacitor Cbo2 must be high enough to make Vpin2 a dc voltage proportional to the line average value. Practically, select: [(Rbo1//Rbo2) ⋅ Cbo] in the range of half a line period. (V in,rms) BO_H + Rbo1 ) Rbo2 @ 1 V + 83 V (eq. 21) Ǹ2 Rbo2 Rbo1 ) Rbo2 p @ 0.5 V (V in,rms) BO_L + @ + 0.78 @ (V in,rms) BO_H + 65 V (eq. 22) Rbo2 2 @ Ǹ2 When a brown−out condition is detected, the signal “BO_NOK” turns off the circuit (refer to block diagram of the NCP1605 data sheet). Remark: the calculated (VIN,RMS)BO−L is computed assuming that the voltage applied to the BO pin is a dc voltage devoid of ripple. In practice, the (Rbo1, Rbo2, Cbo2) network does not fully integrate the 100 or 120 Hz ripple of the rectified input rail so that the BO signal actually consists of some ac component that is superimposed to its dc voltage. These variations of the BO voltage make Vpin2 go to lower voltages at a given line amplitude and thus, make the BO comparator trigger at a higher line magnitude. The larger ripple, the higher (VIN,RMS)BO−L. In other words, Cbo2 can be adjusted to set the wished (VIN,RMS)BO−L. Feed−back Network The NCP1605 embeds a trans−conductance error amplifier that typically features a 200 mS trans−conductance gain and a ±20 mA maximum capability. The output voltage of the PFC stage is externally scaled down by a resistors divider and monitored by the feed−back input (pin4). The bias current is minimized (less than 500 nA) to allow the use of a high impedance feed−back network. The output of the error amplifier is pinned out for external loop compensation (pin 3). http://onsemi.com 5 AND8281/D Vbulk (PFC Stage Output) Rfb1 pin4 − + Rfb2 to PWM Section + Vref 2.5 V pin3 Ccomp1 C2 Rcomp1 Figure 5. Regulation Trans−conductance Error Amplifier, Feed−back and Compensation Network Computation of the Feed−back / Regulation External Components In practice, we can choose: Rfb2 + 27 kW A resistor divider consisting of Rfb1 and Rfb2 of Figure 5 must provide pin4 with a voltage proportional to the PFC output voltage so that Vpin3 equates the internal reference voltage (VREF = 2.5 V) when the PFC output voltage is nominal. In other words: (instead of 25 kW, 27 kW being a normalized value) Finally, Rfb2 + 27 kW (eq. 23) ǒ V out,nom *1 V REF Ǔ (eq. 27) In our application, we target a regulation level around 390 V. Hence, Another constraint on the feed−back resistors is the power it dissipates. Rfb1 and Rfb2 being biased by the PFC output high voltage (in the range of 400 V typically), they can easily consume several hundreds of mW if their resistance is low. Targeting a bias current in the range of 100 mA generally gives a good trade−off between wasted energy and noise immunity. That means that: V REF + 25 kW 100 mA (eq. 26) Rfb1 + Rfb2 @ V out,nom Rfb2 @ V out,nom + V REF ³ Rfb1 + *1 Rfb2 V REF Rfb1 ) Rfb2 Rfb2 + (eq. 25) Rfb2 + 27 kW (eq. 28) ǒ Ǔ Rfb1 + 27 kW @ 390 * 1 + 4185 kW 2.5 (eq. 29) Like for the input voltage sensing network, several resistors should be placed in series instead of a single Rfb1 resistor. In our application, we choose a (1800 kW + 1800 kW + 560 kW = 4160 kW) network. This selection together with (Rfb2 = 27 kW) leads to: (eq. 24) V out,nom + Rfb1 ) Rfb2 @ V REF + 1800 k ) 1800 k ) 560 k ) 27 k @ 2.5 V + 387.7 V Rfb2 27 k (eq. 30) Compensation: The NCP1605 integrates the Follower Boost by making the charge current of the timing capacitor, a function of the squared output voltage. Based on the data−sheet equations and neglecting the zero resulting from the ESR of the bulk capacitor, a small signal analysis would lead to the following transfer function of the PFC stage: ǒ V OUT + Rfb1 ) Rfb2 V REGUL Rfb2 • • • • • Ǔ 2 @ C pin7 @ R LOAD @ V IN,RMS 2 120 m @ L @ V OUT 2 Where: CBULK is the bulk capacitor ROUT is the load equivalent resistance Cpin7 is the pin7 external capacitor L is the PFC coil inductance Rfb1 and Rfb2 are the feed−back resistors @ ƪ ǒ 1) s@ 1 R OUT @C BULK 4 Ǔƫ (eq. 31) • VREGUL is the internal signal that generated by the • regulation block modulates the MOSFET conduction time. RLOAD is the equivalent load resistance. http://onsemi.com 6 AND8281/D However, PFC stages must exhibit a very low regulation bandwidth, in the range of 20 Hz to yield high power factor ratios. Hence, sharp variations of the load generally result in excessive over and under−shoots. The NCP1605 limits over−shoots by the Over−Voltage Protection (see OVP section). To contain under−shoots, an internal comparator monitors the feed−back (Vpin4) and when Vpin4 is lower than 95.5% of its nominal value, it connects a 220 mA current source to speed−up the charge of the compensation capacitor (Cpin3). Finally, it is like if the comparator multiplied the error amplifier gain by about 10 (Note 1). The implementation of this dynamic response enhancer together with the accurate and programmable over−voltage protection, guarantees a reduced spread of the output voltage in all conditions included sharp line / load transients. Hence, in most applications, it is sufficient to place a low frequency pole that drastically limits the bandwidth. Practically, the compensation network can just consist of a capacitor in the range of 680 nF or 1 mF that is applied between pin3 and ground. Such a circuitry generates the following control characteristic: V REGUL R fb2 @ G EA + V OUT s @ 3 @ (R fb1 ) R fb2) @ C 2 (eq. 32) Where: • GEA is the trans−conductance gain of the error amplifier (200 mS, typically) • C2 is the compensation capacitor (see Figure 5) • Rfb1 and Rfb2 are the feedback resistors (see Figure 5) Hence, we have them the following pole: f p1 + 1 6p @ (R fb1)R fb2) R fb2@GEA (eq. 33) @ C2 In our case, we choose (C2 = 680 nF) which leads to a ȡ ȧ6p @ Ȣ 1 (4160 k)27 k) @ 680 27 k@200 m n ȣ ȧ Ȥ ^ 0.1 Hz corner frequency. 1. The circuit does not enable the under−shoots limitation function during the start−up sequence of the PFC stage but only once the converter has stabilized (that is when the “pfcOK” signal of the block diagram, is high). This is because, at the beginning of operation, the pin3 capacitor must charge slowly and gradually for a soft start−up. Current Sense Network Rdrv Vin Rzcd Icoil AC Line 6 EMI Filter VDD Cin D1 L1 CSout 100 mV ZCD + − VCC Current Mirror VDD Ics Ics M1 Output Buffer outON 10 DRV S Vzcd Rocp CSin RSENSE 5 LdT R Q Cbulk DT Ics > 250 mA ≥ OCP OCP (RESET of the PWM Latch) Figure 6. Current Sense Block The CS block performs the over−current protection and the zero current detection. null (refer to Figure 6). By inserting a resistor ROCP between the CS pin and RSENSE, we adjust the pin5 current as follows: The NCP1605 is designed to monitor a negative voltage proportional to the coil current. Practically, a current sense resistor (RSENSE of Figure 6) is inserted in the return path to generate a negative voltage proportional to the coil current. The circuit incorporates an operational amplifier that sources the current necessary to maintain the CS pin voltage * [R CSICOIL] ) [R OCPI pin5] + V pin5 [ 0 (eq. 34) Finally the pin5 current is proportional to the coil current as shown by the following equation: http://onsemi.com 7 AND8281/D I pin5 + R CS I R OCP COIL In practice, we will use (RSENSE = 0.1 W) and hence, since the maximum coil current is 6 A (see inductor computation): (eq. 35) In other words, the pin5 current is proportional to the coil current. The circuit uses Ipin5 to set the coil current limit (Over−Current Protection). Practically, if Ipin5 exceeds 250ĂmA, the PWM latch is reset for a cycle by cycle current limitation. Hence, the maximum coil current is: I COIL,MAX + R OCP 250 mA R SENSE R OCP + 0.1 @ Finally, the ratio (ROCP / RSENSE) sets the over−current limit in accordance with the following equation: (eq. 37) As we have two external components to set the current limit (ROCP and RSENSE), the current sense resistor can be optimized to have the best trade−off between losses and noise immunity. As shown in [1], the RSENSE losses are given by the following equation: PR SENSE + ǒ Ǔ P in,av 4 @ R SENSE @ 3 V in,rms 2 (eq. 38) 4 @ R SENSE @ 3 ǒ (P in,av)max (V in,rms) min Ǔ 2 (eq. 39) (eq. 40) I COIL,MAX (eq. 41) 250 mA R SENSE + 3 @ 0.25% @ 90 ^ 87 mW 4 175 2 (eq. 42) Vout (Bulk Voltage) Rout3 Rout2 1 FB 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 (eq. 45) R SENSE + 100 mW (eq. 46) R OCP + 2.4 kW (eq. 47) R ZCD + 7.2 kW (eq. 48) R DRV + 22 kW (eq. 49) The NCP1605 dedicates one specific pin for the under−voltage and over−voltage protections. The NCP1605 configuration allows the implementation of two separate feed−back networks (see Figure 8): • One for regulation applied to pin 4 (feed−back input). • Another one for the OVP function. In our application, we choose (a = 0.25%), Rout1 R DRV + 3 @ R ZCD Over−Voltage Protection And: R OCP + R SENSE @ (eq. 44) The propagation delay (Vpin6 lower than 100 mV) to (drive output high) has been minimized (120 ns typically) to help turn on at the valley of the MOSFET drain−source voltage. Finally: (V in,rms) min 2 R SENSE + 3 @ a @ 4 (P in,av) max R ZCD + 3 @ R OCP Finally, in our application, we use: One can choose RSENSE as a function of its relative impact on the PFC stage efficiency at low line and full power. If a is the relative percentage of the power that can be consumed by RSENSE, this criterion leads to: a @ (P in,av) max + (eq. 43) Please note that ROCP should not exceed 5 kW. If your calculation led to an excessive ROCP value, reduce RSENSE to meet the aforementioned requirement. The pin5 current is internally copied and sourced by pin6. Place a resistor (Rpin6) between pin6 and ground to build a voltage proportional to the coil current. The circuit detects the core reset when Vpin6 drops below 100 mV, typically. It is recommended to implement a zero current detection resistor on pin 6 (RZCD ) that is as high as possible but that does not exceed 3 times ROCP. In addition, a resistor is to be placed between the drive output (pin9) and pin6, to ease the circuit detection by creating some over−riding at the turn on instant. It should be 3 times the RZCD to cope with all possible VCC levels (VCC and hence, the drive amplitude can range from 8 to 20 V). (eq. 36) I COIL,MAX R OCP + R SENSE 250 mA 6 A + 2.4 kW 250 mA Vout (Bulk Voltage) HV 1 Rout1 OVP FB Rout2 Figure 7. Configuration with One Feed−back Network for Both OVP and Regulation 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 HV Rovp1 OVP Rovp2 Figure 8. Configuration with Two Separate Feed−back Networks http://onsemi.com 8 AND8281/D The double feed−back configuration offers some redundancy and hence, an up−graded safety level as it protects the PFC stage even if there is a failure of one of the two feed−back arrangements. However, the regulation and the OVP function have the same reference voltage (VREF = 2.5 V) so that if wished, one single feed−back arrangement is possible as portrayed by Figure 7. The regulation and OVP blocks having the same reference voltage, the resistance ratio Rout2 over Rout3 adjusts the OVP threshold. More specifically, − The bulk regulation voltage is: V OUT + Rout1 ) Rout2 ) Rout3 @ V REF Rout2 ) Rout3 1. high enough to limit the losses that if excessive, may not allow to comply with the stand−by requirements to be met by most power supplies 2. low enough for a good noise immunity Again, a bias current in the range of 100 mA generally gives a good trade−off. Hence: Rovp2 + (eq. 50) Rovp2 + 27 kW (eq. 51) (eq. 55) (eq. 56) ǒ Ǔ For safety reason, several resistors should be placed in series instead of a single Rovp1 one. In our application, we choose a (1800 kW + 1800 kW + 820 kW) network. This selection together with (Rovp2 = 27 kW) leads to: Rovp1 ) Rovp2 @ V REF + 1800 k ) 1800 k ) 820 k ) 27 k @ 2.5 V ^ 412 V (eq. 58) Rovp2 27 k C pin7 @ V REGUL @ V OUT,nom 2 @ 375 m @ L @ V OUT 2 C pin7 @ V REGUL @ V OUT,nom 2 750 m @ L @ V OUT 2 Ǔ Rovp1 + 27 kW @ 410 * 1 + 4401 kW (eq. 57) 2.5 Finally, since the maximum power is obtained when VREGUL is 1 V: (P IN,AVG) max + 2 @ V IN(t) (eq. 59) C pin7 @ V OUT,nom 2 750 m @ L @ V OUT 2 @ V IN,rms 2 (eq. 61) Now, as Where: − (VREGUL) is an internal signal linearly dependant of the output of the regulation block (VCONTROL). (VREGUL) varies between 0 and 1 V. − IIN(t) and VIN(t) are the instantaneous line current and voltage respectively. − L is the coil inductance − VOUT,nom is the output regulation voltage. This level is set to about 390 V typically. Equation (59) illustrates that as any voltage mode controller, the timing capacitor (CPIN7) adjusts the power. Multiplying IIN by VIN and averaging the result over the line period, the mean input power is deducted as follows: P IN,AVG + V OVP *1 V REF Rovp2 + 27 kW Maximum Power Adjustment From the data−sheet equations, we can deduct the following expression of the instantaneous line current that is absorbed by the PFC stage: I IN(t) + ǒ In our application, we target an OVP level in the range of 410 V. Hence, (eq. 52) For instance, (VOVP = 105% ⋅ VOUT) leads to the following constraint: (Rout3 = 5% ⋅ Rout2). As soon and as long as the circuit detects that the output voltage exceeds the OVP level, the power switch is turned off to stop the power delivery. In our application, the option that consists of two separate VOUT sensing networks is chosen (as sketched by Figure 8). Like for the regulation network, the impedance of the monitoring resistors must be: V OVP + (eq. 54) Rovp1 + Rovp2 @ − The ratio OVP level over regulation level is: V OVP + 1 ) Rout3 V OUT Rout2 (eq. 53) In practice, we can choose: Rovp2 = 27 kW (instead of 25 kW, 27 kW being a normalized value) Finally, − The OVP level is: V OVP + Rout1 ) Rout2 ) Rout3 @ V REF Rout2 V REF + 25 kW 100 mA V OUT,nom + R fb1 ) R fb2 @ V REF R fb2 where VREF is the regulation reference voltage (2.5 V) and Rfb1 and Rfb2 are the feed−back resistors as portrayed in Figure 5. Hence, the input power can be expressed as follows: ǒ Ǔ 2 C pin7 @ V REGUL V IN,rms 2 R ) R fb2 P IN,AVG+ fb1 @ @ (eq. 62) R fb2 120 m @ L V OUT 2 The maximum power is only dependent on the coil inductance, on the input voltage magnitude and on the Cpin7 capacitor. PIN,AVG is also a function of the output voltage square so that the power capability of the PFC stage increases while Vout decreases. This is what allows the @ V IN,rms 2 (eq. 60) http://onsemi.com 9 AND8281/D Follower Boost characteristic (see data sheet for more information on this mode). If this operation mode is not wished (as this is the case in our application), the timing capacitor (CPIN7) must be dimensioned so that the PFC stage can provide the full power at low line (VIN,RMS = [VIN,RMS]LL) under the nominal output voltage (VOUT = VOUT,nom). The maximum VREGUL value being 1 V, this leads to: C pin7 + 120 m @ L @ (P IN,AVG) max ǒ R )R fb1 R Ǔ 2 fb2 fb2 @ V OUT,nom 2 (V IN,RMS) LL 2 In our case, VCC and hence, the drive pulses’ amplitude is 15 V. The choice of (R2 =150 W) together with (R8 = 4700 W) leads to a 460 mV offset. The maximum pin7 swing that is 1 V without offset, is now: 540 mV that is 54% of its normal value. To allow the same maximum on−time, Cpin7 must be increased in response to this swing diminution as follows: C pin7 + 2.64 nF + 4.9 nF 54% (eq. 63) Finally, the following timing network is implemented: − Cpin7 = 4.7 nF − R2 = 150 W − R8 = 4.7 kW Noting that , V OUT,nom + R fb1 ) R fb2 @ V REF R fb2 Feeding Circuitry The NCP1605 must start first and allow the downstream converter to operate when the output voltage of the PFC stage is nominal. This is done as follows: • The NCP1605 start−up current source charges the VCC capacitor tank that is common to the two controllers (NCP1605 and NCP1217A). As the NCP1605 VCC start−up level is high (15 V typically while the NCP1217A starts to operate when its supply voltage exceeds 12.8 V typically), VCC is necessarily high enough to activate both drivers when the start−up current source turns off. • The circuitry of Figure 9 is implemented to power the two controllers after start−up. An auxiliary winding is added across the forward transformer (see Figure 9). The turn ratio is 1/14. The diode D15 rectifies the ac voltage seen by the auxiliary winding so that the capacitor C28 is substantially charged to (VBULK/14), i.e., about 28 V when the MOSFETs X31 and X24 are on. A low cost regulator consisting of Q7, R31, D9 and D8 steps down this voltage to provide both the NCP1605 and NCP1217A with a friendly voltage (around 15 V). This configuration that makes C28 store a significant amount of energy as soon as there is some activity in the forward side (C28 being charged up to almost 30 V), allows a robust powering of the controllers even in stand−by where they enter skip−cycle mode to reduce the losses. the above equation simplifies as follows: C pin7 + 120 m @ L @ V REF 2 @ (P IN,AVG) max (V IN,RMS) LL 2 (eq. 64) In our case, − L = 150 mH − (PIN,AVG)max = 190 W − (VIN,RMS)LL = 90 V − VREF = 2.5 V Hence: C pin7 + 120 m @ 150 m @ 2.5 2 @ 190 ^ 2.64 nF (90) 2 (eq. 66) (eq. 65) Offsetting the pin7 Pin… At high line, the PFC MOSFET on−time becomes very small and the circuit must be able to operate with low VCONTROL levels. At light load, these levels are particularly and make the circuit task very tough (the PWM comparator functions with very low inputs). To avoid excessive minimum on−times able to prevent the PFC stage to regulate when at high line and light load, skip mode is not activated, it is recommended to generate an offset on pin7 by placing a resistor R2 between Cpin7 and ground and forcing some voltage across R2 using the drive pulses (thanks to the resistor R8 of the application schematic). The offset should be as high as 400 or 500 mV. http://onsemi.com 10 AND8281/D Forward Primary Side Vbulk X31 IRF840 1N4934 D12 MUR160E R44 2.2 D15 C28 100 mF/50 V R31 10 k D13 MUR160E T2 Q7 BC368 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D9 16 V D8 1N4148 VCC To the NCP1217A VCC Pin NCP1605 X24 IRF840 R25 0.33/3 W C1 VCC Capacitor Figure 9. Feeding Circuitry Stand−by Management receive a voltage below 300 mV in light load conditions. Practically, a portion of the feedback signal of the downstream converter is applied to pin 1, as portrayed by Figure 10. The NCP1605 automatically skips switching cycles when the power demand drops below a given level. This is accomplished by monitoring the pin1 voltage that must PFC Stage Downstream Converter Rectified ac Line 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 HV + Downstream Converter Controller (NCP1217A) VCC NCP1605 R28 Stand−by Input Voltage C R18 Feed−back of the Downstream Converter Figure 10. Signal for Stand−by Detection A portion of the SMPS feedback is injected to pin1. In our application, R28 is 47 kW and R18 is 22 kW so that 30% of the SMPS feedback voltage is applied. In normal operation, the circuit controls the continuous absorption of the line current necessary for matching the load power demand. Instead, when the voltage applied to pin1 goes below 300 mV: − The output pulses are blanked and pin3 (“VCONTROL”) is grounded, − The output of the PFC stage being not fed any more, it drops. When the output voltage goes below 95.5% of http://onsemi.com 11 AND8281/D the regulation level, the circuit resumes operation until “FLAG1” becomes low (what means that the output voltage has exceeded the regulation level). − At that moment, if Vpin1 is still below 300 mV, a new skipping phase starts. In other words, instead of continuously providing the output with a small amount of power, the circuit operates from time to time at a higher power level. As an example and to make it simple, instead of continuously supplying 1% of PMAX, the circuit can provide the load with 10% of PMAX for 10% of the time. The IC enters the so−called skip cycle mode that is much more efficient compared to a continuous power flow as it drastically reduces the number of pulsations and therefore the switching losses associated to them. Figure 11 portrays this operation mode. Remarks: • This technique that is based on the monitoring of the downstream converter feed−back, makes the PFC stage enter the skip mode at a very stable power level over the input voltage range. • When in skip mode, each working phase of the PFC stage, starts smoothly as pin3 is grounded at the beginning of it. This soft−start capability is effective to avoid the audible noise that could possibly result from such a burst operation. Figure 11. Stand−by Management Control of the Downstream Converter (“pfcOK” Pin) − Incorrect feeding of the circuit (“UVLO” high when VCC < VCCOFF, VCCOFF equating 9 V typically). − Excessive die temperature detected by the thermal shutdown. − Under−Voltage Protection. − Too repetitive Over−Voltage conditions leading to the circuit shutdown (“STDWN” of the block diagram turns high). − A major fault has definitively latched off the circuit. And “pfcOK/REF5V” is high when the PFC output voltage is properly and safely regulated. The signal is intended to control the operation of the downstream converter. The signal “pfcOK/REF5V is high (5 V) when the PFC stage is in normal operation (its output voltage is stabilized at the nominal level) and low otherwise. More specifically, “pfcOK/REF5V” is low: • During the PFC stage start−up, that is, as long as the output voltage has not yet stabilized at the right level. • In case of a condition preventing the circuit from operating properly, i.e., during the VCC charge by the high voltage start−up current source, in brown−out conditions or when one of the following major faults sets the “Fault Latch” of the block diagram, causing the circuit turning off: http://onsemi.com 12 AND8281/D The signal “pfcOK” is low when the PFC stage is not in nominal operation (start−up, fault conditions) and high (5 V) when it is ok for operation. Vbulk R49 22 k D14 pfcOK The PFC controls the downstream converter activity thanks to the « pfcOK » signal: NCP1217A 1 8 2 7 3 6 4 5 − If ”pfcOK” is low, the NCP1217A feed−back is forced low by D14 and the forward does not operate − If ”pfcOK” is high, the NCP1217A feed−back is no more grounded and the forward is free to operate. Figure 12. Enabling / Disabling the Downstream Converter R49 is optional. It is implemented here as an additional pull− up resistor that increases the biasing current on the NCP1217A feed−back pin. D14 could be removed if a resistor R49 was implemented that is low impedance enough to disable the controller when “pfcOK” is in low state. Design of the Two−switch Forward The NCP1605 enables the two−switch forward when the PFC stage output is nominal. Therefore, its input voltage range is narrow. More specifically, we will consider that: − the minimum input voltage is 350 V (taking into account the 10 ms hold−up time) − the maximum one is 450 V We select the NCP1217A as the two−switch forward because it guarantees that the duty cycle cannot exceed 50%. Also, this compact and cost−effective circuit incorporates some stand−by management to keep the stand−by losses at a low level. Hence: NP t 42% @ 350 + 7.35 20 NS A 7 ratio is selected, that gives some margin. The magnetizing inductor is selected in order to minimize the (L @ Ipk 2 ). The choice of the output current ripple leads to a 800 mH inductor. Finally, a ETD39, ferrite core transformer is implemented. A third winding (auxiliary winding) is added for the VCC generation (see the “feeding circuitry” section). We choose (NP / NAUX = 14) so that the auxiliary winding provides about 28 V when the bulk voltage nominal. Finally, the transformer specification is: − LP = 800 mH − NP / NS = 7 − NP / NAUX = 14 − IP,RMS = 1,9 A − IP,MAX = 3 A − IS,RMS = 9.5 A − IS,MAX = 11 A Selection of the Magnetic Components and of the Output Capacitor: Two components are to be computed: • the forward transformer that transfers the energy from • the primary to the secondary side the output filtering coil that: − Adjusts the ripple of the output current. As a rule of the thumb, 70% of the maximum load current will be used as the peak to peak ripple. − In conjunction with the output capacitor filters the ac voltage provided by the transformer, to form the dc output voltage (19 V). (L.C) must be large enough to meet the ripple requirements of the 19 V output voltage. Design of the Output Filtering Network The criterion 1 (70% current ripple) leads to: DI COIL + 70% @ I LOAD,MAX + 70% @ 8 A + 5.6 A On the other hand: DI COIL + Forward Transformer Design Since the NCP1217A limits the duty−cycle at a level that can be as low as 42% (see data−sheet), the turn ratio of the forward transformer must selected so that the voltage it applies to the secondary side is high enough to provide 20 V (that is 19 V the output voltage + the diode voltage drop) when the bulk voltage is minimum (350 V). In other words: V BULKń7 V out ) V F @ @ 7.5 ms ³ L V BULKń7 ) V F L ^ 19 ) 1 @ 7.5 ms + 26 mH 5.6 Two parallel low ESR, 470 mF / 25 V capacitors are connected across the output to form the output (L, C) filter together with the 26 mH / 11 A inductor. NS @ V BULK,min u 20 V 42% NP http://onsemi.com 13 AND8281/D Application Schematics Vbulk + C2 100 mF/450 V D1 MUR460 VCC Vbulk M1 SPP20N60S R42 D3 C5 100 16 V 10 nF R11 R9 1800 k R14 1800 k R20 1800 k C30 R22 1800 k 1 nF R10 R13 2.2 1k R24 560 k 220 nF R21 27 k Q2 BC369 D2 1N4148 C17 pfcOK R23 820 k 10 k DRV1 R12 47 VCC R17 16 15 14 13 12 11 10 9 27 k R7 0.1 NCP1605 C14 1 nF stby 1 2 3 4 5 6 7 pin6 C6 T1x 150 mH (np/ns = 9) R16 R4 1800 k 1800 k C22 680 nF 220 mF R3 1800 k C4 VRramp C3 4.7 nF C37 1 nF VCC 8 330 pF R2 150 R6 C8 R1 1800 k 62 k 2.4 k pin6 220 nF R15 R58 R52 6.8 k 22 k DRV1 R8 4.7 k C1 Type = X2 VRramp 330 nF + − 100−265 VAC U1x KBU6K N C15 C12 2.2 nF Type = Y2 Earth C13 2.2 nF Type = Y2 CM1 330 nF Type = X2 Type = X2 CM2 150 mH opt. Figure 13. PFC Stage http://onsemi.com 14 C11 330 nF N F1 L AND8281/D Vout C29 19 V/8 A 470 mF C18 25 V SGND 470 mF 25 V C19 Vout R27 1 mF L1 22 mH 22 k R30 3.3 k C27 R35 470 pF 100/2 W R57 C23 1k 10 nF R29 3.3 k MBR20100CT D7 D13 MUR160E Vbulk T2 X31 SPP11N60 K = Np/Ns = 7; Np/Naux = 14 Vaux2 10 k D10 100 nF D15 1N4934 D12 10 k D20 16 V X25 C10 2.2 nF Type = Y2 R25 0.33/3 W Vz BC368 Q6 STRAP C32 100 nF BC368 Q5 R50 10 DRV2 C28 1N4148 Vz VCC 7 8 D9 R55 VCC 1 mF C20 C31 Vbulk 5 6 D5 3V0 Q1x BC846B 1 2 3 FB 220 mF Circuitry for Over−Load Protection 4 FB 1 nF R43 1k C34 6.8 k pfcOK PFC Skip−Mode Control C35 R49 D14 1N5817 1 nF C33 R46 1 nF 1k R1x 43 k NCP1217A 16 V C26 1 mF 10 k R39 47 D8 BC368 Q7 R56 0R BC369 Q1 R51 100 mF/50 V 10 k C16 2.2 nF Type = Y2 16 V R33 10 VCC R31 TL431 R38 MUR160E R40 10 2.2 SGND X24 SPP11N60 800 mH D18 R44 SFH615A−4 X30 FB R37 Vaux2 X29 D6 FB R18 R5 47 k 22 k stby 22 k Figure 14. Forward Stage http://onsemi.com 15 AND8281/D Bill of Materials CM1 CM CHOKE B82734−R2322−B30 EPCOS CM2 DM CHOKE WI−FI series − 150 mH Wurth Electronik C1, C11, C15 330 nF X2 Capacitor PHE840MY6330M RIFA C2 Bulk Cap. 100 mF / 450 V 222, 215, 937, 101 BC Components C3 CMS Capacitor 4.7 nF various C4 CMS Capacitor 330 pF various C5, C8, C17 CMS Capacitor 220 nF various C6, C31 Electrolytic Capacitor 220 mF / 25 V various C14, C33, C34, C35, C30, C37 CMS Capacitor 1 nF various C27 CMS Capacitor 470 pF various C21, C25, C12, C13 2.2 nF Y2 Capacitor DE2E3KH222MA3B muRata C18, C29 electrolytic Capacitor UPM1E471MPD Nichicon C19, C20 CMS Capacitor 1 mF various C22, C26 CMS Capacitor 680 nF various C23 CMS Capacitor 10 nF various C28 Electrolytic Capacitor 100 mF / 50 V various C32 CMS Capacitor 100nF various D10 Through Hole Ceramic Cap 100 nF various C38 CMS Capacitor 330 nF various D1 PFC Diode MUR460RLG ON Semiconductor D2, D8 DO−35 Diode 1N4148 various D14 Schottky Diode 1N5817 ON Semiconductor D3, D9 16 V Zener Diode 1N5930 ON Semiconductor D18, D20 16 V Zener Diode BZX84C16LT1, G ON Semiconductor D16 16 V Zener Diode BZX79−C3V0 ON Semiconductor D6, D7 Dual Schottky Diode MBR20100CT ON Semiconductor D12, D13 Demagnetization Diodes MUR160RLG ON Semiconductor D15 Rectifier 1N4934RLG ON Semiconductor HS1_M1, HS3_D6 Heatsink KL195/25.4SW Schaffner HS1_X31, HS2_X24 Heatsink KL194/25.4SW Schaffner L1 DMT2−26−11L 26 mH Power Choke CoilCraft M1 PFC MOSFET SPP20N60S5 Infineon Q1, Q2 PNP TO92 Transistor BC369 ON Semiconductor Q1x SOT23 BC846B ON Semiconductor Q5, Q6, Q7 NPN TO92 transistor BC368 ON Semiconductor R1, R3, R4, R9, R14, R16, R20, R22 1%, 1/4 W Resistors 1.8 MR various R2 1%, 1/4 W Resistors 150 R various R12, R39 1%, 1/4 W Resistors 47 R various R6 1%, 1/4 W Resistors 2.4 kR various R7 3 W PFC CS Resistor RLP3 0R1 1% Vishay R8 1%, 1/4 W Resistors 4.7 k various R10, R31, R37, R38, R51 1%, 1/4 W Resistors 10 kR various R13, R44 1%, 1/4 W Resistors 2.2 R various R15 1%, 1/4 W Resistors 62 kR various R17, R21 1%, 1/4 W Resistors 27 kR various R18, R27, R46, R58 1%, 1/4 W Resistors 22 kR various R23 1%, 1/4 W Resistors 820 kR various R24 1%, 1/4 W Resistors 560 kR various R25 3 W 0.39 R Forward CS Resistor W31−R39 JI WELWYN R33, R40, R50 1%, 1/4 W Resistors 10 R various http://onsemi.com 16 AND8281/D Bill of Materials R28, R55 1%, 1/4 W Resistors 47 kR various R29, R30 1%, 1/4 W Resistors 3.3 kR various R35 100 R / 4 W Resistor SBCHE4 Meggitt CGS R11, R43, R57 1%, 1/4 W Resistors 1 kR various R42 1%, 1/4 W Resistors 100 R various R49, R52 1%, 1/4 W Resistors 6.8 k various R1x 1%, 1/4 W Resistors 43 k various T1 PFC Coil SICO 977 Sicoenergie T2 Forward Transformer SICO 978 Sicoenergie U1 Diodes Bridge KBU6K General Semiconductor U2 Forward Controller NCP1217AD133R2G ON Semiconductor U3 PFC Controller NCP1605 ON Semiconductor X25 01:01 Pulse Transformer Q3903−A CoilCraft X29 Opto−coupler SFH6156−2 Infineon X30 TO92 Voltage Reference TL431ACDR2G ON Semiconductor X24, X31 Forward MOSFET SPP11N60S5 Infineon F1 4 A Fuse various various ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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