NCP1631 D

NCP1631
Interleaved, 2-Phase Power
Factor Controller
The NCP1631 integrates a dual MOSFET driver for interleaved
PFC applications. Interleaving consists of paralleling two small
stages in lieu of a bigger one, more difficult to design. This approach
has several merits like the ease of implementation, the use of smaller
components or a better distribution of the heating.
Also, Interleaving extends the power range of Critical Conduction
Mode that is an efficient and cost−effective technique (no need for
low trr diodes). In addition, the NCP1631 drivers are 180° phase shift
for a significantly reduced current ripple.
Housed in a SOIC16 package, the circuit incorporates all the
features necessary for building robust and compact interleaved PFC
stages, with a minimum of external components.
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MARKING DIAGRAM
A
WL
Y
WW
G
General Features
• Near−Unity Power Factor
• Substantial 180° Phase Shift in All Conditions Including Transient
•
•
•
•
•
•
•
•
•
Phases
Frequency Clamped Critical Conduction Mode (FCCrM) i.e.,
Fixed Frequency, Discontinuous Conduction Mode Operation with
Critical Conduction Achievable in Most Stressful Conditions
FCCrM Operation Optimizes the PFC Stage Efficiency Over the
Load Range
Out−of−phase Control for Low EMI and a Reduced rms Current in
the Bulk Capacitor
Frequency Fold−back at Low Power to Further Improve the Light
Load Efficiency
Accurate Zero Current Detection by Auxiliary Winding for Valley
Turn On
Fast Line / Load Transient Compensation
High Drive Capability: −500 mA / +800 mA
Signal to Indicate that the PFC is Ready for Operation (“pfcOK”
Pin)
VCC Range: from 10 V to 20 V
NCP1631G
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN ASSIGNMENT
ZCD2
FB
ZCD1
1
REF5V/pfcOK
Rt
DRV1
OSC
GND
Vcc
Vcontrol
FFOLD
DRV2
BO
Latch
OVP / UVP
CS
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1631DR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Safety Features
• Output Over and Under Voltage Protection
• Brown−Out Detection with a 50−ms Delay to Help
•
•
•
•
Typical Applications
• Computer Power Supplies
• LCD / Plasma Flat Panels
• All Off Line Appliances Requiring Power Factor
Meet Hold−up Time Specifications
Soft−Start for Smooth Start−up Operation
Programmable Adjustment of the Maximum Power
Over Current Limitation
Detection of Inrush Currents
Correction
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 7
1
Publication Order Number:
NCP1631/D
NCP1631
Vin
Vaux2
Vout
Rbo1
Rovp1
Rzcd2
Rout1
1
2
Rout2
Ac lin e
EMI
Filter
Rbo2
OVPin
Cosc
Rovp2
Ccomp2
Rcomp1
Icoil1
Rt
RFF
Cbo2 Ccomp1
16 Rzcd1
15
3
14
4
13
5
12
6
11
7
8
10
Vaux2
Icoil2
D1
Vout
pfcOK
D2
M1
Vcc
LOAD
M2
9
Cbulk
Rocp
OVPin
Cin
L1
L2
RCS
Iin
Figure 1. Typical Application Schematic
Table 1. MAXIMUM RATINGS
Symbol
Rating
Pin
Value
Unit
VCC(MAX)
Maximum Power Supply Voltage Continuous
12
−0.3, +20
V
VMAX
Maximum Input Voltage on Low Power Pins
1, 2, 3, 4, 6, 7,
8, 9, 10, 15,
and 16
−0.3, +9.0
V
5
−0.3, VControl(clamp) (Note 1)
V
550
145
mW
°C/W
−55 to +150
°C
150
°C
−65 to +150
°C
300
°C
3
kV
250
V
VControl(MAX)
PD
RqJ−A
TJ
VControl Pin Maximum Input Voltage
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
Operating Junction Temperature Range
TJ(MAX)
Maximum Junction Temperature
TS(MAX)
Storage Temperature Range
TL(MAX)
Lead Temperature (Soldering, 10s)
ESD Capability, HBM model (Note 2)
ESD Capability, Machine Model (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. “VControl(clamp)” is the pin5 clamp voltage.
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
VCC increasing
VCC decreasing
VCC decreasing
VCC(on)
VCC(off)
VCC(hyst)
VCC(reset)
11
9.5
1.5
4.0
11.85
10
1.85
5.75
12.7
10.5
−
7.5
VCC = 9.4 V
ICC(start)
−
35
100
Fsw = 130 kHz (Note 4)
VCC = 15 V, Vpin10 = 5 V
VCC = 15 V, pin 7 grounded
ICC1
−
–
−
5.0
0.4
0.4
7.0
0.8
0.8
31.5
30
35
35
38.5
38.5
126
120
140
140
154
154
76.5
85
93.5
94.5
90
105
105
115.5
115.5
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) – VCC(off)
Internal Logic Reset
V
Startup current
Supply Current
Device Enabled/No output load on pin6
Current that discharges VCC in latch mode
Current that discharges VCC in OFF
mode
mA
mA
ICC(latch)
ICC(off)
OSCILLATOR AND FREQUENCY FOLDBACK
mA
Pin 6 open
TJ = −40°C to +125°C
TJ = −55°C to +125°C (Note 6)
IOSC(clamp)
Pin 6 grounded
TJ = −40°C to +125°C
TJ = −55°C to +125°C (Note 6)
IOSC(CH1)
Ipin6 = 50 mA
IOSC(CH2)
Pin 6 grounded
TJ = −40°C to +125°C
TJ = −55°C to +125°C (Note 6)
IOSC(DISCH1)
Ipin6 = 50 mA
IOSC(DISCH2)
45
50
55
mA
Ipin6 = 50 mA, Vpin5 = 2.5 V
VFF
0.9
1.0
1.3
V
Oscillator Upper Threshold
VOSC(high)
−
5
−
V
Oscillator Lower Threshold
VOSC(low)
3.6
4.0
4.4
V
VOSC(swing)
0.93
0.98
1.03
V
Ipin9 = 100 mA
Ipin9 = 10 mA
VCS(TH100)
VCS(TH10)
−20
−10
0
0
20
10
mV
TJ = 25°C
TJ = −40°C to 125°C
TJ = −55°C to +125°C (Note 6)
IILIM1
202
194
173
210
210
210
226
226
226
mA
TJ = −40°C to +125°C
TJ = −55°C to +125°C
Iin−rush
11
10.4
14
14
17
17
mA
Ipin14 = 100 mA
Ipin14 = −100 mA
Ipin11 = 100 mA
Ipin11 = −100 mA
RSNK1
RSRC1
RSNK2
RSRC2
–
–
–
–
7
15
7
15
15
25
15
25
Clamping Charging Current
Charge Current with no frequency foldback
Charge Current @ Ipin6 = 50 mA
Maximum Discharge Current
with no frequency foldback
Discharge Current @ Ipin6 = 50 mA
Voltage on pin 6
Oscillator Swing (Note 5)
mA
mA
mA
CURRENT SENSE
Current Sense Voltage Offset
Current Sense Protection Threshold
Threshold for In−rush Current Detection
(Note 5)
GATE DRIVE
Drive Resistance
DRV1 Sink
DRV1 Source
DRV2 Sink
DRV2 Source
Ω
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
VDRV1 = 10 V
VDRV1 = 0 V
VDRV2 = 10 V
VDRV2 = 0 V
ISNK1
ISRC1
ISNK1
ISRC1
−
−
−
−
800
500
800
500
−
−
−
−
Rise Time
DRV1
DRV2
CDRV1 = 1 nF, VDRV1 = 1 to 10 V
CDRV2 = 1 nF, VDRV2 = 1 to 10 V
tr1
tr2
−
−
40
40
−
−
Fall Time
DRV1
DRV2
CDRV1 = 1 nF, VDRV1 = 10 to 1 V
CDRV2 = 1 nF, VDRV2 = 10 to 1 V
tf1
tf2
–
–
20
20
–
–
VREF
2.44
2.500
2.56
Unit
GATE DRIVE
Drive Current Capability (Note 5)
DRV1 Sink
DRV1 Source
DRV2 Sink
DRV2 Source
mA
ns
ns
REGULATION BLOCK
Feedback Voltage Reference
Error Amplifier Source Current Capability
@ Vpin2 = 2.4 V
IEA(SRC)
Error Amplifier Sink Current Capability
@ Vpin2 = 2.6 V
IEA(SNK)
Error Amplifier Gain
Pin 5 Source Current when (Vout(low)
Detect) is activated
TJ = −40°C to 125°C
TJ = −55°C to +125°C (Note 6)
Pin2 Bias Current
V
mA
−20
+20
GEA
110
200
290
mS
IControl(boost)
184
178
230
230
276
276
mA
mA
Vpin2 = 2.5 V
IFB(bias)
−500
500
nA
@ Vpin2 = 2.4 V
@ Vpin2 = 2.6 V
VControl(clamp)
VControl(MIN)
VControl(range)
3.0
0
2.7
3.6
0.6
3
4.2
1.2
3.3
V
@ Vpin2 = 2.6 V, Ipin6 = 90 mA
@ Vpin2 = 2.4 V, Ipin6 = 90 mA
VREGUL(MIN)
VREGUL(Clamp)
−
−
−
1.66
0.1
−
V
Ratio (Vout(low) Detect Threshold / VREF)
(Note 5)
FB falling
Vout(low)/VREF
95.0
95.5
96.0
%
Ratio (Vout(low) Detect Hysteresis /
VREF) (Note 5)
FB rising
Hout(low)/VREF
−
−
0.5
%
Vpin2 = 3 V
DMIN
−
−
0
%
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
TJ = −25°C to +125°C
Vpin7 = 1.1 V, Ipin3 = 50 mA
Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5)
ton1
ton2
ton3
ton4
14.5
1.10
4.00
0.35
19.5
1.35
5.00
0.41
22.5
1.60
6.00
0.48
ms
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
TJ = −40°C to +125°C
Vpin7 = 1.1 V, Ipin3 = 50 mA
Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5)
ton1
ton2
ton3
ton4
14.0
1.05
3.84
0.33
19.5
1.35
5.00
0.41
22.5
1.60
6.00
0.48
ms
Maximum DRV1 and DRV2 On−Time
(FB pin grounded)
TJ = −55°C to +125°C
Vpin7 = 1.1 V, Ipin3 = 50 mA (Note 6)
Vpin7 = 1.1 V, Ipin3 = 200 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 100 mA (Note 5)
Vpin7 = 2.2 V, Ipin3 = 400 mA (Note 5)
ton1
ton2
ton3
ton4
13.0
1.00
3.70
0.32
19.5
1.35
5.00
0.41
22.5
1.60
6.00
0.48
ms
Pin 5 Voltage:
Internal VREGUL Voltage
(measured on pin 6):
SKIP MODE
Duty Cycle
RAMP CONTROL (valid for the two phases)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
VBO = Vpin7 = 1.1 V, Ipin3 = 50 mA
VBO = Vpin7 = 1.1 V, Ipin3 = 200 mA
VBO = Vpin7 = 2.2 V, Ipin3 = 50 mA
VBO = Vpin7 = 2.2 V, Ipin3 = 200 mA
VRt1
VRt2
VRt3
VRt4
1.071
1.071
2.169
2.169
1.096
1.096
2.196
2.196
1.121
1.121
2.223
2.223
V
Not tested
Vton(MAX)
RAMP CONTROL (valid for the two phases)
Pin 3 voltage
Maximum Vton Voltage
Pin 3 Current Capability
IRt(MAX)
Pin 3 sourced current below which the
controller is OFF
5
1
IRt(off)
Pin 3 Current Range
Not tested
−
V
−
mA
7
IRt(range)
20
0.40
0.20
mA
1000
mA
0.60
0.30
V
ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2)
ZCD Threshold Voltage
VZCD increasing
VZCD falling
VZCD(TH),H
VZCD(TH),L
ZCD Hysteresis
VZCD decreasing
VZCD(HYS)
Ipin1 = 5.0 mA
Ipin1 = −5.0 mA
VZCD(high)
VZCD(low)
9.0
−1.1
11
−0.65
13
−0.1
Internal Input Capacitance (Note 5)
CZCD
−
10
−
pF
ZCD Watchdog Delay
tZCD
80
200
320
ms
Input Clamp Voltage
High State
Low State
0.50
0.25
0.25
V
V
BROWN−OUT DETECTION
Brown−Out Comparator Threshold
Brown−Out Current Source
VBO(TH)
0.97
1.00
1.03
V
TJ = −40°C to 125°C
TJ = −55°C to +125°C (Note 6)
IBO
6
5.7
7
7
8
8
mA
TJ = −40°C to 125°C
TJ = −55°C to +125°C
tBO(BLANK)
38
38
50
50
62
63.5
ms
tBO(window)
38
50
62
ms
VBO(clamp)
−
965
−
mV
IBO(clamp)
100
−
−
mA
VBO(HYS)
10
35
60
mV
IBO(PNP)
100
−
−
mA
VBO(PNP)
0.35
0.70
0.90
V
Brown−Out Blanking Time (Note 5)
Brown−Out Monitoring Window (Note 5)
Pin 7 clamped voltage if VBO < VBO(TH)
during tBO(BLANK)
Ipin7 = −100 mA
Current Capability of the BO Clamp
Hysteresis VBO(TH) – VBO(clamp)
Ipin7 = − 100 mA
Current Capability of the BO pin Clamp
PNP Transistor
Pin BO voltage when clamped by the PNP
Ipin7 = − 100 mA
OVER AND UNDER VOLTAGE PROTECTIONS
Over−Voltage Protection Threshold
VOVP
2.425
2.500
2.575
V
Ratio (VOVP / VREF) (Note 5)
VOVP/VREF
99.2
99.7
100.2
%
Ratio UVP Threshold over VREF
VUVP/VREF
8
12
16
%
IOVP(bias)
−500
−
500
nA
VLatch
2.375
2.500
2.625
V
Pin 8 Bias Current
Vpin8 = 2.5 V
Vpin8 = 0.3 V
LATCH INPUT
Pin Latch Threshold for Shutdown
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1631
Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V; for typical
values TJ = 25°C, for min/max values TJ = −55°C to +125°C, unless otherwise specified) (Note 6)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
Vpin10 = 2.3 V
ILatch(bias)
−500
−
500
nA
Pin 15 Voltage Low State
Vpin7 = 0 V, Ipin15 = 250 mA
VREF5V(low)
−
60
120
mV
Pin 15 Voltage High State
Vpin7 = 0 V, Ipin15 = 5 mA
VREF5V(high)
4.7
4.85
5.3
V
IREF5V
5
10
−
mA
Thermal Shutdown Threshold
TSHDN
130
140
150
°C
Thermal Shutdown Hysteresis
TSHDN(HYS)
−
50
−
°C
LATCH INPUT
Pin Latch Bias Current
pfcOK / REF5V
Current Capability
THERMAL SHUTDOWN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz.
5. Not tested. Guaranteed by design and characterization.
6. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.
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NCP1631
Table 3. DETAILED PIN DESCRIPTION
Pin Number
Name
Function
1
ZCD2
2
FB
This pin receives a portion of the pre−converter output voltage. This information is used for the regulation and the “output low” detection (VOUTL) that drastically speed−up the loop response when the
output voltage drops below 95.5% of the wished level.
3
RT
The resistor placed between pin 3 and ground adjusts the maximum on−time of our system for both
phases, and hence the maximum power that can be delivered by the PFC stage.
4
OSC
Connect a capacitor to set the clamp frequency of the PFC stage. If wished, this frequency can be
reduced in light load as a function of the resistor placed between pin 6 and ground (frequency
fold−back). If the coil current cycle is longer than the selected switching period, the circuit delays
the next cycle until the core is reset. Hence, the PFC stage can operate in Critical Conduction Mode
in the most stressful conditions.
5
VControl
The error amplifier output is available on this pin. The capacitor connected between this pin and
ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power
Factor ratios.
Pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly
(soft−start).
6
Freq. Foldback
Apply a resistor between pin 6 and ground to adjust the oscillator charge current. Clamped not to
exceed 100 mA, this charge current is made proportional to the power level for a reduced switching
frequency at light load and an optimum efficiency over the load range.
7
BO
(Brown−out
Protection)
Apply an averaged portion of the input voltage to detect brown−out conditions when Vpin2 drops
below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time requirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the
“pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated
to offer a programmable hysteresis.
The pin2 voltage is internally re−used for feed−forward.
Grounding pin 7 disables the part (after the 50−ms blanking time has elapsed).
8
OVP / UVP
The circuit turns off when Vpin9 goes below 480 mV (UVP) and disables the drive as long as the pin
voltage exceeds 2.5 V (OVP).
9
CS
This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the
maximum coil current and protect the PFC stage in presence of in−rush currents.
10
Latch
Apply a voltage higher than 2.5 V to latch−off the circuit. The device is reset by unplugging the PFC
stage (practically when the circuit detects a brown−out detection) or by forcing the circuit VCC below
VCCRST (4 V typically). Operation can then resume when the line is applied back.
11
DRV2
This is the gate drive pin for phase 2 of the interleaved PFC stage. The high current capability of the
totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power
MOSFETs.
12
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V and
turns off when VCC goes below 10 V (typical values). After start−up, the operating range is 9.5 V up
to 20 V.
13
GND
Connect this pin to the pre−converter ground.
14
DRV1
This is the gate drive pin for phase 1 of the interleaved PFC stage. The high current capability of the
totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power
MOSFETs.
15
REF5V /
pfcOK
The pin15 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low
otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and
that hence, it can start operation.
16
ZCD1
This is the zero current detection pin for phase 2 of the interleaved PFC stage. Apply the voltage
from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET
drain source voltage
This is the zero current detection pin for phase 1 of the interleaved PFC stage. Apply the voltage
from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET
drain source voltage.
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NCP1631
pfcOK
Vout low
detect
−
+
0.955*Vref
VD D
SHDN
UVP
Error Amplifier
±20 mA
−
Vref
Regul
Vcc
Iref
TS D
Vcc_OK
BO_NOK
IRt_low
+
FB
VD D
Vref
Internal
Thermal
Shutdown
230 mA
OVLflag1
Vcc(on)
Vcc(off)
UVLO
Vcontrol
SK I P
( 0.6 V cl amp vo ltag e Fault
management
i s acti vated)
5R
OC P
STOP
VREGUL
OF F
4R
3V
Rt
OFF
DT
VBOcomp
pfcOK
IRt_low
Generation of the charge
current for the internal
timing capacitors (max
on−time setting for the
two phases)
DRV1
ICH
DRV2
On−time control
for the two
phases
ZCD2
Vcc
S
Q
Lpwm2
R
Vpwm2
STOP
Vton
CLK1
In−rush
Vpwm1
DRV2
Ou tpu t
Buffer 1
Oscillator block
with interleaving and
frequency foldback
VZCD1
VZCD2
All the RS latches are
RESET dom inant
VZCD1
Stup
DT
OFF
DRV1
OVLflag1
−
12% Vr ef
Vovp = Vref
Current Sense Block
(Building of ICS
proportional to ICOIL)
UVP
OVP
−
ICS > 210 mA
In−rush
ICS > 14 mA
BO_NOK
Vcc_OK
−
+
Latch
Ics
CS
QZCD1
QZCD2
Vcc < Vcc(r eset)
Vr ef
pfcOK/
REF5V
S
Lstup Q
R
OC P
+
pfcOK
OFF
+
OVP
OSC
IFF
−
ZCD1
In−rush
REF5V
VDMG1
Zero current
detection for
phase 1
DRV1
Q
Lpwm1
R
STOP
VZCD2
Ou tpu t
Buffer 2
Vcc
Vpwm2
CLK2
DRV2
S
Vpwm1
VDMG2
Zero current
detection for
phase 2
VBO
CLK2
In−rush
Vton
processing
circuitry
CLK1
VBO
BO
In−rush
SKIP
Generation of the oscillator
charge current IFF as a
function of VREGUL
(frequency fold−back)
IRt < 7 mA
Brown−out
detection with
50−ms delay
OVP
IFF
FFOLD
BO_NOK
VBOcomp
+
pfcOK
OF F
R
L SHDN Q
S
DRV1
DRV2
SHDN
GND
Figure 2. Functional Block Diagram
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8
NCP1631
A “pfcOK” signal.
Detailed Operating Description
The NCP1631 integrates a dual MOSFET driver for
interleaved, 2−phase PFC applications. It drives the two
branches in so−called Frequency Clamped Critical
conduction Mode (FCCrM) where each phase operates in
Critical conduction Mode (CrM) in the most stressful
conditions and in Discontinuous Conduction Mode (DCM)
otherwise, acting as a CrM controller with a frequency
clamp (given by the oscillator). According to the
conditions, the PFC stage actually jumps from DCM to
CrM (and vice versa) with no discontinuity in operation and
without degradation of the current shape.
Furthermore, the circuit incorporates protection features
for a rugged operation together with some special circuitry
to lower the power consumed by the PFC stage in no−load
conditions. More generally, the NCP1631 is ideal in
systems where cost−effectiveness, reliability, low stand−by
power and high power factor are the key parameters:
The circuit detects when the PFC stage is in steady state
or if on the contrary, it is in a start−up or fault condition. In
the first case, the “pfcOK” pin (pin15) is in high state and
low otherwise. This signal is to disable the downstream
converter unless the bulk capacitor is charged and no fault
is detected. Finally, the downstream converter can be
optimally designed for the narrow voltage provided by the
PFC stage in normal operation.
Safety Protections.
The NCP1631 permanently monitors the input and
output voltages, the input current and the die temperature
to protect the system from possible over−stresses and make
the PFC stage extremely robust and reliable. In addition to
the aforementioned OVP protection, one can list:
Maximum Current Limit: the circuit permanently
senses the total input current and prevents it
from exceeding the preset current limit, still
maintaining the out−of−phase operation.
In−rush Detection: the NCP1631 prevents the
power switches turn on for the large in−rush
currents sequence that occurs during the
start−up phase.
Fully Stable FCCrM and Out−Of−Phase Operation.
Unlike master/slave controllers, the NCP1631 utilizes an
interactive−phase approach where the two branches
operate independently. Hence, the two phases necessarily
operate in FCCrM, preventing risks of undesired
dead−times or continuous conduction mode sequences. In
addition, the circuit makes them interact so that they run
out−of−phase. The NCP1631 unique interleaving
technique substantially maintains the wished 180° phase
shift between the 2 branches, in all conditions including
start−up, fault or transient sequences.
Under−Voltage Protection: this feature is mainly to
prevent operation in case of a failure in the
OVP monitoring network (e.g., bad
connection).
Brown−Out Detection: the circuit stops operating if
the line magnitude is too low to protect the
PFC stage from the excessive stress that could
damage it in such conditions.
Thermal Shutdown: the circuit stops pulsing when
its junction temperature exceeds 150°C
typically and resumes operation once it drops
below about 100°C (50°C hysteresis).
Optimized Efficiency Over The Full Power Range.
The NCP1631 optimizes the efficiency of your PFC
stage in the whole line/load range. Its clamp frequency is
a major contributor at nominal load. For medium and light
load, the clamp frequency linearly decays as a function of
the power to maintain high efficiency levels even in very
light load. The power threshold under which frequency
reduces is programmed by the resistor placed between pin
6 and ground. To prevent any risk of regulation loss at no
load, the circuit further skips cycles when the error
amplifier reaches its low clamp level.
NCP1631 Operating Modes
The NCP1631 drives the two branches of the interleaved
in FCCrM where each phase operates in Critical
conduction Mode (CrM) in the most stressful conditions
and in Discontinuous Conduction Mode (DCM) otherwise,
acting as a CrM controller with a frequency clamp (given
by the oscillator). According to the conditions, the PFC
stage actually jumps from DCM to CrM (and vice versa)
with no discontinuity in operation and without degradation
of the current shape.
The circuit can also transition within an ac line cycle so
that:
• CrM reduces the current stress around the sinusoid top.
• DCM limits the frequency around the line zero
crossing.
This capability offers the best of each mode without the
drawbacks. The way the circuit modulates the MOSFET
on−time allows this facility.
Fast Line / Load Transient Compensation.
Characterized by the low bandwidth of their regulation
loop, PFC stages exhibit large over and under−shoots when
abrupt load or line transients occur (e.g. at start−up). The
NCP1631 dramatically narrows the output voltage range.
First, the controller dedicates one pin to set an accurate
Over−Voltage Protection level and interrupts the power
delivery as long as the output voltage exceeds this
threshold. Also, the NCP1631 dynamic response enhancer
drastically speeds−up the regulation loop when the output
voltage is 4.5% below its desired level. As a matter of fact,
a PFC stage provides the downstream converter with a very
narrow voltage range.
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9
NCP1631
Figure 3. DCM and CRM Operation Within a Sinusoid Cycle for One Branch
NCP1631 On−time Modulation
The NCP1631 operates in voltage mode. As portrayed by
Figure 6, the MOSFET on time t1 is controlled by the signal
Vton generated by the regulation block as follows:
Let’s study the ac line current absorbed by one phase of
the interleaved PFC converter.
The current waveform of the inductor (L) during one
switching period (Tsw) is portrayed by Figure 5.
The ac line current is the averaged value of the coil
current as the result of the EMI filter “polishing” action.
Hence, the line current produced by one of the phase is:
ǒ Ǔǒt T) t ǓV
t
Iin + 1 1
2 L
1
2
sw
in
t1 +
(eq. 1)
ǒt (tT) t )Ǔ
1 1
Equation 1 shows that Iin is proportional to Vin if
t1(t 1 ) t2)
is a constant.
Tsw
Forcing
Ǔ
2
sw
to be a constant for proper power factor correction can be
changed into:
ǒt (tT) t )Ǔ
1 1
(eq. 2)
Where:
• Ct is the internal timing capacitor
• It is the internal current source for the timing capacitor.
The It charge current is constant for a given resistor
placed on the Rt pin. Ct is also a constant. Hence, the
condition
Where (Tsw = t1 + t2 + t3) is the switching period and Vin
is the ac line rectified voltage.
ǒ
C tVTON
It
ǒ
2
sw
constant is what the NCP1631 does to perform FCCrM
operation that is, to operate in discontinuous or critical
conduction mode according to the conditions, without
degradation of the power factor.
Ǔ is constant.
VTON(t 1 ) t2)
T sw
The output of the regulation block (VCONTROL) is
linearly changed into a signal (VREGUL) varying between
0 and 1.66 V. (VREGUL) is the voltage that is injected into
the PWM section to modulate the MOSFET duty−cycle.
However, the NCP1631 inserts some circuitry that
processes (VREGUL) to form the signal (VTON) that is used
in the PWM section instead of (VREGUL) (see Figure 7).
(VTON) is modulated in response to the dead−time sensed
during the precedent current cycles, that is, for a proper
shaping of the ac line current. This modulation leads to:
VTON +
Figure 4. Boost Converter
T swVREGUL
t1 ) t2
or: VTON
t1 ) t2
+ VREGUL (eq. 3)
Tsw
Substitution of Equation 3 into Equation 2 leads to the
following on−time expression:
ǒ
Ct
t1 +
Ǔ
TswVREGUL
t1)t2
(eq. 4)
It
Replacing “t1” by its expression of Equation 4,
Equation 1 simplifies as follows:
Iin(phase1) + I in(phase2) +
Figure 5. Inductor Current in DCM
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10
V in C tVREGUL
2L
It
(eq. 5)
NCP1631
Given the regulation low bandwidth of the PFC systems,
(VCONTROL) and then (VREGUL) are slow varying signals.
Hence, the line current absorbed by each phase is:
Iin(phase1) + I in(phase2) + k V in
where: k + constant +
ƪ
From this equation, we can check that if Vpin7 (BO
voltage) is 1 V and Rt is 20 kW (Ipin3 = 50 mA) that the
on−time is 20 ms as given by parameter Ton1.
Since:
(eq. 6)
ƫ
VREGUL(max) + 1.66 V
C tVREGUL
2 L It
Ton +
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped.
One can note that this analysis is also valid for CrM
operation that is just a particular case of this functioning
where (t3=0), which leads to (t1+t2=Tsw) and
(VTON=VREGUL). That is why the NCP1631 automatically
adapts to the conditions and jumps from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
The charging current It is internally processed to be
proportional to the square of the line magnitude. Its value
is however programmed by the pin 3 resistor to adjust the
available on−time as defined by the Ton1 to Ton4 parameters
of the data sheet.
From these data, we can deduce:
Rt 2
t1 + T on(ms) + 50 n
Vpin7 2
C tVREGUL
It
Vpin7 +
2 Ǹ2 Vin(rms)
k BO
p
where kBO is the scale down factor of the BO sensing
network
ǒ
k BO +
Ǔ
R bo2
R bo1 ) R bo2
(see Brown−out section)
We can deduce the total input current value and the
average input power:
Iin(rms) ^
(R t)2V REGUL
26.9 @ 10 12 L k BO 2V in,rms
(eq. 8)
(Rt)2V REGUL
26.9 @ 10 12 L k BO 2
(eq. 9)
Pin,avg ^
(eq. 7)
timing capacitor
s aw −too th
PWM
comparator
+
to PWM latch
−
VREGUL
+
R1
OA1
Vton
SKIP
−
C1
S3
OC P
0.5*
(I se nse
− 210 m)
S1
IN 1
S2
−> V ton d u ring (t1+t2)
−> 0 V d u ring t3 (d e a d −time)
−> V ton *(t1+t2)/T in average
OV P
OF F
VBOcomp
(from BO block)
pfcOK
DT
(high during dead−time)
In−rus h
The integrator OA1 amplifies the error between VREGUL and
IN1 so that in average, (VTON*(t1+t2)/Tsw) equates VREGUL.
Figure 6. PWM Circuit and Timing Diagram
Figure 7. VTON Processing Circuit
The “VTON processing circuit” is “informed” when there
is an OVP condition or a skip sequence, not to
over−dimension VTON in that conditions. Otherwise, an
OVP sequence or a skipped cycle would be viewed as a
“normal” dead−time phase by the circuit and VTON would
inappropriately increase to compensate it. (Refer to
Figure 7).
The output of the “VTON processing circuit” is also
grounded when the circuit is in OFF state to discharge the
capacitor C1 and initialize it for the next active phase.
Finally, the “VTON” is not allowed to be further increased
compared to VREGUL when the circuit has not completed
the start−up phase (pfcOK low) and if VBOcomp from the
brown−out block is high (refer to brown−out section for
more information).
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11
350,00
3,50
300,00
3,00
250,00
2,50
200,00
2,00
150,00
1,50
100,00
Ton (ms)
Vin (V)
NCP1631
1,00
Vin
ton
50,00
0,50
0,00
0,00
0
2
4
6
8
10
time (ms)
12
14
16
18
20
Figure 8. Input Voltage and On−time vs. Time (example with FSW = 100 kHz, Pin = 150 W, VAC = 230 V, L = 200 mH)
Regulation Block and Low Output Voltage Detection
The swing of the error amplifier output is limited within
an accurate range:
• It is forced above a voltage drop (VF) by the “low
clamp” circuitry. When this circuitry is activated, the
power demand is minimum and the NCP1631 enters
skip mode (the controller stops pulsating) until the
clamp is no more active.
• It is clamped not to exceed 3.0 V + the same VF
voltage drop.
A trans−conductance error amplifier with access to the
inverting input and output is provided. It features a typical
trans−conductance gain of 200 mS and a typical capability
of ±20 mA. The output voltage of the PFC stage is typically
scaled down by a resistors divider and monitored by the
inverting input (feed−back pin – pin2). The bias current is
minimized (less than 500 nA) to allow the use of a high
impedance feed−back network. The output of the error
amplifier is pinned out for external loop compensation
(pin5). Typically a type−2 compensator is applied between
pin5 and ground, to set the regulation bandwidth below
20 Hz, as need in PFC applications (refer to application
note AND8407).
FB
230 m A
VDD
−
0.955*Vref
pfcOK
+
Vout low
detect
Hence, Vpin5 features a 3 V voltage swing. Vpin5 is then
offset down by (VF) and further divided before it connects
to the “Vton processing block” and the PWM section.
Finally, the output of the regulation is a signal (“VREGUL”
of the block diagram) that varies between 0 and 1.66 V.
E rr o r Am p lifier
±20 m A
−
V control
+
Vref
OVLflag1
OFF
5R
SKIP (0 .6 V c lamp
vo ltage is activated)
VREGUL
3V
4R
Figure 9. Regulation Block
Figure 10. Correspondence Between
VCONTROL and VREGUL
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12
NCP1631
Zero Current Detection
Provided the low bandwidth of the regulation loop, sharp
variations of the load, may result in excessive over and
under−shoots. Over−shoots are limited by the Over−
Voltage Protection (see OVP section). To contain the
under−shoots, an internal comparator monitors the
feed−back signal (Vpin2) and when Vpin2 is lower than
95.5% of its nominal value, it connects a 230 mA current
source to speed−up the charge of the compensation
capacitor (Cpin5). Finally, it is like if the comparator
multiplied the error amplifier gain by 10.
One must note that this circuitry for under−shoots
limitation, is not enabled during the start−up sequence of
the PFC stage but only once the converter has stabilized
(that is when the “pfcOK” signal of the block diagram, is
high). This is because, at the beginning of operation, the
pin5 capacitor must charge slowly and gradually for a soft
start−up.
While the on time is constant, the core reset time varies
with the instantaneous input voltage. The NCP1631
determines the demagnetization completion by sensing the
inductor voltage, more specifically, by detecting when the
inductor voltage drops to zero.
Practically, an auxiliary winding in flyback
configuration is taken off of the boost inductor and gives a
scaled down version of the inductor voltage that is usable
by the controller (Figure 12). In that way, the ZCD voltage
(“VAUX”) falls and starts to ring around zero volts when the
inductor current drops to zero. The NCP1631 detects this
falling edge and allows the next driver on time.
Figure 1 shows how it is implemented.
For each phase, a comparator detects when the voltage
of the ZCD winding exceeds 0.5 V. When this is the case,
the coil is in demagnetization phase and the latch LZCD is
set. This latch is reset when the next driver pulse occurs.
Rzcd2
Rzcd1
1
ZCD2
16
ZCD1
Negative
and
positive
clamp
S
LZCD
Qzcd1
Q
S
QZCD
R
CLK1
R
(from phase
In−rush
management
block)
200−ms
delay
S
OFF
(from Fault
management
VDMG2
block)
+
−
0.5 V
PWM
latch
PH1
Vzcd1
SET1
+
−
0.5 V
L1
AND1
VDMG1
Negative
and
positive
clamp
D1
Vin
Q
Vcc
DRV1
Q
14 M1
output
buffe r 1
reset signal
(from PH1 PWM
comparator)
DT
R
D2
Vout
Vin L2
Vzcd2
S
R
Q
SET2
PWM
latch PH2
output
buffe r 2
Vcc
Qzcd2
S
Q
CLK2
R
(from phase
management In−rush
reset signal
block)
(from PH2 PWM comparator)
DRV2
Cbulk
11 M2
Cbulk
Figure 11. Zero Current Detection
To prevent negative voltages on the ZCD pins (ZCD1 for
phase 1 and ZCD2 for phase 2), these pins are internally
clamped to about 0 V when the voltage applied by the
corresponding ZCD winding is negative. Similarly, the
ZCD pins are clamped to VZCD(high) (10 V typical), when
the ZCD voltage rises too high. Because of these clamps,
a resistor (RZCD of Figure 11) is necessary to limit the
current from the ZCD winding to the ZCD pin. The clamps
are designed to respectively source and sink 5 mA
minimum. It is recommended not to exceed this 5 mA level
within the ZCD clamps for a proper operation.
At startup or after an inactive period (because of a
protection that has tripped for instance), there is no energy
in the ZCD winding and therefore no voltage signal to
activate the ZCD comparator. This means that the driver
will never turn on. To avoid this, an internal watchdog
timer is integrated into the controller. If the driver remains
low for more than 200 ms (typical), the timer sets the LZCD
latch as the ZCD winding signal would do. Obviously, this
200−ms delay acts as a minimum off−time if there is no
demagnetization winding while it has no action if there is
a ZCD voltage provided by the auxiliary winding.
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13
NCP1631
Figure 12. Zero Current Detection Timing Diagram
(VAUX is the Voltage Provided by the ZCD Winding)
Current Sense
not to sink more than 5 mA from the CS pin for a proper
operation.
Two functions use ICS: the over current protection and
the in−rush current detection.
The NCP1631 is designed to monitor a negative voltage
proportional to total input current, i.e., the current drawn by
the two interleaved branches (Iin). As portrayed by
Figure 13, a current sense resistor (RCS) is practically
inserted within the return path to generate a negative
voltage (VCS) proportional to Iin. The circuit uses VCS to
detect when Iin exceeds its maximum permissible level. To
do so, the circuit incorporates an operational amplifier that
sources the current necessary to maintain the CS pin
voltage null (refer to Figure 13). By inserting a resistor
ROCP between the CS pin and RCS, we adjust the current
that is sourced by the CS pin (ICS) as follows:
* [R CSICOIL] ) [ROCPI CS] + 0
Over−Current Protection (OCP)
If ICS exceeds IILIM1 (210 mA typical), an over−current
is detected and the on−time is decreased proportionally to
the difference between the sensed current IIN and the
210 mA OCP threshold.
The on−time reduction is done by injecting a current Ineg
in the negative input of the “VTON processing circuit”
OPAMP. (See Figure 7)
Ineg + 0.5(I CS * 210 m)
(eq. 10)
This current is injected each time the OCP signal is high.
Which leads to:
ICS +
RCS
I
R OCP COIL
(eq. 12)
The maximum coil current is:
(eq. 11)
ICOIL(max) +
In other words, the pin 9 current (ICS) is proportional to
the coil current.
A negative clamp protects the circuit from the possible
negative voltage that can be applied to the pin. This
protection is permanently active (even if the circuit off).
The clamp is designed to sustain 5 mA. It is recommended
R OCP
I
RCS ILIM1
(eq. 13)
In−rush Current Detection
When the PFC stage is plugged to the mains, the bulk
capacitor is abruptly charged to the line voltage. The
charge current (named in−rush current) can be very huge
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14
NCP1631
EMI
Filter
VIN
MOSFETs from the possible excessive stress it could suffer
from if it was allowed to turn on while a huge current
flowed through the coil as it can be the case at start−up or
during an over−load transient.
The propagation delay (ICS < Iin−rush) to (drive outputs
high) is in the range of few ms.
However when the circuit starts to operate, the NCP1631
disables this protection to avoid that the current produced
by one phase and sensed by the circuit prevents the other
branch from operating. Practically, some logic grounds the
In−rush protection output when it detects the presence of
current cycles with a zero current detection signal provided
by the auxiliary winding (Figure 13).
Vaux2
IIN
Vaux1
Curr e nt
Mirror
CIN
The pin voltage
is maintained
to 0 V
CS
ICS
OC P
ICS
ICS
In−r ush
Iin−rush = 14 mA
Negative clamp
M2
DRV 2
(from ZCD
block)
QZCD1
QZCD2
ROCP
RCS
L2
L1
IILIM1 = 210 mA
(ICS is proportional to the coil current)
9
ICS
ICS
D1
VOUT
D2
M1
DRV 1
CBULK
DRV 1
DRV 2
LOAD
Ac lin e
depending on the presence or absence of an effective
in−rush limiting circuitry. If the MOSFET turns on during
this severe transient, it may be over−stressed and finally
damaged. That is why, the NCP1631 permanently monitors
the input current and delays the MOSFET turn on until the
in−rush current has vanished. This is the function of the ICS
comparison to the Iin−rush threshold (14 mA typical). When
ICS exceeds Iin−rush, the comparator output (“In−rush”) is
high and prevents the PWM latches from setting (see block
diagram). Hence, the two drivers cannot turn high and the
MOSFETs cannot switch on. This is to guarantee that the
MOSFETs remain off as long as if the input current exceeds
10% of its maximum value. This feature protects the
IIN
The CS block performs the over−current protection and the in−rush current detection.
Figure 13. Current Sense Block
Over−Voltage Protection
While PFC circuits often use one single pin for both the
Over−Voltage Protection (OVP) and the feed−back, the
NCP1631 dedicates one specific pin for the under−voltage
and over−voltage protections. The NCP1631 configuration
allows the implementation of two separate feed−back
networks (see Figure 15):
1. One for regulation applied to pin 2.
2. Another one for the OVP function (pin 8).
Vout (bulk voltage)
Vout (bulk voltage)
Rout1
Rout1
1
FB
2
3
16
FB
15
14
Rout3
Rout2
4
13
5
12
6
11
7
OVP
8
Rovp1
Rout2
1
2
16
3
14
4
13
5
12
6
11
7
10
15
Rovp2
10
OVP
9
9
8
Figure 14. Configuration with One Feed−back
Network for Both OVP and Regulation
Figure 15. Configuration with Two
Separate Feed−back Networks
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15
NCP1631
should be used to allow operation of the downstream
converter.
The double feed−back configuration offers some
up−graded safety level as it protects the PFC stage even if
there is a failure of one of the two feed−back arrangements.
However, if wished, one single feed−back arrangement
is possible as portrayed by Figure 14. The regulation and
OVP blocks having the same reference voltage, the
resistance ratio Rout2 over Rout3 adjusts the OVP threshold.
More specifically,
Oscillator Section – Phase Management
The oscillator generates the clock signal that dictates the
maximum switching frequency for the global system (fosc).
In other words, each of the two interleaved branches cannot
operate above the clamp frequency that is half the oscillator
frequency (fosc/2). The oscillator frequency (fosc) is
adjusted by the capacitor applied to pin 4. Typically, a
440 pF capacitor approximately leads to a 120−kHz
operating frequency, meaning a 60−kHz clamp frequency
for each branch. The oscillator frequency should be kept
below 500 kHz (which corresponds to a pin4 capacitor in
the range of 100 pF).
As shown by Figure 16, two current sources IOSC(clamp)
(35 mA typical) and IOSC(CH) (105 mA typical) charge the
pin 4 capacitor until its voltage exceeds VOSC(high) (5 V
typically). At that moment, the output of the COMP_OSC
comparator (“SYNC” of Figure 16) turns high and changes
the COMP_OSC reference threshold that drops from
VOSC(high) down to VOSC(low) (hysteresis). The system
enters a discharge phase where the ICH current source is
disabled and instead a sink current IOSC(DISCH) (105 mA
typ.) discharges the pin 4 capacitor. This sequence lasts
until Vpin4 goes below VOSC(low) when the “SYNC” signal
turns low and a new charging phase starts. A divider by two
uses the “SYNC” information to manage the phases of the
interleaved PFC: the first SYNC pulse sets “phase 1”, the
second one, “phase 2”, the third one phase 1 again... etc...
According to the selected phase, the “SYNC” signal sets
the relevant “Clock generator latch” that will generate the
clock signal (“CLK1” for phase 1, “CLK2” for phase 2)
when SYNC drops to zero (falling edge detector). So, the
drivers are synchronized to SYNC falling edge.
Actually, the drivers cannot turn on at this very moment
if the demagnetization of the coil is not yet complete (CrM
operation). In this case, the clock signal is maintained high
until the driver turns high (the clock generator latches are
reset by the corresponding driver is high − reset on rising
edge detector). Also, the discharge time can be prolonged
if when Vpin4 drops below VOSC(low), the driver of the
phase cannot turn on because the core is not reset yet (CrM
operation). In this case, Vpin4 decreases until the driver
turns high. The further discharge of Vpin4 below VOSC(low)
helps maintain a substantial 180° phase shift in CrM that is
in essence, guaranteed in DCM. In the two conditions (CrM
or DCM), operation is stable and robust.
Figure 17 portrays the clock signal waveforms in
different cases:
− In fixed frequency operation (DCM), the cycle
time of the coil current is shorter than an
oscillator period. Hence, as soon as the clock
signal goes high, the driver can turn on and
reset the clock generator latch. The clock
signal is then a short pulse.
The bulk regulation voltage (“Vout(nom)”) is:
Vout(nom) +
R out1 ) R out2 ) R out3
@ V ref
R out2 ) R out3
(eq. 14)
The OVP level (“Vout(ovp)”) is:
Vout(ovp) +
R out1 ) R out2 ) R out3
@ V ref
R out2
(eq. 15)
The ratio OVP level over regulation level is:
Vout(ovp)
Vout(nom)
+1)
Rout3
Rout2
(eq. 16)
For instance, (Vout(nom) = 105% x Vout(nom)) leads to:
(Rout3 = 5% x Rout2).
When the circuit detects that the output voltage exceeds
the OVP level, it maintains the power switch open to stop
the power delivery.
As mentioned previously, the “VTON processing circuit”
is “informed” when there is an OVP condition, not to
over−dimension VTON in that conditions. Otherwise, an
OVP sequence would be viewed as a dead−time phase by
the circuit and VTON would inappropriately increase to
compensate it (refer to Figure 7).
PfcOK / REF5V Signal
The NCP1631 can communicate with the downstream
converter. The signal “pfcOK/REF5V” is high (5 V) when
the PFC stage is in normal operation (its output voltage is
stabilized at the nominal level) and low otherwise.
More specifically, “pfcOK/REF5V” is low:
− During the PFC stage start−up, that is, as long as
the output voltage has not yet stabilized at the
right level. The start−up phase is detected by
the latch “LSTUP” of the block diagram in
Figure 2. “LSTUP” is set during each “off”
phase so that its output (“STUP“) is high when
the circuit enters an active phase. The latch is
reset when the error amplifier stops charging
its output capacitor, that is, when the output
voltage of the PFC stage has reached its
desired regulation level. At that moment,
“STUP” falls down to indicate the end of the
start−up phase.
− Any time, the circuit is off or a fault condition is
detected as described by the “Fault
management and OFF mode” section
Finally, “pfcOK/REF5V” is high when the PFC output
voltage is properly and safely regulated. “pfcOK/REF5V”
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16
NCP1631
− However, the coil current can possibly be non
zero when the clock signal turns high. The
circuit would enter Continuous Conduction
Mode (CCM) if the MOSFET turned on in that
moment. In order to avoid CCM operation, the
clock is prevented from setting the PWM latch
until the core is reset (that is as low as “VZCD”
of Figure 8 is low). The clock signal remains
high during this waiting phase (refer to
Figure 12). Hence the next MOSFET
conduction time occurs as soon as the coil
current has totally vanished. In other words,
critical conduction mode (CrM) operation is
obtained.
The clamp frequency can be computed using the
following equation:
60 m
C OSC ) 10 p
fosc ^
(eq. 17)
where COSC is the pin 4 external capacitor and Cpin the pin
4 parasitic capacitance (about 10 pF).
105 mA
FFOLD
Current
Mirror
IFF
VREGUL
RFF
VREGUL
IFF
pfcOK
Circuitry for
Frequency Foldback
CL K1
SYNCbar
DRV 1
SYNCbar
IOSC(CH) = IFF
R
CLK1
Ge nera tion
latch
IOSC(clamp)
Co mp _OSC
OS C
S
SYNC
Q_ph1
Q
P h ase1
COSC
VOSC(high)/
VOSC(low)
DRV 2
divider
by tw o
P hase2
IOSC(DISCH) = IFF
Q_ph2
Q_ph2
R
Q_ph1
CLK2
Ge nera tion
latch
S
Q
SYNCbar
Figure 16. Oscillator Block
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17
CL K2
NCP1631
Figure 17. Typical Waveforms (Tdelay not shown here for the sake of simplicity)
Frequency Foldback
“VREGUL” is the signal derived from Vcontrol that is
effectively used to modulate the MOSFET on−time.
VREGUL is buffered and applied to pin 6 (“Frequency
fold−back” pin). A resistor RFF is to be connected to pin 6
to sink a current proportional to VREGUL
In addition, the circuit features the frequency fold−back
function to improve the light load efficiency. Practically,
the oscillator charge and discharge currents (IOSC(CH) and
IOSC(DISCH) of Figure 16) are not constant but dependent on
the power level. More specifically, IOSC(CH) and
IOSC(DISCH) linearly vary as a function of Vcontrol output of
the regulation block that thanks to the feed−forward
featured by the NCP1631, is representative of the load.
The practical implementation is portrayed by Figure 16.
ǒ
Ipin6 + I FF +
Ǔ
V REGUL
.
R FF
This current is clamped not to exceed 105 mA and copied
by a current mirror to form IOSC(CH) and IOSC(DISCH).
As a matter of fact, the oscillator charge current is:
IOSC(CH) + I OSC(clamp) )
V REGUL
R FF
if
ǒ
Ǔ
VREGUL
v 105 mA
RFF
IOSC(CH) + I OSC(clamp) ) I OSC(CH1) + I OSC(CHT1) + 140 mA
The oscillator charge current is then an increasing function of VREGUL and is clamped to 140 mA.
The oscillator discharge current is:
IOSC(DISCH) +
V REGUL
R FF
IOSC(DISCH) + I OSC(DISCH1) + 105 mA
if
ǒ
(eq. 18)
otherwise
Ǔ
VREGUL
v 105 mA
RFF
(eq. 19)
otherwise
value for (IFF = 105 mA). If we consider the clamp
frequency fOSC computed by Equation 17 as the nominal
value obtained at full load and if we name it “fOSC(nom)”:
The oscillator discharge current is also an increasing
function of VREGUL and is clamped to105 mA.
As a consequence, the clamp frequency is also an
increasing function of VREGUL until it reaches a maximum
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18
NCP1631
if ǒVREGUL w R FF @ 105 mAǓ
fOSC + f OSC(nom)
fOSC +
VREGUL(R FFIOSC(clamp) ) VREGUL)
60 m R FF(RFFI OSC(clamp) ) 2V REGUL)
Let’s illustrate this operation on an example.
VREGUL is the control signal that varies between 0 and
1.66 V, (VREGUL = 1.66 V) corresponding to the maximum
power (Pin)HL that can virtually be delivered by the PFC
stage as selected by the timing resistor (for more details,
you can refer to the application note AND8407).
@ f OSC(nom)
if ǒVREGUL v R FF @ 105 mAǓ
(eq. 20)
If one decides to start to reduce the clamp frequency
when the power goes below (Pin)HL/2, the oscillator charge
current should start to decrease when VREGUL is 0.83 V.
Hence, the pin 6 resistor (“RFF”) must be selected so that
pin 6 sources 105 mA when VREGUL equates 0.83 V:
RFF +
0.83 V
+ 7.9 kW
105 mA
(eq. 21)
Let’s take (RFF = 8.2 kW) which is a normalized value.
This selection leads to:
if ǒVREGUL w 8.2 k @ 105 m + 860 mVǓ
fOSC + f OSC(nom)
fOSC +
V REGUL(RFFI OSC(clamp) ) V REGUL)
492 m(RFFI OSC(clamp) ) 2V REGUL)
@ f OSC(nom)
if ǒVREGUL v 860 mVǓ
(eq. 22)
For instance, if the nominal frequency (fOSC(nom)) is 120 kHz, the following characteristic is obtained.
150
100
Fosc (kHz)
fOSC(nom) = 120 kHz
50
0
0
0.5
1
1.5
VREGUL (V)
Figure 18. Fold−back Characteristic of the Clamp Frequency with RFF = 8.2 kW and fOSC(nom) = 120 kHz
If pin6 is grounded (accidently or not), the circuit operates
properly with a constant 140 mA oscillator charge current and
a 105 mA discharge current. The clamp frequency equates its
nominal value over the whole load range.
If pin6 is open, the oscillator charge current is equal to
IOSC(clamp) but the oscillator discharge current is null and
hence the PFC stage cannot operate.
A minimum discharge current and hence a minimum
clamp frequency can be forced by placing a resistor
between pin 4 and ground. For instance, a 1.5−MW resistor
forces a 3.3−mA discharge current when the oscillator
capacitor is fully charged and about 2.6 mA when it is near
the oscillator low threshold (4 V).
A transistor pulls the pin 6 down during startup to disable
the frequency fold−back function.
Skip Mode
The circuit features the frequency fold−back that leads to
a very efficient stand−by mode. In order to ensure a proper
regulation in no load conditions even if this feature is not
used (pin 6 grounded), the circuit skips cycles when the
error amplifier output is at its minimum level. The error
amplifier output is maintained between about 0.6 V and
3.6 V thanks to active clamps. A skip sequence occurs as
long as the 0.6 V clamp circuitry is triggered and switching
operation is recovered when the clamp is inactive.
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19
NCP1631
Brown−Out Protection
The brown−out pin receives a portion of the input voltage (VIN). As VIN is a rectified sinusoid, a capacitor must integrate
the ac line ripple so that a voltage proportional to the average value of (VIN) is applied to the brown−out pin.
IRt_ low
IRt < 7 mA
Current M irror
Rt
IRt
VBO
RRt
Vin
VBO
IRt
Feed−forward
circuitry
Ac line
EM I
Filter
Cin
RCS
Rbo1
Cbo
1V
BO
BO_NOK
Tdelay
Rbo2
S
LBO Q
R
s2
Vdd
This PNP transistor
maintains the BO pin
below the BO threshold
when the circuit is not fed
enough to control the
state of the BO block
VBOcomp
s1
7 mA
980 mV
Clamp
50-ms
delay
reset
50-ms
delay
res et
This voltage
(“VBOcomp”) is
high when Vpin7
is below 1 V
Ci r c uitr y fo r
brown−out detection
Figure 19. Brown−out Block
The main function of the BO block is to detect too low
input voltage conditions. A 7−mA current source lowers the
BO pin voltage when a brown−out condition is detected.
This is for hysteresis purpose as required by this function.
In nominal operation, the voltage applied to pin7 must be
higher than the 1 V internal voltage reference. In this case,
the output of the comparator BO_Comp (VBOcomp) is low
(see Figure 19).
Conversely, if Vpin7 goes below 1 V, the BO_Comp
output turns high and a 965 mV voltage source is connected
to the BO pin to maintain the pin level near 1 V. Then, a
50−ms blanking delay is activated during which no fault is
detected. The main goal of the 50−ms lag is to help meet
the hold−up requirements. In case of a short mains
interruption, no fault is detected and hence, the “pfcOK”
signal remains high and does not disable the downstream
converter. In addition, pin7 being kept at 965 mV, there is
almost no extra delay between the line recovery and the
occurrence of a proper voltage applied to pin2, that
otherwise would exist because of the large capacitor
typically placed between pin7 and ground to filter the input
voltage ripple. As a result, the NCP1631 effectively
“blanks” any mains interruption that is shorter than 25 ms
(minimum guaranteed value of the 50−ms timer).
At the end of this 50−ms blanking delay, another timer is
activated that sets a 50−ms window during which a fault
can be detected. This is the role of the second 50−ms timer
of Figure 19:
• if the output of OPAMP is high at the end of the first
delay (50−ms blanking time) and before the second
50−ms delay time is elapsed, a brownout condition is
detected
• if the output of OPAMP remains low for the duration
of the second delay, no fault is detected.
When the “BO_NOK” signal is high:
− The drivers are disabled, the “Vcontrol” pin is
grounded to recover operation with a soft−start
when the fault has gone and the “pfcOK”
voltage turns low to disable the downstream
converter.
− The OPAMP output is separated from pin7
(Figure 19) to prevent the operational
amplifier from maintaining 1 V on pin7 (as
done by the switches s1 and s2 in the
representation of Figure 19). Instead, Vpin2
drops to the value that is externally forced (by
Vin, Rbo1, Rbo2 and Cbo2 in Figure 19). As a
consequence, the OPAMP output remains high
and the “BO_NOK” signal stays high until the
line recovers.
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20
NCP1631
− The 7−mA current source is enabled that lowers
the pin7 voltage for hysteresis purpose.
A short delay (Tdelay) is added to get sure that these three
actions are properly done before the PFC driver is disabled
and the “Vcontrol” and “pfcOK” pins are grounded.
At startup (and in UVLO situations that is when the Vcc
voltage is not sufficient for operation), a pnp transistor
ensures that the BO pin voltage remains below the 1 V
threshold until VCC reaches VCC(on). This is to guarantee
that the circuit starts operation in the right state, that is,
“BONOK” high. When VCC exceeds VCC(on), the pnp
transistor turns off and the circuit enables the 7−mA current
source (IBO).
Also, (IBO) is enabled whenever the part is in off−mode,
but at startup, IBO is disabled until VCC reaches VCC(on).
temperature exceeds 140°C typically. The output stage is
then enabled once the temperature drops below about 80°C
(60°C hysteresis).
The temperature shutdown keeps active as long as the
circuit is not reset, that is, as long as VCC keeps higher than
VCCRESET. The reset action forces the TSD threshold to
be the upper one (140°C). This ensures that any cold
start−up will be done with the right TSD level.
Under−Voltage Lockout Section
The NCP1631 incorporates an Under−Voltage Lockout
block to prevent the circuit from operating when the power
supply is not high enough to ensure a proper operation. An
UVLO comparator monitors the pin 12 voltage (VCC) to
allow the NCP1631 operation when VCC exceeds 12 V
typically. The comparator incorporates some hysteresis
(2.0 V typically) to prevent erratic operation as the VCC
crosses the threshold. When VCC goes below the UVLO
comparator lower threshold, the circuit turns off.
The circuit off state consumption is very low: < 50 mA.
This low consumption enables to use resistors to charge
the VCC capacitor during the start−up without the penalty
of a too high dissipation.
Brown−out Resistors Calculation
The BO resistors can be calculated with the following
equations (for more details, refer to the application note
AND8407)
(V in,avg)boH
Rbo1 +
Rbo2 +
ȡ
*ȧ(V
Ȣ
ȡ f10 ȣȣ
ȧ1 * 3f ȧȧ
Ȣ
ȤȤ
line
in,avg) boL
line
IHYST
ǒ
Rbo1
(Vin,avg)boL
VBO(th)
ǒ
ǓǓ
f
1 * BO
3fline
Output Drive Section
(eq. 23)
The circuit embeds two drivers to control the two
interleaved branches. Each output stage contains a totem
pole optimized to minimize the cross conduction current
during high frequency operation. The gate drive is kept in
a sinking mode whenever the Under−Voltage Lockout
(UVLO) is active or more generally whenever the circuit
is off. Its high current capability (−500 mA/+800 mA)
allows it to effectively drive high gate charge power
MOSFET.
(eq. 24)
*1
Feed−forward
As shown by Figure 19, The BO circuit also generates an
internal current proportional to the input voltage average
value (IRt). The pin7 voltage is buffered and made available
on pin 3. Placing a resistor between pin 3 and ground,
enables to adjust a current proportional to the average input
voltage. This current (IRt) is internally copied and squared
to form the charge current for the timing capacitor of each
phase. Since this current is proportional to the square of the
line magnitude, the conduction time is made inversely
proportional to the line magnitude. This feed−forward
feature makes the transfer function and the power delivery
independent of the ac line level. Only the regulation output
(VREGUL) controls the power amount. If the IRt current is
too low ( below 7 mA), the controller goes in OFF mode to
avoid damaging the MOSFETs with too long conduction
time.
Reference Section
The circuit features an accurate internal reference
voltage (VREF). VREF is optimized to be ±2.4% accurate
over the temperature range (the typical value is 2.5 V).
VREF is the voltage reference used for the regulation and
the over−voltage protection. The circuit also incorporates
a precise current reference (IREF) that allows the
Over−Current Limitation to feature a ±6% accuracy over
the temperature range.
Fault Management and OFF Mode
The circuit detects a fault if the Rt pin is open (Figure 20).
Practically, if the pin sources less than 7 mA, the “IRt_Low”
signal sets a latch that turns off the circuit if its output
(Rt(open)) is high. A 30−ms blanking time avoids parasitic
fault detections. The latch is reset when the circuit is in
UVLO state (too low VCC levels for proper operation).
Thermal Shutdown (TSD)
An internal thermal circuitry disables the circuit gate
drive and then keeps the power switch off when the junction
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21
NCP1631
Internal
Thermal
Shutdown
Vref
Vcc
VDD
Regul
TSD
Iref
Stdwn
UVP
Vcc_OK
BO_NOK
UVLO
12 V / 10 V
Rt(open)
Q
R
S
30−ms
blanking
time
IRt_Low
(Ipin3 < 7 mA)
OF F
Fault
management
Figure 20. Fault Management Block
− The pin5 capacitor (Vcontrol) is discharged and kept
grounded along the OFF time, to initialize it for the
next operating sequence, where it must be slowly and
gradually charged to offer some soft−start.
− The “pfcOK” pin is grounded.
− The output of the “VTON processing block” is
grounded
When the circuit recovers after a fault, the first watchdog
time is around 20 ms instead of 200 ms to allow a faster
re−start.
In OFF mode at startup, the consumption is very low (<
50 mA). The brown−out block is initialized not to allow
operation (“BO_NOK” high) by default. The PNP clamp is
active and maintains the BO pin level below 1 V. The 7−mA
current source is enabled only when VCC reaches VCC(on)
threshold.
When any of the following faults is detected:
− brown−out (“BO_NOK”)
− Under−Voltage Protection (“UVP”)
− Latch−off condition (“Stdwn”)
− Die over−temperature (“TSD”)
− Too low current sourced by the Rt pin (“Rt(open)”)
− “UVLO” (improper Vcc level for operation)
The circuit turns off. In this mode, the controller stops
operating. The major part of the circuit sleeps and its
consumption is minimized (< 500 mA). More specifically,
when the circuit is in OFF state:
− The two drive outputs are kept low
− The 7−mA current source of the brown−out block is
enabled to set the proper start−up BO threshold if Vcc
is high enough for proper operation. If not, the
brown-out pin is pulled down by a pnp transistor for a
proper input voltage sensing when the circuit recovers
operation (see brown-out section).
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22
NCP1631
Figure 21. Start−up and Brown Out Conditions
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23
NCP1631
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0_
7_
0_
7_
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
ON Semiconductor and
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NCP1631/D