Power Factor Correction Stages Operating in Critical Conduction Mode

AND8123/D
Power Factor Correction
Stages Operating in Critical
Conduction Mode
This paper proposes a detailed and mathematical analysis
of the operation of a critical conduction mode Power factor
Corrector (PFC), with the goal of easing the PFC stage
dimensioning. After some words on the PFC specification
and a brief presentation of the main critical conduction
schemes, this application note gives the equations necessary
for computing the magnitude of the currents and voltages
that are critical in the choice of the power components.
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APPLICATION NOTE
Introduction
input bridge and the bulk capacitor. This intermediate stage
is designed to output a constant voltage while drawing
a sinusoidal current from the line. In practice, the step-up (or
boost) configuration is adopted, as this type of converter is
easy to implement. One can just notice that this topology
requires the output to be higher than the input voltage. That
is why the output regulation level is generally set to around
400 V in universal mains conditions.
The IEC1000−3−2 specification, usually named Power
Factor Correction (PFC) standard, has been issued with the
goal of minimizing the Total Harmonic Distortion (THD) of
the current that is drawn from the mains. In practice, the
legislation requests the current to be nearly sinusoidal and in
phase with the AC line voltage.
Active solutions are the most effective means to meet the
legislation. A PFC pre-regulator is inserted between the
BASICS OF THE CRITICAL CONDUCTION MODE
• Zero Current Turn On: One Major Benefit of Critical
Critical conduction mode (or border line conduction
mode) operation is the most popular solution for low power
applications. Characterized by a variable frequency control
scheme in which the inductor current ramps to twice the
desired average value, ramps down to zero, then
immediately ramps positive again (refer to Figures 2 and 4),
this control method has the following advantages:
• Simple Control Scheme: The Application Requires Few
External Components
• Ease of Stabilization: The Boost Keeps the First Order
Converter and There is No Need for Ramp
Compensation
Diode Bridge
Conduction Mode is the MOSFET Turn On when the
Diode Current Reaches Zero. Therefore the MOSFET
Switch On is Lossless and Soft and there is No Need
for a Low trr Diode
On the other hand, the critical conduction mode has some
disadvantages:
• Large Peak Currents that Result in High dl/dt and rms
Currents Conducted throughout the PFC Stage
• Large Switching Frequency Variations as Detailed in
the Paper
PFC Stage
Power Supply
+
AC
Line
+ Bulk
Capacitor
Controller
IN
LOAD
−
Figure 1. Power Factor Corrected Power Converter
PFC boost pre-converters typically require a coil, a diode and a Power Switch. This stage also needs a Power Factor Correction controller
that is a circuit specially designed to drive PFC pre-regulators. ON Semiconductor has developed three controllers (MC33262, MC33368 and
MC33260) that operate in critical mode and the NCP1650 for continuous mode applications.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1
Publication Order Number:
AND8123/D
AND8123/D
One generally devotes critical conduction mode to power factor control circuits below 300 W.
Diode Bridge
Diode Bridge
+
L
Icoil
+
Icoil
L
Vin
+
Vin
IN
Vout
IN
−
−
The power switch is ON
The power switch is OFF
The power switch being about zero, the input
voltage is applied across the coil. The coil current
linearly increases with a (Vin /L) slope.
Coil
Current
The coil current flows through the diode. The coil
voltage is (Vout −Vin ) and the coil current linearly decays
with a (Vout −Vin )/L slope.
Vin/L
(Vout−Vin)/L
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
Icoil_pk
Figure 2. Switching Sequences of the PFC Stage
• The controller multiplies the shaping information by
In critical discontinuous mode, a boost converter presents
two phases (refer to Figure 2):
• The on-time during which the power switch is on.
The inductor current grows up linearly according to
a slope (Vin/L) where Vin is the instantaneous input
voltage and L the inductor value.
• The off time during which the power switch is off.
The inductor current decreases linearly according to the
slope (Vout−Vin)/L where Vout is the output voltage.
This sequence terminates when the current equals zero.
•
•
Consequently, a triangular current flows through the coil.
The PFC stage adjusts the amplitude of these triangles so
that in average, the coil current is a (rectified) sinusoid (refer
to Figure 4). The EMI filter (helped by the 100 nF to 1.0 mF
input capacitor generally placed across the diodes bridge
output), performs the filtering function.
The more popular scheme to control the triangles
magnitude and shape the current, forces the inductor peak
current to follow a sinusoidal envelope. Figure 3
diagrammatically portrays its operation mode that could be
summarized as follows:
• The diode bridge output being slightly filtered,
the input voltage (Vin) is a rectified sinusoid. One pin
of the PFC controller receives a portion of Vin.
The voltage of this terminal is the shaping information
necessary to build the current envelope.
• An error amplifier evaluates the power need in response
to the error it senses between the actual and wished
levels of the output voltage. The error amplifier
bandwidth is set low so that the error amplifier output
reacts very slowly and can be considered as a constant
within an AC line period.
the error amplifier output voltage. The resulting product
is the desired envelope that as wished, is sinusoidal, in
phase with the AC line and whose amplitude depends
on the amount of power to be delivered.
The controller monitors the power switch current.
When this current exceeds the envelope level, the PWM
latch is reset to turn off the power switch.
Some circuitry detects the core reset to set the PWM
latch and initialize a new MOSFET conduction phase
as soon as the coil current has reached zero.
Consequently, when the power switch is ON, the current
ramps up from zero up to the envelope level. At that
moment, the power switch turns off and the current ramps
down to zero (refer to Figures 2 and 4). For simplicity of the
drawing, Figure 4 only shows 8 “current triangles”.
Actually, their frequency is very high compared to the AC
line one. The input filtering capacitor and the EMI filter
averages the “triangles” of the coil current, to give:
t Icoil u T +
Icoil_pk
2
(eq. 1)
where <Icoil>T is the average of one current triangle
(period T) and Icoil_pk is the peak current of this triangle.
As Icoil_pk is forced to follow a sinusoidal envelop
(k*Vin), where k is a constant modulated by the error
amplifier, <Icoil>T is also sinusoidal:
ǒ
t Icoil u T + k * Vin +
2
k * Ǹ2 * Vac * sin(wt)
2
Ǔ
(eq. 2)
As a result, this scheme makes the AC line current
sinusoidal.
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2
AND8123/D
PFC Stage
Vin
L1
D1
Bulk
Capacitor
Input
Filtering
Capacitor
AC Line
+
C1
X1
R7
Current Sensing
Resistor
PWM Latch
Zero Current
Detection
S
Output Buffer
Q
+
R
Current
Envelope
Current Sense
Comparator
C2
R1
R2
Error
Amplifier
Multiplier
+
R3
Vref
R4
Figure 3. Switching Sequences of the PFC Stage
The controller monitors the input and output voltages and using this information and a multiplier, builds a sinusoidal envelope. When the
sensed current exceeds the envelope level, the Current Sense Comparator resets the PWM latch and the power switch turns off. Once
the core has reset, a dedicated block sets the PWM latch and a new MOSFET conduction time starts.
Peak
Icoil_pk
Average (<Icoil>T)
Inductor Current
(Icoil)
T
Tac/2
(Tac is the
AC line period)
MOSFET
DRIVE
Figure 4. Coil Current
During the power switch conduction time, the current ramps up from zero up to the envelope level. At that moment, the power switch turns
off and the current ramps down to zero. For simplicity of the drawing, only 8 “current triangles” are shown. Actually, their frequency is very
high compared to the AC line one.
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3
AND8123/D
One can note that a simple calculation would show that the on-time is constant over the sinusoid: ton + 2 * L * t Pin u and
Vac2
that the switching frequency modulation is brought by the off-time that equals:
toff + 2 * Ǹ2 * L *
Ǹ2 * Vac * sin(wt)
t Pin u
* sin(wt) + ton *
Ǹ
Vac * (Vout * 2 * Vac * sin(wt))
Vout * Ǹ2 * Vac * sin(wt)
That is why the MC33260 developed by ON Semiconductor
does not incorporate a multiplier inputting a portion of the
rectified AC line to shape the coil current. Instead, this part
(eq. 3)
forces a constant on-time to achieve in a simplest manner, the
power factor correction.
MAIN EQUATIONS
Switching Frequency
•
As shown in the next paragraph (equation 17), the coil
peak current can be expressed as a function of the input
power and the AC line rms voltage as follows:
As already stated, the coil current consists of two phases:
The power switch conduction time (ton). During this
time, the input voltage applies across the coil and the
current increases linearly through the coil with
a (Vin/L) slope:
Icoil(t) + Vin * t
L
Icoil_pk + 2 * Ǹ2 * t Pin u * sin(wt)
Vac
Where w is the AC line angular frequency. Replacing
Icoil_pk by this expression in equation (9) leads to:
(eq. 4)
T + 2 * Ǹ2 * L *t Pin u * sin(wt)
Vac
Vout
*
Ǹ2 * Vac * sin(wt) * (Vout * Vin)
This phase ends when the conduction time (ton) is
complete that is when the coil current has reached its peak
value (Icoil_pk). Thus:
Icoil_pk + Vin * ton
L
(eq. 5)
T + 2 * L *t Pin u * Vout
Vac2 * (Vout * Vin)
(eq. 6)
phase, the coil current flows through the output diode
and feeds the output capacitor and the load. The diode
voltage being considered as null when on, the voltage
across the coil becomes negative and equal to
(Vin−Vout). The coil current decreases then linearly with
the slope ((Vout−Vin)/L) from (Icoil_pk) to zero, as
follows:
ǒ
Ǔ
f+
L * Icoil_pk
Vout * Vin
Ǔ
(eq. 13)
Ǔ that only varies versus the
• One term ǒ2 * L Vac
*t Pin u
2
working point (load and AC line rms voltage).
(eq. 7)
• A modulation factor
ǒ
1*
Ǹ2 * Vac * sin(wt)
Vout
Ǔ
that
makes the switching frequency vary within the AC line
sinusoid.
(eq. 8)
The following figure illustrates the switching frequency
variations versus the AC line amplitude, the power and
within the sinusoid.
The total current cycle (and then the switching period, T)
is the sum of ton and toff. Thus:
T + ton ) toff + L * Icoil_pk *
ǒ
Ǹ2 * Vac * sin(wt)
Vac2
1*
Vout
2 * L *t Pin u
This equation shows that the switching frequency consists
of:
This phase ends when Icoil reaches zero, then the off−time
is given by the following equation:
toff +
(eq. 12)
The switching frequency is the inverse of the switching
period. Consequently:
• The power switch off time (toff). During this second
Icoil(t) + Icoil_pk * Vout * Vin * t
L
(eq. 11)
This equation simplifies:
The conduction time is then given by:
L * Icoil_pk
ton +
Vin
(eq. 10)
Vout
(eq. 9)
Vin * (Vout * Vin)
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AND8123/D
2.50
1.5
2.00
1.0
f / f(90)
sin (wt)
1.50
0.5
1.00
f
0.50
80
110
140
170
200
Vac, (V)
230
260
0
290
0
1.0
2.0
3.0
wt
Figure 5. Switching Frequency Over the AC Line
RMS Voltage (at the Sinusoid top)
Figure 7. Switching Frequency Over the AC Line
Sinusoid @ 230 Vac
The figure represents the switching frequency variations versus
the line rms voltage, in a normalized form where f(90) = 1. The plot
drawn for Vout = 400 V, shows large variations (200% at Vac =
180 V, 60% at Vac = 270 V). The shape of the curve tends to flatten
if Vout is higher. However, the minimum of the switching frequency
is always obtained at one of the AC line extremes (VacLL or VacHL
where VacLL and VacHL are respectively, the lowest and highest
Vac levels).
This plot gives the switching variations over the AC line sinusoid
at Vac = 230 V and Vout = 400 V, in a normalized form where f is
taken equal to 1 at the AC line zero crossing. The switching
frequency is approximately divided by 5 at the top of the sinusoid.
1.5
20
1.0
f / f(200W)
sin (wt)
f
0.5
10
0
0
1.0
2.0
3.0
wt
Figure 8. Switching Frequency Over the AC Line
Sinusoid @ 90 Vac
0
0
50
100
150
200
Pin (W)
This plot shows the same characteristic but for Vac = 90 V.
Similarly to what was observed in Figure 5 (f versus Vac), the
higher the difference between the output and input voltages, the
flatter the switching frequency shape.
Figure 6. Switching Frequency vs. the Input Power
(at the Sinusoid top)
This plot sketches the switching frequency variations versus the
input power in a normalized form where f(200 W) = 1. The
switching frequency is multiplied by 20 when the power is 10 W.
In practice, the PFC stage propagation delays clamp the
switching frequency that could theoretically exceed several
megaHertz in very light load conditions. The MC33260 minimum
off-time limits the no load frequency to around 400 kHz.
Finally, the switching frequency dramatically varies
within the AC line and versus the power. This is probably the
major inconvenience of the critical conduction mode
operation. This behavior often makes tougher the EMI
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5
AND8123/D
In light load conditions, the switching period can become as
low as 2.0 ms (500 kHz). All the propagation delays within
the control circuitry or the power switch reaction times are
no more negligible, what generally distorts the current
shape. The power factor is then degraded.
The switching frequency variation is a major limitation of
the system that should be reserved to application where the
load does not vary drastically.
filtering. It also can increase the risk of generating
interference that disturb the systems powered by the PFC
stage (for instance, it may produce some visible noise on the
screen of a monitor).
In addition, the variations of the frequency and the high
values it can reach (up to 500 kHz) practically prevent the
use of effective tools to damp EMI and reduce noise like
snubbing networks that would generate too high losses.
One can also note that the frequency increases when the
power diminishes and when the input voltage increases.
COIL PEAK AND RMS CURRENTS
Coil Peak Current
From this equation, one can easily deduct that the peak
coil current is maximum when the required power is
maximum and the AC line at its minimum voltage:
As the PFC stage makes the AC line current sinusoidal and
in phase with the AC line voltage, one can write:
lin(t) + Ǹ2 * lac * sin(wt)
Icoil_max + 2 * Ǹ2 * t Pin u max
VacLL
(eq. 14)
where Iin(t) is the instantaneous AC line current and Iac its
rms value.
Provided that the AC line current results from the
averaging of the coil current, one can deduct the following
equation:
Icoil_pk
lin(t) +t Icoil u T +
2
where <Pin>max is the maximum input power of the
application and VacLL the lowest level of the AC line
voltage.
Coil RMS Current
The rms value of a current is the magnitude that squared,
gives the dissipation produced by this current within a 1.0 W
resistor. One must then compute the rms coil current by:
• First calculating the “rms current” within a switching
period in such a way that once squared, it would give
the power dissipated in a 1.0 W resistor during the
considered switching period.
• Then the switching period being small compared to the
input voltage cycle, regarding the obtained expression
as the instantaneous square of the coil current and
averaging it over the rectified sinusoid cycle, to have
the squared coil rms current.
(eq. 15)
where <Icoil>T is the average of the considered coil current
triangle over the switching period T and Icoil_pk is the
corresponding peak.
Thus, the peak value of the coil current triangles follows
a sinusoidal envelope and equals:
Icoil_pk + 2 * Ǹ2 * lac * sin(wt)
(eq. 16)
Since the PFC stage forces the power factor close to 1, one
can use the well known relationship linking the average
input power to the AC line rms current and rms voltage
(t Pin u+ Vac * lac) and the precedent equation leads to:
Icoil_pk + 2 * Ǹ2 * t Pin u * sin(wt)
Vac
This method will be used in this section. As above
explained, the current flowing through the coil is:
• (IM(t) + Vin * tńL + Icoil_pk * tńton) during the
MOSFET on−time, when 0 < t < ton.
(eq. 17)
The coil current peak is maximum at the top of the
sinusoid where sin(ùt) + 1. This maximum value,
(Icoil_pk)H, is then:
(Icoil_pk)H + 2 * Ǹ2 * t Pin u
Vac
(eq. 19)
•
(eq. 18)
(ID(t) + Icoil_pk−NJ(Vout−Vin) * tńLNj + Icoil_pk * (T * t)ń
(T * ton) ) during the diode conduction time, that is,
when ton < t < T.
Therefore, the rms value of any coil current triangle over the corresponding switching period T, is given by the following
equation:
t (Icoil)rms u T +
Ǹǒ
1*
T
2
T
2
Icoil_pk * t
ƪ
ƫ
* dt ) ŕ ƪIcoil_pk * T * t ƫ * dtǓ
ton
T * ton
ton
0
ton
ŕ
(eq. 20)
Solving the integrals, it becomes:
t (Icoil)rms u T +
Ǹ ǒƪ
1*
T
(eq. 21)
ƫ
ƪ
Icoil_pk2 ton3
* (T * ton)
*
)
*
3
3 * Icoil_pk
ton2
3
ƫ
ǒƪIcoil_pk * TT**tonT ƫ3 * ƪIcoil_pk * TT ** ton
ǓƫǓ
ton
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AND8123/D
The precedent simplifies as follows:
t (Icoil)rms u T +
Ǹǒ
ƪ
1 * Icoil_pk2 * ton ) * (T * ton) * (* Icoil_pk3)
3
T
3 * Icoil_pk
Ǹ
(eq. 23)
ǒ
Ǔ
1 * ton ) T * ton
3
3
T
Calculating the term under the root square sign, the
following expression is obtained:
t (Icoil)rms u T +
Icoil_pk
Ǹ3
(eq. 24)
Replacing the coil peak current by its expression as
a function of the average input power and the AC line rms
voltage (equation 17), one can write the following equation:
t (Icoil)rms u T + 2 *
Pin u * sin(wt)
Ǹ23 * t Vac
(eq. 22)
gives the resistive losses at this given Vin. Now to have the
rms current over the rectified AC line period, one must not
integrate <(Icoil)rms>T but the square of it, as we would
have proceeded to deduct the average resistive losses from
the dissipation over one switching period. However, one
must not forget to extract the root square of the result to
obtain the rms value.
As the consequence, the coil rms current is:
Rearrangement of the terms leads to:
t (Icoil)rms u T + Icoil_pk *
ƫǓ
(Icoil)rms +
Ǹ
(eq. 26)
2 *
Tac
Tacń2
ŕ
0
t (Icoil)rms u T 2 * dt
where Tac = 2*p/w is the AC line period (20 ms in Europe,
16.66 ms in USA). The PFC stage being fed by the rectified
AC line voltage, it operates at twice the AC line frequency.
That is why, one integrates over half the AC line period
(Tac/2).
(eq. 25)
This equation gives the equivalent rms current of the coil
over one switching period, that is, at a given Vin. As already
stated, multiplying the square of it by the coil resistance,
Substitution of equation (25) into the precedent equation leads to:
(Icoil)rms +
Ǹ
2 *
Tac
Tacń2
ŕ
0
ƪ Ǹ
2*
Pin u * sin(wt),
Ǹ23 * t Vac
Pin u). The rms value of such a sinusoidal
Ǹ23 * t Vac
current is well known (the amplitude divided by Ǹ2).
Therefore:
Icoil(rms) + 2 * t Pin u
Ǹ3
Vac
2
* dt
(eq. 27)
The switching losses are difficult to determine with
accuracy. They depend of the MOSFET type and in
particular of the gate charge, of the controller driver
capability and obviously of the switching frequency that
varies dramatically in a critical conduction mode operation.
However, one can make a rough estimation if one assumes
the following:
• The output voltage is considered as a constant. The
output voltage ripple being generally less than 5% the
nominal voltage, this assumption seems reasonable.
• The switching times (dt and tFR, as defined in
Figure 9), are considered as constant over the sinusoid.
that is, the rms
value of a sinusoidal current whose magnitude is
(2 *
ƫ
Switching Losses
This equation shows that the coil rms current is the rms
value of: 2 *
2 * t Pin u * sin(wt)
3
Vac
(eq. 28)
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AND8123/D
Dissipated Power:
(IMOSFET * Vdrain)
tFR
IMOSFET
Vdrain
dt
Figure 9. Turn Off Waveforms
where: dt and tFR are the switching times portrayed by
Figure 9 and T is the switching period.
Figure 9 represents a turn off sequence. One can observe
three phases:
• During approximately the second half of the gate
voltage Miller plateau, the drain−source voltage
increases linearly till it reaches the output voltage.
• During a short time that is part of the diode forward
recovery time, the MOSFET faces both maximum
voltage and current.
• The gate voltage drops (from the Miller plateau) below
the gate threshold and the drain current ramps down
to zero.
Equation (9) gives an expression linking the coil peak
current and the switching period of the considered current
cycle (triangle): T +
Substitution of equation (9) into the equation (29) leads
to:
psw +
Therefore, one can write:
ǒ
(eq. 29)
Ǔ ǒ
Rearranging the terms, one obtains:
t psw u+
dt ) tFR
*
2*L
ǒ
ȡ
ȥ
Ȣ
2 *
Tac
(eq. 30)
(eq. 31)
Ǔ
t psw u+ 2 *
Tac
Tacń2
ŕ
Vin * (Vout * Vin) * (dt ) tFR)
2*L
This equation shows that the switching losses over
a switching period depend of the instantaneous input
voltage, the difference between the instantaneous output and
input voltages, the switching time and the coil value. Let’s
calculate the average losses (<psw>) by integrating psw
over half the AC line period:
“dt” of Figure 9 represents the total time of the three phases,
“tFR’’ the second phase duration.
Vout * Icoil_pk dt−tFR
t
psw +
*
) Vout * Icoil_pk * FR
2
T
T
L * Icoil_pk
Vout
*
.
Vin
Vout * Vin
Vin * Vout * dt
0
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Ǔǒ
*
Tacń2
2 *
Tac
ŕ
0
Vin * (Vout * Vin) * (dt ) tFR)
* dt
2*L
Tacń2
ŕ
0
ǓȣȦȤ
Vin2 * dt
(eq. 32)
AND8123/D
t psw u+
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
(Vac2 + 2 *
Tac
Tacń2
ŕ
Vin2 * dt). Applying this, it becomes:
0
(eq. 33)
ǒ
Ǔ
dt ) tFR
2 * Ǹ2 * Vac * Vout
*
* Vac2
p
2*L
Or in a simpler manner:
ǒ
2 * (dt ) tFR) * Vac2
Vout * p
t psw u+
*
Ǹ2 * Vac 4
p*L
Ǔ
(eq. 34)
QT
VDS
9
VGS
6
Q2
Q1
3
ID = 2.3 A
TJ = 25°C
Q3
0
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
12
Vout being considered as a constant, one can easily solve
this equation if one remembers that the input voltage
average
value
is
(2 * Ǹ2 * Vacńp)
and
that
QT, TOTAL GATE CHARGE (nC)
Figure 10. Typical Total Gate Charge Specification
of a MOSFET
The coil inductance (L) plays an important role: the losses
are inversely proportional to this value. It is simply because
the switching frequency is also inversely proportional to L.
This equation also shows that the switching losses are
independent of the power level. One could have easily
predict this result by simply noting that the switching
frequency increased when power diminished.
Equation (34) also shows that the lower the ratio
(Vout/Vac), the smaller the MOSFET switching losses. That
is because the “Follower Boost” mode that reduces the
difference between the output and input voltages, lowers the
switching frequency. In other words, this technique enables
the use of a smaller coil for the same switching frequency
range and the same switching losses.
For instance, the MC33260 features the “Follower Boost”
operation where the pre-converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
minimize the cost of the PFC stage 1.
How to extract dt and tFR?
• The best is to measure them.
• One can approximate dt as the time necessary to extract
the gate charge Q3 of the MOSFET (refer to Figure 10).
Q3 being not always specified, instead, one can take
the sum of Q1 with half the Miller plateau gate charge
(Q2/2). Knowing the drive capability of the circuit,
one can deduct the turn off time (dt = Q3/Idrive or dt =
[Q1 + (Q2/2)]/Idrive).
• In a first approach, tFR can be taken equal to the diode
forward recovery time.
One must note that the calculation does not take into
account:
• The energy consumed by the controller to drive the
MOSFET (Qcc*Vcc*f), where Qcc is the MOSFET
gate charge necessary to charge the gate voltage to Vcc,
Vcc the driver supply voltage and f the switching
frequency.
• The energy dissipated because of the parasitic
capacitors of the PFC stage. Each turn on produces an
abrupt voltage change across the parasitic capacitors of
the MOSFET drain−source, the diode and the coil. This
results in some extra dissipation across the MOSFET
(1/2*Cparasitic*DV2*f), where Cparasitic is the
considered parasitic capacitor and DV the voltage
change across it.
1
Refer to MC33260 data sheet for more details at
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However, equation (34) should give a sufficient first
approach approximation in most applications where the two
listed sources of losses play a minor role. Nevertheless, the
losses produced by the parasitic capacitors may become
significant in light load conditions where the switching
frequency gets high. As always, bench validation is key.
Power MOSFET Conduction Losses
As portrayed by Figure 4, the coil current is formed by
high frequency triangles. The input capacitor together with
the input RFI filter integrates the coil current ripple so that
the resulting AC line current is sinusoidal.
During the on-time, the current rises linearly through the
power switch as follows:
Icoil(t) + Vin * t
L
(eq. 35)
where Vin is the input voltage (Vin + Ǹ2 * Vac * sin(wt) ), L
is the coil inductance and t is the time.
www.onsemi.com
9
AND8123/D
During the rest of the switching period, the power switch is off. The conduction losses resulting from the power dissipated
by Icoil during the on-time, one can calculate the power during the switching period T as follows:
ton
pT + 1 *
T
ŕ
ton
ŕ
Ron * Icoil(t)2 * dt + 1 *
T
0
Ǔ
(eq. 36)
• Either noting that the off-time (toff) can be expressed as
Solving the integral, equation (36) simplifies as follows:
(eq. 37)
•
2 ton
2
3
pT + Ron * Vin * ŕ t2 * dt + 1 * Ron * Vin * ton
3
T
L
L
T
0
ǒ Ǔ
As the coil current reaches its peak value at the end of the
on-time, Icoil_pk + Vin * tonńL and the precedent equation
can be rewritten as follows:
pT + 1 * Ron * Icoil_pk2 * ton
3
T
ǒ
One can calculate the duty cycle (d = ton/T) by:
where Ron is the MOSFET on-time drain source resistor, ton
is the on-time.
ǒ Ǔ
0
2
Ron * Vin * t * dt
L
a function of ton (refer to equation 3) and substituting
this equation into (T = ton + Toff),
Or considering that the critical conduction mode being
at the border of the continuous conduction mode
(CCM), the expression giving the duty-cycle in a CCM
boost converter applies.
Both methods lead to the same following result:
d + ton + 1 * Vin
T
Vout
(eq. 38)
(eq. 39)
Substitution of equation (39) into equation (38) leads to:
One can recognize the traditional equation permitting to
calculate the MOSFET conduction losses in a boost or
ǒ
Ǔ
pT + 1 * Ron * Icoil_pk2 * 1 * Vin
3
Vout
a flyback ( 1 * Ron * Ipk2 * d, where Ipk is the peak current
3
(eq. 40)
One can note that the coil peak current (Icoil_pk) that
follows a sinusoidal envelop, can be written as follows:
and d, the MOSFET duty cycle).
Icoil_pk + 2 * Ǹ2 * t Pin u * sin(wt) (refer to equation 17).
Vac
Replacing Vin and Icoil_pk by their sinusoidal expression, respectively (Ǹ2 * Vac * sin(wt) ) and (2 * Ǹ2 * t Pin u * sin(wt) ),
Vac
equation (40) becomes:
ǒ
Ǹ2 * Vac * sin(wt)
2
pT + 1 * Ron * 2 * Ǹ2 * t Pin u * sin(wt) * 1 *
3
Vout
Vac
ǒ
Ǔ
That is in a more compact form:
ǒ
Ǔ
ƪ
ǒ
Ǹ2 * Vac
2
pT + 8 * Ron * t Pin u * sin 2(wt) *
* sin 3(wt)
3
Vac
Vout
Ǔ
(eq. 41)
Ǔƫ
(eq. 42)
Equation (42) gives the conduction losses at a given Vin voltage. This equation must be integrated over the rectified AC line
sinusoid to obtain the average losses:
ǒ
Ǔ
2
t p u Tac + 8 * Ron * t Pin u * 2 *
3
Vac
Tac
Tacń2
ŕ
•
sin 2(a) +
sin 2(wt) *
0
If the average value of sin2(wt) is well known (0.5), the
calculation of <sin3(wt)> requires few trigonometry
remembers:
ƪ
•
ǒ
Ǹ2 * Vac
* sin 3(wt)
Vout
sin(a) * cos(b) +
Ǔƫ
(eq. 43)
* dt
sin(a ) b) ) sin(a * b)
2
Combining the two precedent formulas, one can obtain:
1 * cos(2a)
2
sin 3(wt) +
3 * sin(wt) sin(3wt)
*
4
4
(eq. 44)
Substitution of equation 44) into equation (43) leads:
ǒ
Ǔ
2
t p u Tac + 8 * Ron * t Pin u * 2 *
3
Vac
Tac
Tacń2
ŕ
0
ƪ
sin(wt)2 *
ǒ
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10
Ǔ ǒ
Ǹ2 * Vac
3 * Ǹ2 * Vac
* sin(wt) )
* sin(3wt)
4 * Vout
4 * Vout
Ǔƫ
* dt
(eq. 45)
AND8123/D
Solving the integral, it becomes:
ǒ
ƪ ǒ
Ǔ
Ǔ ǒ
Ǹ2 * Vac 2
2
3 * Ǹ2 * Vac 2
t p u Tac + 8 * Ron * t Pin u * 1 *
*p )
*
2
3
Vac
4 * Vout
4 * Vout 3p
Equation (46) simplifies as follows:
ǒ
Ǔ
ƪ ǒ
Ǔƫ
(eq. 46)
Ǔƫ
2
8 * Ǹ2 * Vac
t p u Tac + 4 * Ron * t Pin u * 1 *
3
Vac
3p * Vout
This formula shows that the higher the ratio (Vac/Vout),
the smaller the MOSFET conduction losses. That is why the
“Follower Boost” mode that reduces the difference between
the output and input voltages, enables to reduce the
MOSFET size.
For instance, the MC33260 features the “Follower Boost”
operation where the pre-converter output voltage stabilizes
at a level that varies linearly versus the AC line amplitude.
This technique aims at reducing the gap between the output
and input voltages to optimize the boost efficiency and
minimize the cost of the PFC stage2.
By the way, one can deduct from this equation the rms
current ((IM)rms) flowing through the power switch
knowing that t p u Tac + Ron * (IM)2rms :
(IM)rms + 2 * t Pin u *
Ǹ3
Vac
Ǹ
ǒ
8 * Ǹ2 * Vac
1*
3p * Vout
Ǔ
(eq. 47)
The MC33260 monitors the whole coil current by
monitoring the voltage across a resistor inserted between
ground and the diodes bridge (negative sensing – refer to
Figure 15). The circuit utilizes the current information for
both the overcurrent protection and the core reset detection
(also named zero current detection). This technique brings
two major benefits:
• No need for an auxiliary winding to detect the core
reset. A simple coil is sufficient in the PFC stage.
• The MC33260 detects the in-rush currents that may
flow at start-up or during some overload conditions and
prevents the power switch from turning on in that
stressful condition. The PFC stage is significantly safer.
Some increase of the power dissipated by the current
sense resistor is the counter part since the whole current is
sensed while circuits like the MC33262 only monitor the
power switch current.
(eq. 48)
Dissipation within the Current Sense Resistor
Dissipation of the Current Sense Resistor in MC33262
Like Circuits
PFC controllers monitor the power switch current either
to perform the shaping function or simply to prevent it from
being excessive. That is why a resistor is traditionally placed
between the MOSFET source and ground to sense the power
switch current.
Since the same current flows through the current sense
resistor and the power switch, the calculation is rather easy.
One must just square the rms value of the power switch
current (IM)rms calculated in the previous section and
multiply the result by the current sense resistance.
2
Refer to MC33260 data sheet for more details at
www.onsemi.com
Doing this, one obtains:
ǒ
Ǔ
ƪ ǒ
Ǔƫ
2
8 * Ǹ2 * Vac
t pRs u 262 + 4 * Rs * t Pin u * 1 *
3
Vac
3p * Vout
where <pRs>262 is the power dissipated by the current
sense resistor Rs.
Consequently:
ǒ
Comparison of the Losses Amount in the Two Cases
Let’s calculate the ratios: t pRs u 262ń t pRs u 260 .
In this case, the current sense resistor Rs derives the whole
coil current. Consequently, the product of Rs by the square
of the rms coil current gives the dissipation of the current
sense resistor:
One obtains:
t pRs u 262ń t pRs u 260 + 1 *
(eq. 50)
where Icoil(rms) is the coil rms current that as expressed by
ǒ
(eq. 52)
8 * Ǹ2 * Vac
3p * Vout
Ǔ
If one considers that (8/3 p) approximately equals 0.85,
the precedent equation simplifies:
equation (28), equals: Icoil(rms) + Ǹ2 * t Pin u .
3
Ǔ
2
(eq. 51)
t pRs u 260 + 4 * Rs * t Pin u
3
Vac
Dissipation of the Current Sense Resistor in MC33260
Like Circuits
t pRs u 260 + Rs * (Icoil(rms) )2
(eq. 49)
Vac
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11
AND8123/D
ƪ
t pRs u 262 ń t pRs u 260 [ 1 * 0.85 * Vm (eq. 53)
Vout
where Vm is the AC line amplitude.
The diode average current can be easily computed if one
notes that it is the sum of the load and output capacitor
currents:
Id(rms)T +
Then, in average:
Id(rms)T + 2 *
(eq. 55)
t Id u+t Iload ) ICout u+t Iload u )t ICout u
(eq. 59)
Pin u * Ǹtoff * sin(wt)
Ǹ23 * t Vac
T
(eq. 60)
In addition, one can easily show that toff and T are linked
by the following equation:
At the equilibrium, the average current of the output
capacitor must be 0 (otherwise the capacitor voltage will be
infinite). Thus:
Ǹ2 * Vac * sin(wt)
toff + T * Vin + T *
Vout
Vout
(eq. 56)
(eq. 61)
Consequently, equation (60) can be changed into:
The rms diode current is more difficult to calculate.
Similarly to the computation of the rms coil current for
instance, it is necessary to first compute the squared rms
current at the switching period level and then to integrate the
obtained result over the AC line sinusoid.
As portrayed by Figure 4, the coil discharges during the
off time. More specifically, the current decays linearly
through the diode from its peak value (Icoil_pk) down to
zero that is reached at the end of the off-time. Taking the
beginning of the off-time as the time origin, one can then
write:
Icoil(t) + Icoil_pk * toff−t
toff
Ǹ3toff* T * Icoil_pk
Substitution of equation (17) that expresses Icoil_pk, into
the precedent equation leads to:
(eq. 54)
t Id u+t Iload u+ Pout
Vout
(eq. 58)
Solving the integral, one obtains the expression of the
“rms diode current over one switching period”:
Average and RMS Current through the Diode
Id + Iload ) ICout
ƫ
toff
2
Id(rms)2T + 1 * ŕ Icoil_pk * toff−t * dt
T 0
toff
Id(rms)T +
3
2 * Ǹ2 * Ǹ2 t Pin u ǒǸ
*
* sin(wt)Ǔ (eq. 62)
Ǹ3
ǸVac * Vout
This equation gives the equivalent rms current of the
diode over one switching period, that is, at a given Vin. As
already stated in the Coil Peak and RMS Currents section,
the square of this expression must be integrated over
a rectified sinusoid period to obtain the square of the diode
rms current.
Therefore:
Tacń2
Id(rms)2 + 2 *
Tac
(eq. 57)
Similarly to the calculation done to compute the coil rms
current, one can calculate the “diode rms current over one
switching period”:
ŕ
0
(eq. 63)
8 * Ǹ2 t Pin u2
*
* sin 3(wt) * dt
3
Vac * Vout
Similarly to the Power MOSFET Conduction Losses section, the integration of (sin3 (wt)) requires some preliminary
trigonometric manipulations:
sin 3(wt) + sin(wt) * sin 2(wt) + sin(wt) *
ǒ1 * cos(2wt)
Ǔ + 12 * sin(wt) * 12 * sin(wt) * cos(2wt)
2
And :
sin(wt) * cos(2wt) + 1 * (sin(−wt) ) sin(4wt) )
2
Then :
sin 3(wt) + 3 * sin(wt) * 1 * sin(3wt)
4
4
Consequently, equation (63) can change into:
Tacń2
Id(rms)2 + 2 *
Tac
One can now solve the integral and write:
ŕ
0
ƪ
ƫ
3 * sin(wt) sin(3wt)
8 * Ǹ2
Pin2
*
*
*
* dt
4
4
3
Vac * Vout
ǒ
16 * Ǹ2 t Pin u 2 3 * (cos(w0) * cos(wTacń2) ) cos(3wTacń2) * cos(3w0)
Id(rms)2 +
*
*
)
4w
12w
3 * Tac Vac * Vout
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12
(eq. 64)
Ǔ
(eq. 65)
AND8123/D
As (ù * Tac + 2p), we have:
ǒ
3 * (1− cos(p) )
cos(p)−1
16 * Ǹ2
Pin2
Id(rms)2 +
*
*
)
3
Vac * Vout
4w * Tac
12w * Tac
(eq. 66)
PFC Stage
One can simplify the equation replacing the cosine
elements by their value:
ǒ
Ǔ
L
Ǔ
16 * Ǹ2 t Pin u2
(eq. 67)
Id(rms)2 +
*
* 6 * 1
3
Vac * Vout 8 * p 12 * p
Vout
D
Vin
I1
The square of the diode rms current simplifies as follows:
32 * Ǹ2 t Pin u2
Id(rms)2 +
*
9 * p Vac * Vout
I2
Ic
Load
DRV
Power
Switch
(eq. 68)
Finally, the diode rms current is given by:
Id(rms) + 4 *
3
Ǹ2 * Ǹ2
p
Figure 11. Output Capacitor Current
* t Pin u
ǸVac * Vout
(eq. 69)
One knows the first term (I1(rms)2). This is the diode rms
current calculated in the previous section. The second and
third terms are dependent of the load. One cannot compute
them without knowing the characteristic of this load.
Anyway, the second term (I2(rms)2) is generally easy to
calculate once the load is known. Typically, this is the rms
current absorbed by a downstream converter. On the other
hand, the third term is more difficult to determine as it
depends on the relative occurrence of the I1 and I2 currents.
As the PFC stage and the load (generally a switching mode
power supply) are not synchronized, this term even seems
impossible to predict. One can simply note that this term
tends to decrease the capacitor rms current and
consequently, one can deduct that:
Output Capacitor RMS Current
As shown by Figure 11, the capacitor current results from
the difference between the diode current (I1) and the current
absorbed by the load (I2):
Ic(t) + I1(t) * I2(t)
(eq. 70)
Thus, the capacitor rms current over the rectified AC line
period, is the rms value of the difference between I1 and I2
during this period. As a consequence:
Ic(rms)2 + 2 *
Tac
Tacń2
ŕ
(I1 * I2)2 * dt
(eq. 71)
0
Rearranging (I1−I2)2 leads to:
Ic(rms)2 + 2 *
Tac
ŕ
Ic(rms) v ǸI1(rms)2 ) I2(rms)2
(eq. 72)
Tacń2
[I12 ) I22 * (2 * I1 * I2)] * dt
Substitution of equation (69) that gives the diode rms
current into the precedent equation leads to:
0
Thus:
Ic(rms) v
(eq. 73)
Tacń2
Ic(rms)2 + I1(rms)2 ) I2(rms)2 * 4 * ŕ I1 * I2 * dt
Tac
0
Pin u2
Ǹ329 ** pǸ2* *t
) I2(rms)2
Vac * Vout
where I2(rms) is the load rms current.
If the load is resistive, I2 = Vout/R where R is the load resistance and equation (73) changes into:
ǒ
Ǔ
2
Ic(rms)2 + ń1(rms)2 ) Vout * 4 *
R
Tac
Tacń2
ŕ
0
ń1 * Vout * dt
R
(eq. 76)
Thus, the capacitor squared rms current is:
ǒ
Ǔ
2 2 * Vout
Ic(rms)2 + Id(rms)2 ) Vout
*t Id u
R
R
ǒ
Ǔ
ǒ
(eq. 77)
Ǔ
2
32 * Ǹ2 t Pin u2
*
) Vout * 2 * Vout * Pout
Ic(rms)2 +
R
R
Vout
9 * p Vac * Vout
(eq. 78)
As Pout = Vout2/R, the precedent equation simplifies as follows:
Ic(rms) +
Ǹƪ
ƫ
ǒ
(eq. 74)
Ǔ
2
32 * Ǹ2 t Pin u2
*
* Vout
9 * p Vac * Vout
R
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13
(eq. 79)
(eq. 75)
AND8123/D
You may find a more friendly expression in the literature:
This explanation assumes that the energy that is fed by the
PFC stage perfectly matches the energy drawn by the load
over each switching period so that one can consider that the
capacitive part of the bulk has a constant voltage and that
only the ESR creates some ripple.
In fact, there is an additional low frequency ripple which
is inherent to the Power Factor Correction. The input current
and voltage being sinusoidal, the power fed by the PFC stage
has a squared sinusoid shape. On the other hand, the load
generally draws a constant power. As a consequence, the
PFC pre-converter delivers an amount of power that
matches the load demand in average only. The output
capacitor compensates the lack (excess) of input power by
supplying (storing) the part of energy necessary for the
instantaneous matching. Figures 13 and 14 sketch this
behavior.
Ic(rms) + I2 , where I2 is the load current. This equation is
Ǹ2
an approximate formula that does not take into account the
switching frequency ripple of the diode current. Only the
low frequency current that generates the low frequency
ripple of the bulk capacitor (refer to the next section) is
considered (this expression can easily be found by using
equation (90) and computing Ibulk + Cbulk * dVoutńdt ).
Equation (79) takes into account both high and low
frequency ripples.
Output Voltage Ripple
The output voltage (or bulk capacitor voltage) exhibits
two ripples.
The first one is traditional to Switch Mode Power
Supplies. This ripple results from the way the output is fed
by current pulses at the switching frequency pace. As bulk
capacitors exhibit a parasitic series resistor (ESR – refer to
Figure 12), they cannot fully filter this pulsed energy source.
More specifically:
• During the on-time, the PFC MOSFET conducts and
no energy is provided to the output. The bulk capacitor
feeds the load with the current it needs. The current
together with the ESR resistor of the bulk capacitor
form a negative voltage –(ESR*I2), where I2 is the
instantaneous load current,
• During the off-time, the diode derives the coil current
towards the output and the current across the ESR
becomes ESR*(Id−I2), where Id is the instantaneous
diode current.
PFC Stage
Id
Vin
I2
Load
Ic
Driver
ESR
Bulk
Capacitor
Figure 12. ESR of the Output Capacitor
400 V
Vout (5 V/div)
h*Pin (40 W/div)
Load Power (100 W)
Vin (100 V/div)
0V
Figure 13. Output Voltage Ripple
The dashed black line represents the power that is absorbed by the load. The PFC stage delivers a power that has a squared sinusoid shape.
As long as this power is lower than the load demand, the bulk capacitor compensates by supplying part of the energy it stores. Consequently
the output voltage decreases. When the power fed by the PFC pre-converter exceeds the load consumption, the bulk capacitor recharges.
The peak of the PFC power is twice the load demand.
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14
AND8123/D
Vout (5 V/div)
400 V
Ic (200 mA/div)
0A
Vin (100 V/div)
0V
Figure 14. Output Voltage Ripple
The output voltage equals its average value when the input voltage is minimum and maximum. The output voltage is lower than its average
value during the rising phase of the input voltage and higher during the input voltage decay. Similarly to the input power and voltage, the
frequency of the capacitor current (represented in the case of a resistive load) is twice the AC line one.
In this calculation, one does not consider the switching
ripple that is generally small compared to the low frequency
ripple. In addition, the switching ripple depends on the load
current shape that cannot be predicted in a general manner.
As already discussed, the average coil current over
a switching period is:
lin +
Ǹ2 *t Pin u
* sin(wt)
Vac
The instantaneous input power (averaged over the
switching period) is the product of the input voltage
(Ǹ2 * Vac * sin(ùt) ) by Iin. Consequently:
Pin + 2 *t Pin u * sin 2(wt)
(eq. 81)
In average over the switching period, the bulk capacitor
receives a charge current ( h * PinńVout), where h is the PFC
stage efficiency, and supplies the averaged load current
t I2 u+ h *t Pin u ń Vout. Applying the famous
“capacitor formula” I + C * dVńdt, it becomes:
(eq. 80)
h * Pin *t I2 u+ Cbulk * dVout
Vout
dt
Substitution of equation (81) into equation (82) leads to:
ǒ
dVout + 1 * 2 * h *t Pin u * sin 2(wt) * h *t Pin u
Vout
Vout
dt
Cbulk
Rearranging the terms of this equation, one can obtain:
Ǔ
(eq. 82)
(eq. 83)
Dividing the terms of the precedent equations by the
square of the average output voltage, it becomes:
h *t Pin u
Vout * dVout +
* ƪ 2 * sin 2(wt) * 1 ƫ (eq. 84)
dt
Cbulk
d(Vout2)
Noting that
+ 2 * Vout * dVout and that
dt
dt
cos(2wt) + 1−2 * sin 2(wt), one can deduct the square of the
h *t Pin u * sin(2wt)
ǒt Vout
Ǔ2 + 1 * Cbulk
Vout u
* w *t Vout u 2
(eq. 86)
Thus:
(eq. 87)
output voltage from the precedent equation:
−h *t Pin u
Vout2 *t Vout u 2 +
* sin(2wt) (eq. 85)
Cbulk * w
t Vout u ) dVout +
t Vout u
h *t Pin u * sin(2wt)
Ǹ1 * Cbulk
* w *t Vout u 2
Where dVout is the instantaneous output voltage ripple.
where <Vout> is the average output voltage.
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15
AND8123/D
Equation (87) can be rearranged as follows:
dVout +t Vout u*
ǒǸ
1*
(eq. 88)
h *t Pin u * sin(2wt)
Cbulk * w *t Vout u 2
Ǔ
*1
One can simplify this equation considering that the output voltage ripple is small compared to the average output voltage
(fortunately, it is generally true). This leads to say that the term
words, that
ǒǸ
1*
h *t Pin u * sin(2wt)
Cbulk * w *t Vout u 2
h *t Pin u * sin(2wt)
ǒCbulk
Ǔ is small compared to 1. Thus, one can write that:
* w *t Vout u 2
h *t Pin u * sin(2wt)
h t Pin u * sin(2wt)
Ǹ1 * Cbulk
[1*1*
2 Cbulk * w *t Vout u 2
* w *t Vout u 2
Substitution of equation (88) into equation (89), leads to
the simplified ripple expression that one can generally find
in the literature:
(dVout)pk−pk +
Ǔ
*1
is nearly zero or in other
(eq. 89)
h *t Pin u
(eq. 91)
Cbulk * w *t Vout u
And:
−h *t Pin u * sin(2wt)
(eq. 90)
2 * Cbulk * w *t Vout u
The maximum ripple is obtained when (sin(2ùt) + −1)
and minimum when (sin(2wt) + 1) . Thus, the peak-to-peak
dVout +
Vout +t Vout u *
(dVout)pk−pk
* sin(2wt) (eq. 92)
2
ripple that is the difference of these two values is:
CONCLUSION
Compared to traditional switch mode power supplies, one
faces an additional difficulty when trying to predict the
currents and voltages within a PFC stage: the sinusoid
modulation. This is particularly true in critical conduction
mode where the switching ripple cannot be neglected. As
proposed in this paper, one can overcome this difficulty by:
• First calculating their value within a switching period,
• Then the switching period being considered as very
small compared to the AC line cycle, integrating the
result over the sinusoid period.
The proposed theoretical analysis helps predict the stress
faced by the main elements of the PFC stages: coil,
MOSFET, diode and bulk capacitor, with the goal of easing
the selection of the power components and therefore, the
PFC implementation. Nevertheless, as always, it cannot
replace the bench work and the reliability tests necessary to
ensure the application proper operation.
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16
AND8123/D
Switching Frequency:
Peak Coil Current:
Icoil_pk + 2 * Ǹ2 * t Pin u * sin(wt)
Vac
f+
Maximum Peak Current:
Icoil_max + 2 * Ǹ2 * t Pin u max
VacLL
ǒ
Ǔ
Ǹ2 * Vac * sin(wt)
Vac2
1*
Vout
2 * L *t Pin u
Switching Losses:
t psw u[
RMS Coil Current:
Icoil(rms) + 2 * t Pin u
Ǹ3
Vac
ǒ
Ǔ
2 * (dt ) tFR) * Vac2
Vout * p
*
Ǹ2 * Vac 4
p*L
Conduction Losses:
ǒ
Ǔ
2
t Pon u+ 4 * Ron * t Pin u *
3
Vac
ƪ ǒ
1*
8 * Ǹ2 * Vac
3p * Vout
Ǔƫ
Average Diode Current:
t Id u+t Iload u+ Pout
Vout
RMS Diode Current:
Id(rms) + 4 *
3
Ǹ2 *pǸ2 * Ǹt Pin u
Vac * Vout
L1
D6
CONTROLLER
M1
AC Line
Iload
Vout
+
C1
LOAD
R7
R5
Capacitor Low Frequency Ripple:
(dVout)pk−pk +
MC33260 like Current Sense Resistor (Rs = R5)
Dissipation:
ǒ
Ǔ
RMS Capacitor Current:
2
t pRs u 260 + 4 * Rs * t Pin u
3
Vac
Ic(rms) v
MC33262 like Current Sense Resistor (Rs = R7)
Dissipation:
ǒ
Ǔ
2
t pRs u 262 + 4 * Rs * t Pin u *
3
Vac
Vac: AC line rms voltage
VacLL: Vac lowest level
w: AC line angular frequency
<Pin>: Average input power
<Pin>max: Maximum pin level
ƪ ǒ
h *t Pin u
Cbulk * w *t Vout u
8 * Ǹ2 * Vac
1*
3p * Vout
Ǔƫ
32 * Ǹ2 *t Pin u 2 ƪ
) Iload(rms) ƫ 2
9 * p * Vac * Vout
If load is resistive:
Vout: Output voltage
Pout: Output power
Iload: Load current
Iload(rms): RMS load current
h: Efficiency
Figure 15. Summary
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17
Ǹ
Ic(rms) +
Ǹƪ
ƫ
ǒ
Ǔ
2
32 * Ǹ2 t Pin u 2
*
* Vout
R
9 * p Vac * Vout
Ron: MOSFET on resistance
dt, tFR: Switching times (see Switching
Losses section and Figure 10)
Cbulk = C1: Bulk capacitor value
Rs: Current sense resistance
L: Coil inductance
AND8123/D
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