IRFR7546 Data Sheet (576 KB, EN)

StrongIRFET™
IRFR7546PbF
IRFU7546PbF
HEXFET® Power MOSFET
Application
 Brushed motor drive applications
 BLDC motor drive applications
 Battery powered circuits
 Half-bridge and full-bridge topologies
 Synchronous rectifier applications
 Resonant mode power supplies
 OR-ing and redundant power switches
 DC/DC and AC/DC converters
 DC/AC inverters
D
VDSS
60V
RDS(on) typ.
max
6.6m
ID (Silicon Limited)
71A
ID (Package Limited)
56A
G
S
7.9m
D
Benefits
 Improved gate, avalanche and dynamic dV/dt ruggedness
 Fully characterized capacitance and avalanche SOA
 Enhanced body diode dV/dt and dI/dt capability
 Lead-free, RoHS compliant
S
G
IRFR7546PbF
D-Pak
IRFU7546PbF
I-Pak
20
S
Source
Orderable Part Number
IRFR7546PbF
IRFR7546TRPbF
IRFU7546PbF
80
ID = 43A
Limited by package
15
T J = 125°C
10
5
T J = 25°C
0
60
40
20
0
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
1
D
Drain
Standard Pack
Form
Quantity
Tube
75
Tape and Reel
2000
Tube
75
ID, Drain Current (A)
RDS(on), Drain-to -Source On Resistance (m )
Package Type
S
D
I-Pak
IRFU7546PbF
D-Pak
IRFR7546PbF
G
Gate
Base part number
G
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25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 2. Maximum Drain Current vs. Case Temperature
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Absolute Maximum Rating
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current 
Maximum Power Dissipation
Linear Derating Factor
VGS
Gate-to-Source Voltage
TJ
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics Max.
71
50
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
Drain-to-Source Breakdown Voltage
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
RG
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Resistance
A 56
280
99
0.66
± 20
IDM
PD @TC = 25°C
Symbol
Parameter
EAS (Thermally limited)
Single Pulse Avalanche Energy 
EAS (Thermally limited)
Single Pulse Avalanche Energy 
IAR
Avalanche Current 
Repetitive Avalanche Energy 
EAR
Thermal Resistance Symbol
Parameter
Junction-to-Case 
RJC
Junction-to-Ambient (PCB Mount) 
RJA
Junction-to-Ambient 
RJA
Units
W
W/°C
V
-55 to + 175 °C 300
Max.
120
178
Units
mJ
A
mJ
See Fig 15, 16, 23a, 23b
Typ.
–––
–––
–––
Min.
60
–––
–––
–––
2.1
–––
–––
–––
–––
–––
Max.
1.52
50
110
Units
°C/W Typ. Max. Units
Conditions
––– –––
V VGS = 0V, ID = 250µA
47
––– mV/°C Reference to 25°C, ID = 1mA
6.6
7.9
m VGS = 10V, ID = 43A
8.5 –––
VGS = 6.0V, ID = 21A 

––– 3.7
V VDS = VGS, ID = 100µA
––– 1.0
VDS = 60V, VGS = 0V
µA
––– 150
VDS = 60V,VGS = 0V,TJ =125°C
––– 100
VGS = 20V
nA
––– -100
VGS = -20V
1.5 –––

Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 56A by
source bonding technology. Note that current limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
 Repetitive rating; pulse width limited by max. junction temperature.
 Limited by TJmax, starting TJ = 25°C, L = 130µH, RG = 50, IAS = 43A, VGS =10V.
 ISD  43A, di/dt  1020A/µs, VDD  V(BR)DSS, TJ 175°C.
 Pulse width  400µs; duty cycle  2%.
 Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
 R is measured at TJ approximately 90°C.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994: http://www.irf.com/technical-info/appnotes/an-994.pdf
 Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 19A, VGS =10V.
2
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Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge Sync. (Qg – Qgd)
Turn-On Delay Time
Rise Time
Min.
56
–––
–––
–––
–––
–––
–––
Typ.
–––
58
14
18
26
8.1
28
td(off)
Turn-Off Delay Time
–––
36
tf
Ciss
Coss
Crss
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance
(Energy Related)
Output Capacitance (Time Related)
–––
–––
–––
–––
20
3020
280
180
–––
290
–––
VGS = 0V, VDS = 0V to 48V
–––
370
–––
VGS = 0V, VDS = 0V to 48V
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Min.
Typ.
Max. Units
–––
–––
71
–––
–––
280
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
VSD
Diode Forward Voltage
–––
–––
1.2
dv/dt
Peak Diode Recovery dv/dt
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
–––
–––
–––
–––
–––
–––
12
26
29
22
30
1.5
–––
–––
–––
–––
–––
–––
Coss eff.(ER)
Coss eff.(TR)
Max. Units
Conditions
–––
S VDS = 25V, ID = 43A
87
ID = 43A
–––
VDS = 30V
nC –––
VGS = 10V
–––
–––
VDD = 30V
–––
ID = 43A
ns
–––
RG= 2.7
VGS = 10V 
–––
–––
–––
–––
pF VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig.7
Diode Characteristics Symbol
IS
ISM
3
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A
V
D
G
S
TJ = 25°C,IS = 43A,VGS = 0V 
V/ns TJ = 175°C,IS = 43A,VDS = 60V
TJ = 25°C
VDD = 51V
ns
TJ = 125°C
IF = 43A,
TJ = 25°C di/dt = 100A/µs 
nC
TJ = 125°C
A TJ = 25°C 
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1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
10
4.5V
BOTTOM
4.5V
10
60µs PULSE WIDTH
60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
1
0.1
1
10
0.1
100
V DS, Drain-to-Source Voltage (V)
Fig 3. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
100
T J = 175°C
10
T J = 25°C
1
VDS = 25V
60µs PULSE WIDTH
2.0
3.0
4.0
5.0
6.0
7.0
ID = 43A
V GS = 10V
2.0
1.5
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
8.0
TJ , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 5. Typical Transfer Characteristics
100000
V GS, Gate-to-Source Voltage (V)
ID= 43A
10000
Ciss
1000
Fig 6. Normalized On-Resistance vs. Temperature
14.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = C gd
Coss = Cds + Cgd
C, Capacitance (pF)
100
2.5
0.1
Coss
Crss
100
12.0
10.0
V DS= 48V
8.0
V DS= 12V
V DS= 30V
6.0
4.0
2.0
0.0
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
4
10
Fig 4. Typical Output Characteristics
1000
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
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0
10
20
30
40
50
60
70
80
QG, Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs.
Gate-to-Source Voltage
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100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
TJ = 25°C
10
1
100µsec
100
1msec
Limited by
package
OPERATION
IN THIS
AREA
LIMITED BY
RDS(on)
10
1
V GS = 0V
0.1
DC
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.1
1
V SD, Source-to-Drain Voltage (V)
10
VDS, Drain-toSource Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
0.5
78
Id = 1.0mA
76
0.4
74
Energy (µJ)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
72
70
0.3
0.2
68
0.1
66
0.0
64
-10
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
10
20
30
40
50
60
70
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( m)
0
Fig 12. Typical Coss Stored Energy
40
VGS = 5.5V
VGS = 6.0V
VGS = 7.0V
VGS = 8.0V
VGS =10V
30
20
10
0
0
20 40 60 80 100 120 140 160 180 200
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming  Tj = 150°C and
Tstart =25°C (Single Pulse)
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Avalanche Current vs. Pulse Width
EAR , Avalanche Energy (mJ)
120
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 43A
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figure 14)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
Iav = 2T/ [1.3·BV·Zth]
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IRFR/U7546PbF
12
3.5
10
IF = 28A
V R = 51V
TJ = 25°C
3.0
8
TJ = 125°C
2.5
IRRM (A)
V GS(th) , Gate threshold Voltage (V)
4.0
ID = 100µA
ID = 250µA
2.0
4
ID = 1.0mA
ID = 1.0A
1.5
2
1.0
0
-75 -50 -25
0
25 50 75 100 125 150 175
0
200
400
600
800
1000
TJ , Temperature ( °C )
diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature
Fig 18. Typical Recovery Current vs. dif/dt
12
200
IF = 43A
V R = 51V
10
IF = 28A
V R = 51V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
150
QRR (nC)
8
IRRM (A)
6
6
100
4
50
2
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig 20. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt
200
IF = 43A
V R = 51V
TJ = 25°C
150
QRR (nC)
TJ = 125°C
100
50
0
0
200
400
600
800
1000
diF /dt (A/µs)
Fig 21. Typical Stored Charge vs. dif/dt
7
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Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
IAS
20V
tp
+
V
- DD
A
I AS
0.01
Fig 23a. Unclamped Inductive Test Circuit
Fig 24a. Switching Time Test Circuit
Fig 23b. Unclamped Inductive Waveforms
Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD Vgs(th)
Qgs1 Qgs2
Fig 25a. Gate Charge Test Circuit
8
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Qgd
Qgodr
Fig 25b. Gate Charge Waveform
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IRFR/U7546PbF
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
Note: "P" in assembly line position
indicates "Lead-Free"
IRFR120
12
116A
34
ASSEMBLY
LOT CODE
DATE CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
OR
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFR120
12
ASSEMBLY
LOT CODE
34
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
YEAR 1 = 2001
WEEK 16
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
9
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IRFR/U7546PbF
I-Pak (TO-251AA) Package Outline (Dimensions are shown in millimeters (inches))
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: THIS IS AN IRFU120
WITH ASSEMBLY
LOT CODE 5678
ASSEMBLED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
119A
56
78
ASSEMBLY
LOT CODE
Note: "P" in assembly line position
indicates Lead-Free"
DATE CODE
YEAR 1 = 2001
WEEK 19
LINE A
OR
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
56
ASSEMBLY
LOT CODE
78
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 1 = 2001
WEEK 19
A = ASSEMBLY SITE CODE
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFR/U7546PbF
D-Pak (TO-252AA) Tape & Reel Information (Dimensions are shown in millimeters (inches))
TR
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
11
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IRFR/U7546PbF
Qualification Information† Industrial
(per JEDEC JESD47F) ††
Qualification Level Moisture Sensitivity Level
D-Pak
MSL1
I-Pak
N/A
Yes
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability/
††
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
11/7/2014
Comment
Updated EAS (L =1mH) = 178mJ on page 2
Updated note 10 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 19A, VGS =10V” on page 2
Updated package outline on page 9 & 10
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
12
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