MUN5315DW1, NSBC114TPDXV6 Complementary Bias Resistor Transistors R1 = 10 kW, R2 = 8 kW http://onsemi.com NPN and PNP Transistors with Monolithic Bias Resistor Network This series of digital transistors is designed to replace a single device and its external resistor bias network. The Bias Resistor Transistor (BRT) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. PIN CONNECTIONS (3) (2) R1 • • • • Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable Simplifies Circuit Design Reduces Board Space Reduces Component Count These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant R2 Q1 Q2 R2 Features • S and NSV Prefix for Automotive and Other Applications (1) R1 (4) (5) (6) MARKING DIAGRAMS 6 15 M G G SOT−363 CASE 419B 1 MAXIMUM RATINGS (TA = 25°C both polarities Q1 (PNP) and Q2 (NPN), unless otherwise noted) Symbol Max Unit Collector−Base Voltage VCBO 50 Vdc Collector−Emitter Voltage VCEO 50 Vdc Rating Collector Current − Continuous IC 100 mAdc Input Forward Voltage VIN(fwd) 40 Vdc Input Reverse Voltage −NPN −PNP VIN(rev) Vdc 6 5 1 15 M G 15 M G G SOT−563 CASE 463A = Specific Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION Package Shipping† MUN5315DW1T1G, SMUN5315DW1T1G SOT−363 3,000 / Tape & Reel NSBC114TPDXV6T1G SOT−563 4,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 0 1 Publication Order Number: DTC114TP/D MUN5315DW1, NSBC114TPDXV6 THERMAL CHARACTERISTICS Characteristic Symbol Max Unit 187 256 1.5 2.0 mW MUN5315DW1 (SOT−363) One Junction Heated Total Device Dissipation TA = 25°C (Note 1) (Note 2) (Note 1) (Note 2) Derate above 25°C Thermal Resistance, Junction to Ambient (Note 1) (Note 2) PD RqJA mW/°C 670 490 °C/W 250 385 2.0 3.0 mW MUN5315DW1 (SOT−363) Both Junction Heated (Note 3) Total Device Dissipation TA = 25°C (Note 1) (Note 2) (Note 1) (Note 2) Derate above 25°C PD mW/°C Thermal Resistance, Junction to Ambient (Note 1) (Note 2) RqJA 493 325 °C/W Thermal Resistance, Junction to Lead (Note 1) (Note 2) RqJL 188 208 °C/W TJ, Tstg −55 to +150 °C 357 2.9 mW mW/°C Junction and Storage Temperature Range NSBC114TPDXV6 (SOT−563) One Junction Heated Total Device Dissipation TA = 25°C Derate above 25°C (Note 1) (Note 1) Thermal Resistance, Junction to Ambient (Note 1) PD RqJA 350 °C/W NSBC114TPDXV6 (SOT−563) Both Junction Heated (Note 3) Total Device Dissipation TA = 25°C Derate above 25°C (Note 1) (Note 1) Thermal Resistance, Junction to Ambient (Note 1) Junction and Storage Temperature Range PD RqJA TJ, Tstg 1. FR−4 @ Minimum Pad. 2. FR−4 @ 1.0 x 1.0 Inch Pad. 3. Both junction heated values assume total power is sum of two equally powered channels. http://onsemi.com 2 500 4.0 250 −55 to +150 mW mW/°C °C/W °C MUN5315DW1, NSBC114TPDXV6 ELECTRICAL CHARACTERISTICS (TA = 25°C both polarities Q1 (PNP) and Q2 (NPN), unless otherwise noted) Symbol Characteristic Min Typ Max − − 100 − − 500 − − 0.9 50 − − 50 − − 160 350 − − − 0.25 − − 0.6 0.6 − − − − 1.4 1.4 − − − − 0.2 4.9 − − Unit OFF CHARACTERISTICS Collector−Base Cutoff Current (VCB = 50 V, IE = 0) ICBO Collector−Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO Emitter−Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO Collector−Base Breakdown Voltage (IC = 10 mA, IE = 0) V(BR)CBO Collector−Emitter Breakdown Voltage (Note 4) (IC = 2.0 mA, IB = 0) V(BR)CEO nAdc nAdc mAdc Vdc Vdc ON CHARACTERISTICS hFE DC Current Gain (Note 4) (IC = 5.0 mA, VCE = 10 V) Collector−Emitter Saturation Voltage (Note 4) (IC = 10 mA, IB = 1.0 mA) VCE(sat) Input Voltage (off) (VCE = 5.0 V, IC = 100 mA) (NPN) (VCE = 5.0 V, IC = 100 mA) (PNP) Vi(off) Input Voltage (on) (VCE = 0.2 V, IC = 10 mA) (NPN) (VCE = 0.2 V, IC = 10 mA) (PNP) Vi(on) Output Voltage (on) (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW) VOL Output Voltage (off) (VCC = 5.0 V, VB = 0.25 V, RL = 1.0 kW) VOH Input Resistor R1 7.0 10 13 Resistor Ratio R1/R2 − − − 4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%. PD, POWER DISSIPATION (mW) 400 350 300 (1) SOT−363; 1.0 x 1.0 inch Pad (2) SOT−563; Minimum Pad 250 200 (1) (2) 150 100 50 0 −50 −25 0 25 50 75 100 125 150 AMBIENT TEMPERATURE (°C) Figure 1. Derating Curve http://onsemi.com 3 Vdc Vdc Vdc Vdc Vdc kW MUN5315DW1, NSBC114TPDXV6 TYPICAL CHARACTERISTICS − NPN TRANSISTOR MUN5315DW1, NSBC114TPDXV6 1000 IC/IB = 10 75°C 0.1 −25°C 25°C 0.01 0.001 0 20 40 30 10 IC, COLLECTOR CURRENT (mA) 25°C 10 1 50 TA = −25°C 100 1 10 IC, COLLECTOR CURRENT (mA) Figure 2. VCE(sat) vs. IC 100 2.8 IC, COLLECTOR CURRENT (mA) f = 10 kHz IE = 0 A TA = 25°C 3.2 2.4 2.0 1.6 1.2 0.8 0.4 75°C 10 5 10 15 20 25 30 35 40 VR, REVERSE VOLTAGE (V) 45 50 25°C 1 TA = −25°C 0.1 0.01 0.001 0 VO = 5 V 0 Figure 4. Output Capacitance 1 2 3 4 5 6 7 Vin, INPUT VOLTAGE (V) TA = −25°C 1 25°C 75°C VO = 0.2 V 0.1 0 8 9 Figure 5. Output Current vs. Input Voltage 10 Vin, INPUT VOLTAGE (V) Cob, OUTPUT CAPACITANCE (pF) 100 Figure 3. DC Current Gain 3.6 0 VCE = 10 V 75°C hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) 1 40 10 20 30 IC, COLLECTOR CURRENT (mA) Figure 6. Input Voltage vs. Output Current http://onsemi.com 4 50 10 MUN5315DW1, NSBC114TPDXV6 TYPICAL CHARACTERISTICS − PNP TRANSISTOR MUN5315DW1, NSBC114TPDXV6 1000 IC/IB = 10 75°C hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) 1 75°C 0.1 −25°C 25°C 0.01 0.001 0 20 40 30 10 IC, COLLECTOR CURRENT (mA) TA = −25°C 100 10 VCE = 10 V 1 50 25°C 1 10 IC, COLLECTOR CURRENT (mA) Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain 100 8 7 IC, COLLECTOR CURRENT (mA) f = 10 kHz lE = 0 A TA = 25°C 9 6 5 4 3 2 1 0 10 20 30 40 VR, REVERSE VOLTAGE (V) 75°C 10 25°C 1 0.01 0.001 50 TA = −25°C 0.1 VO = 5 V 0 Figure 9. Output Capacitance 1 2 3 4 5 6 7 Vin, INPUT VOLTAGE (V) VO = 0.2 V TA = −25°C 1 75°C 0.1 0 8 9 Figure 10. Output Current vs. Input Voltage 10 Vin, INPUT VOLTAGE (V) Cob, OUTPUT CAPACITANCE (pF) 10 0 100 25°C 10 20 30 40 IC, COLLECTOR CURRENT (mA) Figure 11. Input Voltage vs. Output Current http://onsemi.com 5 50 10 MUN5315DW1, NSBC114TPDXV6 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. D e 6 5 4 1 2 3 HE DIM A A1 A3 b C D E e L HE −E− b 6 PL 0.2 (0.008) M E MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 M A3 C A A1 L SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches SC−88/SC70−6/SOT−363 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 MUN5315DW1, NSBC114TPDXV6 PACKAGE DIMENSIONS SOT−563, 6 LEAD CASE 463A ISSUE F D −X− 5 6 1 e 2 A 4 L E −Y− 3 b NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b C D E e L HE HE C 5 PL 6 0.08 (0.003) M X Y MILLIMETERS MIN NOM MAX 0.50 0.55 0.60 0.17 0.22 0.27 0.08 0.12 0.18 1.50 1.60 1.70 1.10 1.20 1.30 0.5 BSC 0.10 0.20 0.30 1.50 1.60 1.70 INCHES NOM MAX 0.021 0.023 0.009 0.011 0.005 0.007 0.062 0.066 0.047 0.051 0.02 BSC 0.004 0.008 0.012 0.059 0.062 0.066 MIN 0.020 0.007 0.003 0.059 0.043 SOLDERING FOOTPRINT* 0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394 0.5 0.5 0.0197 0.0197 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative DTC114TP/D