MC74HC4351 Analog Multiplexers/ Demultiplexers with Address Latch High−Performance Silicon−Gate CMOS The MC54/74HC4351, and MC54/74HC4353 utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. The data at the Channel−Select inputs may be latched by using the active−low Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The Channel−Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches. For multiplexers/demultiplexers without latches, see the HC4051, HC4052, and HC4053. • • • • • • • • • Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance than Metal−Gate Types Low Noise In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates HC4353 — 186 FETs or 46.5 Equivalent Gates http://onsemi.com J SUFFIX CERAMIC PACKAGE CASE 732−03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738−03 20 1 20 DW SUFFIX SOIC PACKAGE CASE 751D−04 1 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDW Ceramic Plastic SOIC PIN ASSIGNMENT MC54/74HC4351 X4 1 20 VCC X6 2 19 X2 NC 3 18 X1 X 4 17 X0 X7 5 16 X3 X5 6 15 A ENABLE 1 7 14 NC ENABLE 2 8 13 B VEE 9 12 GND 10 11 C LATCH ENABLE NC = NO CONNECTION © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 7 1 Publication Order Number: MC74HC4351/D MC74HC4351 LOGIC DIAGRAM MC54/74HC4351 Single−Pole, 8−Position Plus Common Off and Address Latch ANALOG INPUTS/OUTPUTS CHANNEL−SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 15 13 12 17 X0 18 X1 19 X2 16 X3 1 X4 6 X5 2 X6 5 X7 FUNCTION TABLE MC54/74HC4351 MULTIPLEXER/ DEMULTIPLEXER 4 X COMMON OUTPUT/INPUT Control Inputs Enable 1 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 11 7 8 Select 2 C B A ON Channel (LE = H)* X0 X1 X2 X3 X4 X5 X6 X7 None None L H L L L L H L L H L H L H L L H L H H L H H L L L H H L H L H H H L L H H H H H X X X X X L X X X X = don’t care *When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. BLOCK DIAGRAM MC54/74HC4353 Triple Single−Pole, Double−Position Plus Common Off and Address Latch FUNCTION TABLE X SWITCH 2 1 Y SWITCH 6 4 Z SWITCH Y0 Y1 Z0 Z1 CHANNEL−SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 15 13 12 PIN ASSIGNMENT 16 X0 17 X1 18 19 5 CHANNEL ADDRESS LATCH X Y COMMON OUTPUT/INPUT Z PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 11 7 8 NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X Switch, Input B controls the Y Switch, and Input C controls the Z Switch. http://onsemi.com 2 Y1 1 20 VCC Y0 2 19 Y NC 3 Control Inputs 18 X On Enable Select Z1 4 X1 17 Channel 1 2 C B A (LE = H)* Z 5 X0 16 L H L L L Z0 Y0 X0 15 A L H L Z0 L 6 H Z0 Y0 X1 L H ENABLE L Z0 Y1 X0 1H 7 L 14 NC L H L H H Z0 Y1 X1 L H ENABLE H 2L 8 L Z1 Y0 X0 13 B L H H L H Z1 Y0 X1 C 12 L H H VEEH 9 L Z1 Y1 X0 L H H H H Z1 Y1 X1 LATCH 11 None H X X GND X 10 X ENABLE None X L X X X NC = NO CONNECTION X = Don’t Care *When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. MC74HC4351 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol Parameter Unit – 0.5 to + 7.0 – 0.5 to 14.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V Vin DC Input Voltage (Ref. to GND) – 1.5 to VCC + 1.5 V I (Ref. to GND) (Ref. to VEE) Value DC Current Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air,Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature – 65 to + 150 _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the ranges indicated in the Recommended Operating Conditions. Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. See Applications Information. TL Lead Temperature, 1 mm from Case for _C 260 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) 300 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) 2.0 2.0 6.0 12.0 V VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Ref. to GND) GND VCC V — 1.2 V – 55 + 125 _C VIO* TA Parameter Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, VCC = 2.0 V 0 1000 ns Channel Select or Enable VCC = 4.5 V 0 500 Inputs (Figure 9a) VCC = 6.0 V 0 400 *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Iin Maximum Input Leakage Current, Channel−Select or Enable Inputs Vin = VCC or GND, VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 μA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND Enables = VCC or GND VIS = VCC or GND VEE = GND VIO = 0 V VEE = – 6.0 Symbol Parameter Test Conditions μA 6.0 6.0 2 8 20 80 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). http://onsemi.com 3 MC74HC4351 ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Limit Symbol Ron VCC V VEE V – 55 to 25_C v 85_C v 125_C Unit Vin = VIL or VIH VIS = VCC to VEE IS v 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 190 120 100 240 150 125 280 170 140 Ω Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 150 100 80 190 125 100 230 140 115 Parameter Test Conditions Maximum “ON” Resistance ΔRon Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH VIS = 1/2 (VCC − VEE) IS v 2.0 mA 4.5 4.5 6.0 0.0 – 4.5 – 6.0 30 12 10 35 15 12 40 18 14 Ω Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL or VIH VIO = VCC − VEE Switch Off (Figure 3) 6.0 − 6.0 0.1 0.5 1.0 μA Maximum Off−Channel Leakage Current, Common Channel HC4351 Vin = VIL or VIH VIO = VCC − VEE Switch Off (Figure 4) 6.0 – 6.0 0.2 2.0 4.0 6.0 – 6.0 0.1 1.0 2.0 HC4353 Ion Maximum On−Channel Leakage Current, Channel to Channel HC4351 Vin = VIL or VIH Switch to Switch = VCC − VEE (Figure 5) HC4353 μA 6.0 – 6.0 0.2 2.0 4.0 6.0 – 6.0 0.1 1.0 2.0 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, Channel−Select to Analog Output (Figure 9) 2.0 4.5 6.0 370 74 63 465 93 79 550 110 94 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Analog Output (Figure 12) 2.0 4.5 6.0 325 65 55 410 82 70 485 97 82 ns tPLZ, tPHZ Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) 2.0 4.5 6.0 290 58 49 365 73 62 435 87 74 ns tPZL, tPZH Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) 2.0 4.5 6.0 345 69 59 435 87 74 515 103 87 ns Cin Maximum Input Capacitance — 10 10 10 pF Cl/O Maximum Capacitance Analog I/O pF Symbol Parameter Enable 1 = VIH, Enable 2 = VIL — 35 35 35 Common O/I: HC4351 HC4353 — 130 50 130 50 130 50 Feedthrough — 1.0 1.0 1.0 NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package) (Figure 14)* 45 (HC4351) 45 (HC4353) pF * Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). http://onsemi.com 4 MC74HC4351 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit tsu Minimum Setup Time, Channel−Select to Latch Enable (Figure 12) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Latch Enable to Channel Select (Figure 12) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns tw Minimum Pulse Width, Latch Enable (Figure 12) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times, Channel−Select, Latch Enable, and Enables 1 and 2 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tr, tf NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) Limit* Symbol Parameter Test Condition BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 Ω, CL = 10 pF Off–Channel Feedthrough Isolation (Figure 7) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF — fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF — Feedthrough Noise, Channel Select Input to Common O/I (Figure 8) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A Enable = GND RL = 600 Ω, CL = 50 pF RL = 10 kΩ, CL = 10 pF — Crosstalk Between Any Two Switches (Figure 13) (Test does not apply to HC4351) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF fin = 1 MHz, RL = 50 Ω, CL = 10 pF THD fin = 1 kHz, RL = 10 kΩ, CL = 50 pF THD = THDMeasured – THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. VCC V 2.25 4.50 6.00 25_C 54/74HC Unit 51 52 53 MHz 80 80 80 95 95 95 120 120 120 VEE V – 2.25 – 4.50 – 6.00 dB 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 40 – 40 – 40 mVPP 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 25 105 135 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 35 145 190 dB 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 60 – 60 – 60 Total Harmonic Distortion (Figure 15) http://onsemi.com 5 % 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 0.10 0.08 0.05 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74HC4351 200 125°C 150 25°C 100 −55 °C 50 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 100 125°C 80 25°C 60 −55 °C 40 20 2.25 0 0.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 25°C Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 75 60 45 −55 °C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 75 125°C 60 25°C 45 −55 °C 30 15 0 6.0 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Figure 1d. Typical On Resistance, VCC − VEE = 9.0 V Ron , ON RESISTANCE (OHMS) PLOTTER 70 125°C 50 25°C PROGRAMMABLE POWER SUPPLY 40 − MINI COMPUTER VCC DEVICE UNDER TEST 20 10 ANALOG IN 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 DC ANALYZER + −55 °C 30 9 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1c. Typical On Resistance, VCC − VEE = 6.0 V 60 4 Figure 1b. Typical On Resistance, VCC − VEE = 4.5 V 105 125°C 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V 90 1.0 8.0 9.0 10.0 11.0 12.0 GND VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC − VEE = 12.0 V http://onsemi.com 6 COMMON OUT VEE Figure 2. On Resistance Test Set−Up MC74HC4351 VCC VCC VEE ANALOG I/O VEE COMMON O/I 7 8 9 10 VIH VEE VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set−Up VOS VCC VCC 20 A VCC COMMON O/I OFF VEE dB METER ON N/C RL C L* VCC ANALOG I/O 7 8 9 10 7 8 9 10 VIL VIH 20 0.1μF fin ON VCC A OFF 7 8 9 10 VIH OFF VCC COMMON O/I OFF NC 20 ANALOG I/O OFF A VCC VCC VCC 20 VEE VEE *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set−Up VCC VIS VOS VCC 20 0.1 μF fin OFF C L* RL Figure 6. Maximum On Channel Bandwidth, Test Set−Up dB METER RL 20 RL ON/OFF ANALOG I/O COMMON O/I OFF/ON 7 8 9 10 VCC VEE VCC GND *Includes all probe and jig capacitance. Vin ≤ 1 MHz tr = tf = 6 ns 7 8 9 10 C L* RL RL TEST POIN VCC 11 VEE CHANNEL SELECT *Includes all probe and jig capacitance. Figure 7. Off Channel Feedthrough Isolation, Test Set−Up Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set−Up http://onsemi.com 7 MC74HC4351 VCC VCC 20 ON/OFF tr ANALOG I/O tf VCC 90% 50% 10% CHANNEL SELECT OFF/ON C L* VCC TES POI 7 8 9 10 GND tPLH COMMON O/I tPHL 50% ANALOG OUT CHANNEL SELECT *Includes all probe and jig capacitance. Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set−Up Channe Select to Analog Out VCC 20 COMMON O/I ANALOG I/O ANALOG IN ON VCC C L* VCC 50% 7 8 9 10 GND tPHL tPLH ANALOG OUT TEST POIN 50% *Includes all probe and jig capacitance. Figure 10b. Propagation Delay, Test Set−Up Analog In to Analog Out Figure 10a. Propagation Delays, Analog In to Analog Out 1 POSITIONWHEN TESTING tPHZ AND tPZH 1 2 POSITIONWHEN TESTING tPLZ AND tPZL 2 ENABLE VCC 50% ANALOG OUT HIGH IMPEDANCE 50% tPZH ANALOG OUT tPLZ 50% tPHZ 10% VOL 90% VOH 20 1 GND tPZL VCC VCC ANALOG I/O ON/OFF 2 C L* ENABLE HIGH IMPEDANCE Figure 11a. Propagation Delay, Enable 1 or 2 to Analog Out 1 kΩ TEST POIN 7 8 9 10 Figure 11b. Propagation Delay, Test Set−Up Enable to Analog Out http://onsemi.com 8 MC74HC4351 VCC VCC CHANNEL SELECT 20 VCC 50% ON/OFF ANALOG I/O GND tsu tr tf th 10% OFF/ON C L* VCC VCC 90% 50% LATCH ENABLE 2 COMMON O/I 7 8 9 10 GND tw TES POI 11 LATCH ENABLE COMMON O/I 50% CHANNEL SELECT tPLH, tPHL *Includes all probe and jig capacitance. Figure 12a. Propagation Delay, Latch Enable to Analog Out VIS Figure 12b. Propagation Delay, Test Set−Up Latch Enable to Analog Out VCC VCC A 20 RL fin VCC VOS ON 0.1 μF dB METER ANALOG I/O OFF VCC VEE 20 ON/OFF NC COMMON O/I OFF/ON VCC RL RL C L* RL C L* 7 8 9 10 7 8 9 10 VCC 11 VEE CHANNEL SELECT *Includes all probe and jig capacitance. Figure 13. Crosstalk Between Any Two Switches, Test Set−Up Figure 14. Power Dissipation Capacitance, Test Set-Up 0 −10 VCC VOS 20 0.1 μF fin ON RL FUNDAMENTAL FREQUENCY −20 C L* TO DISTORTION METER −30 −40 dB VIS VCC −50 DEVICE −60 7 8 9 10 SOURCE −70 −80 −90 VEE 1.0 *Includes all probe and jig capacitance. 2.0 FREQUENCY (kHz) Figure 15a. Total Harmonic Distortion, Test Set-Up Figure 15b. Plot, Harmonic Distortion http://onsemi.com 9 3.1 MC74HC4351 APPLICATIONS INFORMATION outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = + 5 V = logic high VCC − GND = 2 to 6 volts GND = 0 V = logic low VEE − GND = 0 to − 6 volts The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal of ten volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and VCC − VEE = 2 to 12 volts and VEE v GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping. VCC +5 V +5V −5V 20 ANALOG SIGNAL ON Dx +5V ANALOG SIGNAL VCC 20 Dx Dx VEE 15 13 12 11 Dx ON/OFF −5V +5 V 7 8 9 10 VCC TO EXTERNAL CMOS CIRCUITRY 0 TO 5 V DIGITAL SIGNALS VEE 9 10 −5 V VEE Figure 16. Application Example Figure 17. External Germanium or Schottky Clipping Diodes +5V +5V +5V VEE 20 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL +5V +5V VEE VEE 20 ANALOG SIGNAL ON/OFF ANALOG SIGNAL * 7 8 9 10 VEE VEE +5 R VCC +5V R R 15 13 12 11 VCC R LSTTL/NMOS CIRCUITRY * 2 k ≤ R ≤ 10 k 7 15 8 13 9 12 10 11 HCT BUFFER VEE a. Using Pull−Up Resistors LSTTL/NMOS CIRCUITRY b. Using HCT Interface Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs http://onsemi.com 10 MC74HC4351 FUNCTION DIAGRAM HC4351 A 15 LATCH & LEVEL SHIFTER 17 X X B 13 LATCH & LEVEL SHIFTER X X C 12 LATCH & LEVEL SHIFTER X 6 LATCH 11 ENABLE ENABLE 1 ENABLE 2 7 2 LEVEL SHIFTER X X 8 5 4 X X FUNCTION DIAGRAM HC4353 A 15 LATCH & LEVEL SHIFTER 17 16 18 B 13 LATCH & LEVEL SHIFTER 1 2 19 C 12 LATCH & LEVEL SHIFTER 4 6 LATCH 11 ENABLE ENABLE 1 ENABLE 2 5 7 LEVEL SHIFTER 8 http://onsemi.com 11 X X X Y Y Y Z Z Z MC74HC4351 OUTLINE DIMENSIONS 20 11 1 10 J SUFFIX CERAMIC PACKAGE CASE 732−03 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F N H J K G D DIM A B C D F G H J K L M N M SEATING PLANE N SUFFIX PLASTIC PACKAGE CASE 738−03 ISSUE E −A− 20 11 1 10 −T− L DIM A B C D E F G J K L M N K SEATING PLANE G M N E F D J 20 PL M T A 11 −B− 10X P 0.010 (0.25) M 1 B M 10 20X D 0.010 (0.25) M T A B S J S F R C −T− 18X G K SEATING PLANE M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D−04 ISSUE E −A− 20 20 PL 0.25 (0.010) 0.25 (0.010) M http://onsemi.com 12 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B C MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 X 45 _ INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 MC74HC4351 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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