SEMICONDUCTOR TECHNICAL DATA " " ! High–Performance Silicon–Gate CMOS The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel–Select inputs determine which one of the Analog Inputs/ Outputs is to be connected, by means of an analog switch, to the Common Output/Input. The data at the Channel–Select inputs may be latched by using the active–low Latch Enable pin. When Latch Enable is high, the latch is transparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches. For multiplexers/demultiplexers without latches, see the HC4051, HC4052, and HC4053. J SUFFIX CERAMIC PACKAGE CASE 732–03 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 20 1 ORDERING INFORMATION MC54HCXXXXJ MC74HCXXXXN MC74HCXXXXDW • • • • • • • • Fast Switching and Propagation Speeds Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V Improved Linearity and Lower ON Resistance than Metal–Gate Types Low Noise In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates HC4353 — 186 FETs or 46.5 Equivalent Gates Ceramic Plastic SOIC PIN ASSIGNMENT MC54/74HC4351 X4 1 20 VCC X6 2 19 X2 NC 3 18 X1 X 4 17 X0 X7 5 16 X3 X5 6 15 A ENABLE 1 7 14 NC ENABLE 2 8 13 B VEE 9 12 GND 10 11 C LATCH ENABLE NC = NO CONNECTION 10/95 Motorola, Inc. 1995 1 REV 6 MC54/74HC4351 MC54/74HC4353 LOGIC DIAGRAM MC54/74HC4351 Single–Pole, 8–Position Plus Common Off and Address Latch 17 X0 18 X1 19 X2 16 X3 1 X4 6 X5 2 X6 5 X7 ANALOG INPUTS/OUTPUTS CHANNEL–SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 FUNCTION TABLE MC54/74HC4351 MULTIPLEXER/ DEMULTIPLEXER 4 X Control Inputs COMMON OUTPUT/INPUT Enable 1 12 CHANNEL ADDRESS LATCH PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 11 7 8 2 C B A L H L L L X0 L H L L H X1 L H L H X2 L L H L H H X3 L H H X4 L L L L H H H X5 L H H H X6 L L H H H H X7 H None X X X X X None L X X X X = don’t care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. 15 13 ON Channel (LE = H)* Select BLOCK DIAGRAM MC54/74HC4353 Triple Single–Pole, Double–Position Plus Common Off and Address Latch X SWITCH 2 1 Y SWITCH Y0 Y1 Z0 Z1 CHANNEL–SELECT INPUTS A B C LATCH ENABLE SWITCH ENABLE 1 ENABLES ENABLE 2 PIN ASSIGNMENT 16 X0 17 X1 6 4 Z SWITCH 18 19 5 X Y COMMON OUTPUT/INPUT 13 12 CHANNEL ADDRESS LATCH 20 VCC Y0 2 19 Y NC 3 18 X Z1 4 17 X1 Z 5 16 X0 6 15 A ENABLE 1 7 14 NC ENABLE 2 8 13 B VEE 9 12 GND 10 11 C LATCH ENABLE PIN 20 = VCC PIN 9 = VEE PIN 10 = GND PINS 3, 14 = NC 11 7 8 1 Z0 Z 15 Y1 NC = NO CONNECTION FUNCTION TABLE NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X Switch, Input B controls the Y Switch, and Input C controls the Z Switch. Control Inputs Enable On Channel (LE = H)* Select 1 2 C B A L L L L L L L L H X H H H H H H H H X L L L L L H H H H X X L L H H L L H H X X L H L H L H L H X X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None None X0 X1 X0 X1 X0 X1 X0 X1 X = Don’t Care * When Latch Enable is low, the Channel Selection is latched and the Channel Address Latch does not change states. MOTOROLA 2 High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC4351 MC54/74HC4353 MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 – 0.5 to 14.0 V Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V Analog Input Voltage VEE – 0.5 to VCC + 0.5 V VCC Positive DC Supply Voltage VEE VIS Vin DC Input Voltage (Ref. to GND) (Ref. to GND) (Ref. to VEE) – 1.5 to VCC + 1.5 V DC Current Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature – 65 to + 150 _C I TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the ranges indicated in the Recommended Operating Conditions. Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. See Applications Information. _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) 2.0 2.0 6.0 12.0 V VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Ref. to GND) GND VCC V VIO* Parameter Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, Channel Select or Enable Inputs (Figure 9a) — 1.2 V – 55 + 125 _C VCC = 2.0 V 0 1000 ns VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C 85_C 125_C Unit VIH Minimum High–Level Input Voltage, Channel–Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low–Level Input Voltage, Channel–Select or Enable Inputs Ron = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Iin Maximum Input Leakage Current, Channel–Select or Enable Inputs Vin = VCC or GND, VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 µA ICC Maximum Quiescent Supply Current (per Package) Channel Select = VCC or GND Enables = VCC or GND VIS = VCC or GND VEE = GND VIO = 0 V VEE = – 6.0 µA 6.0 6.0 2 8 20 80 40 160 NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). High–Speed CMOS Logic Data DL129 — Rev 6 3 MOTOROLA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ v ÎÎÎÎ v ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC4351 MC54/74HC4353 DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Limit Symbol Ron VCC V VEE V – 55 to 25_C Vin = VIL or VIH VIS = VCC to VEE IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC – VEE) IS 2.0 mA 4.5 4.5 6.0 0.0 – 4.5 – 6.0 4.5 4.5 6.0 Parameter Test Conditions Maximum “ON” Resistance ∆Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Ioff Maximum Off–Channel Leakage Current, Any One Channel Vin = VIL or VIH VIO = VCC – VEE Switch Off (Figure 3) Maximum Off–Channel Leakage Current, Common Channel HC4351 Vin = VIL or VIH VIO = VCC – VEE Switch Off (Figure 4) HC4353 Ion Maximum On–Channel Leakage Current, Channel to Channel HC4351 Vin = VIL or VIH Switch to Switch = VCC – VEE (Figure 5) HC4353 85_C 125_C 190 120 100 240 150 125 280 170 140 0.0 – 4.5 – 6.0 150 100 80 190 125 100 230 140 115 4.5 4.5 6.0 0.0 – 4.5 – 6.0 30 12 10 35 15 12 40 18 14 Ω 6.0 – 6.0 0.1 0.5 1.0 µA 6.0 – 6.0 0.2 2.0 4.0 6.0 – 6.0 0.1 1.0 2.0 Unit Ω µA 6.0 – 6.0 0.2 2.0 4.0 6.0 – 6.0 0.1 1.0 2.0 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V – 55 to 25_C 85_C 125_C tPLH, tPHL Maximum Propagation Delay, Channel–Select to Analog Output (Figure 9) 2.0 4.5 6.0 370 74 63 465 93 79 550 110 94 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns tPLH, tPHL Maximum Propagation Delay, Latch Enable to Analog Output (Figure 12) 2.0 4.5 6.0 325 65 55 410 82 70 485 97 82 ns tPLZ, tPHZ Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) 2.0 4.5 6.0 290 58 49 365 73 62 435 87 74 ns tPZL, tPZH Maximum Propagation Delay, Enable 1 or 2 to Analog Output (Figure 11) 2.0 4.5 6.0 345 69 59 435 87 74 515 103 87 ns Cin Cl/O Maximum Input Capacitance — 10 10 10 pF — 35 35 35 pF Common O/I: HC4351 HC4353 — 130 50 130 50 130 50 Feedthrough — 1.0 1.0 1.0 Symbol Parameter Maximum Capacitance Analog I/O Enable 1 = VIH, Enable 2 = VIL Unit NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package) (Figure 14)* 45 (HC4351) 45 (HC4353) pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA 4 High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC4351 MC54/74HC4353 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit VCC V – 55 to 25_C 85_C 125_C tsu Minimum Setup Time, Channel–Select to Latch Enable (Figure 12) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Latch Enable to Channel Select (Figure 12) 2.0 4.5 6.0 0 0 0 0 0 0 0 0 0 ns tw Minimum Pulse Width, Latch Enable (Figure 12) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times, Channel–Select, Latch Enable, and Enables 1 and 2 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns Symbol tr, tf Parameter Unit NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) Limit* Symbol Parameter Test Condition BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 Ω, CL = 10 pF Off–Channel Feedthrough Isolation (Figure 7) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF — fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF — Feedthrough Noise, Channel Select Input to Common O/I (Figure 8) Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A Enable = GND RL = 600 Ω, CL = 50 pF RL = 10 kΩ, CL = 10 pF — Crosstalk Between Any Two Switches (Figure 13) (Test does not apply to HC4351) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 Ω, CL = 50 pF fin = 1 MHz, RL = 50 Ω, CL = 10 pF THD Total Harmonic Distortion (Figure 15) fin = 1 kHz, RL = 10 kΩ, CL = 50 pF THD = THDMeasured – THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave VCC V 2.25 4.50 6.00 25_C 54/74HC VEE V – 2.25 – 4.50 – 6.00 Unit 51 52 53 80 80 80 95 95 95 120 120 120 MHz dB 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 40 – 40 – 40 mVPP 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 25 105 135 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 35 145 190 dB 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 60 – 60 – 60 % 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 0.10 0.08 0.05 * Limits not tested. Determined by design and verified by qualification. High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC54/74HC4351 MC54/74HC4353 200 125°C 150 25°C 100 – 55°C 50 0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 100 125°C 80 25°C 60 – 55°C 40 20 2.25 0 0.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 25°C Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 75 60 45 – 55°C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 4.0 3.5 4.5 Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V 105 125°C 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V 90 1.0 75 125°C 60 25°C 45 – 55°C 30 15 0 6.0 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1c. Typical On Resistance, VCC – VEE = 6.0 V Figure 1d. Typical On Resistance, VCC – VEE = 9.0 V PLOTTER Ron , ON RESISTANCE (OHMS) 70 60 125°C 50 25°C PROGRAMMABLE POWER SUPPLY 40 – MINI COMPUTER + VCC – 55°C 30 DEVICE UNDER TEST 20 10 ANALOG IN 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 GND VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V MOTOROLA DC ANALYZER COMMON OUT VEE Figure 2. On Resistance Test Set–Up 6 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC4351 MC54/74HC4353 VCC VCC VEE ANALOG I/O 20 VEE ANALOG I/O OFF A VCC VCC VCC 20 OFF NC A OFF 7 8 9 10 VIH OFF VCC COMMON O/I 7 8 9 10 VIH VEE VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set–Up Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set–Up VCC VCC VCC 20 A COMMON O/I OFF VEE dB METER ON N/C RL CL* VCC ANALOG I/O 7 8 9 10 7 8 9 10 VIL VIH VOS 20 0.1µF fin ON VCC COMMON O/I VEE VEE *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set–Up VCC VIS 0.1 µF VOS 20 fin OFF CL* RL Figure 6. Maximum On Channel Bandwidth, Test Set–Up VCC dB METER RL 20 RL ON/OFF COMMON O/I ANALOG I/O OFF/ON 7 8 9 10 VEE VCC VCC GND *Includes all probe and jig capacitance. VCC 11 VEE CHANNEL SELECT *Includes all probe and jig capacitance. Figure 7. Off Channel Feedthrough Isolation, Test Set–Up High–Speed CMOS Logic Data DL129 — Rev 6 Vin ≤ 1 MHz tr = tf = 6 ns 7 8 9 10 CL* RL RL TEST POINT Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set–Up 7 MOTOROLA MC54/74HC4351 MC54/74HC4353 VCC VCC 20 ON/OFF ANALOG I/O tr tf VCC 90% 50% 10% CHANNEL SELECT OFF/ON TEST POINT CL* VCC 7 8 9 10 GND tPLH COMMON O/I tPHL 50% ANALOG OUT CHANNEL SELECT *Includes all probe and jig capacitance. Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set–Up Channel Select to Analog Out VCC 20 COMMON O/I ANALOG I/O ON ANALOG IN VCC CL* VCC 50% 7 8 9 10 GND tPLH tPHL ANALOG OUT TEST POINT 50% *Includes all probe and jig capacitance. Figure 10b. Propagation Delay, Test Set–Up Analog In to Analog Out Figure 10a. Propagation Delays, Analog In to Analog Out POSITION 1 WHEN TESTING tPHZ AND tPZH 1 POSITION 2 WHEN TESTING tPLZ AND tPZL 2 VCC ENABLE 50% 1 GND tPZL ANALOG OUT 50% tPHZ 10% VOL 90% VOH ON/OFF CL* ENABLE HIGH IMPEDANCE Figure 11a. Propagation Delay, Enable 1 or 2 to Analog Out MOTOROLA 1 kΩ ANALOG I/O 2 HIGH IMPEDANCE 50% tPZH ANALOG OUT tPLZ VCC 20 VCC TEST POINT 7 8 9 10 Figure 11b. Propagation Delay, Test Set–Up Enable to Analog Out 8 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC4351 MC54/74HC4353 VCC VCC CHANNEL SELECT 20 VCC 50% ON/OFF ANALOG I/O GND tsu th tf tr 10% OFF/ON 7 8 9 10 GND tw TEST POINT CL* VCC VCC 90% 50% LATCH ENABLE 2 COMMON O/I 11 LATCH ENABLE COMMON O/I 50% CHANNEL SELECT tPLH, tPHL *Includes all probe and jig capacitance. Figure 12a. Propagation Delay, Latch Enable to Analog Out VIS Figure 12b. Propagation Delay, Test Set–Up Latch Enable to Analog Out VCC VCC A 20 RL fin VCC VOS ON 0.1 µF dB METER VEE NC ANALOG I/O OFF VCC 20 ON/OFF COMMON O/I OFF/ON VCC RL RL RL CL* CL* 7 8 9 10 7 8 9 10 VCC 11 VEE CHANNEL SELECT *Includes all probe and jig capacitance. Figure 13. Crosstalk Between Any Two Switches, Test Set–Up Figure 14. Power Dissipation Capacitance, Test Set-Up 0 – 10 VCC 0.1 µF VOS fin ON RL FUNDAMENTAL FREQUENCY – 20 20 CL* TO DISTORTION METER – 30 – 40 dB VIS VCC – 50 DEVICE – 60 7 8 9 10 SOURCE – 70 – 80 – 90 VEE 1.0 *Includes all probe and jig capacitance. 2.0 3.125 FREQUENCY (kHz) Figure 15a. Total Harmonic Distortion, Test Set-Up High–Speed CMOS Logic Data DL129 — Rev 6 Figure 15b. Plot, Harmonic Distortion 9 MOTOROLA MC54/74HC4351 MC54/74HC4353 The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: ever, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC = + 5 V = logic high VCC – GND = 2 to 6 volts GND = 0 V = logic low VEE – GND = 0 to – 6 volts The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal of ten volts peak–to–peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). How- VCC – VEE = 2 to 12 volts APPLICATIONS INFORMATION and VEE When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (D x ) are recommended as shown in Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping. VCC +5 V +5V –5V 20 ANALOG SIGNAL VCC 20 Dx +5V ANALOG SIGNAL ON v GND –5V Dx Dx VEE 15 13 12 11 Dx ON/OFF +5 V 7 8 9 10 VCC TO EXTERNAL CMOS CIRCUITRY 0 TO 5 V DIGITAL SIGNALS VEE 9 10 –5 V VEE Figure 16. Application Example Figure 17. External Germanium or Schottky Clipping Diodes +5V +5V +5V VEE 20 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL +5V +5V VEE VEE 20 ANALOG SIGNAL ANALOG SIGNAL ON/OFF * 7 8 9 10 VEE VEE +5V R VCC +5V R R 15 13 12 11 VCC R LSTTL/NMOS CIRCUITRY * 2 k ≤ R ≤ 10 k 7 15 8 13 9 12 10 11 HCT BUFFER VEE a. Using Pull–Up Resistors LSTTL/NMOS CIRCUITRY b. Using HCT Interface Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs MOTOROLA 10 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC4351 MC54/74HC4353 FUNCTION DIAGRAM HC4351 A 15 LATCH & LEVEL SHIFTER 17 X0 X1 B 13 LATCH & LEVEL SHIFTER X2 X3 C 12 LATCH & LEVEL SHIFTER X4 6 LATCH 11 ENABLE ENABLE 1 7 2 LEVEL SHIFTER ENABLE 2 X5 X6 8 5 4 X7 X FUNCTION DIAGRAM HC4353 A 15 LATCH & LEVEL SHIFTER 17 16 18 B 13 LATCH & LEVEL SHIFTER 1 2 19 C 12 LATCH & LEVEL SHIFTER 4 6 LATCH 11 ENABLE ENABLE 1 5 X1 X0 X Y1 Y0 Y Z1 Z0 Z 7 LEVEL SHIFTER ENABLE 2 8 High–Speed CMOS Logic Data DL129 — Rev 6 11 MOTOROLA MC54/74HC4351 MC54/74HC4353 OUTLINE DIMENSIONS 20 11 1 10 J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. B A L C F DIM A B C D F G H J K L M N N H G D J K M MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 SEATING PLANE N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D M T A 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R X 45 _ C –T– 18X G K SEATING PLANE M T B M M DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E –A– 20 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) MOTOROLA DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 M 12 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC4351 MC54/74HC4353 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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