Low-Voltage CMOS Octal Transceiver/Registered Transceiver

ON Semiconductort
Low−Voltage CMOS Octal
Transceiver/Registered
Transceiver
MC74LCX646
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX646 is a high performance, non−inverting octal
transceiver/registered transceiver operating from a 2.3 to 3.6 V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX646 inputs to be safely driven from 5 V devices. The
MC74LCX646 is suitable for memory address driving and all TTL
level bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW−to−HIGH logic level. Output
Enable (OE) and DIR pins are provided to control the transceiver
outputs. In the transceiver mode, data present at the high impedance
port may be stored in either the A or the B register or in both. The
select controls (SBA, SAB) can multiplex stored and real−time
(transparent mode) data. The direction control (DIR) determines
which bus will receive data when the enable OE is active LOW. In the
isolation mode (OE HIGH), A data may be stored in the B register or B
data may be stored in the A register. Only one of the two buses, A or B,
may be driven at one time.
•
•
•
•
•
•
•
•
•
•
Designed for 2.3 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 μA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 5
1
LOW−VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
DT SUFFIX
24−LEAD PLASTIC TSSOP PACKAGE
CASE 948H
DW SUFFIX
24−LEAD PLASTIC SOIC PACKAGE
CASE 751E
PIN NAMES
Pins
Function
A0−A7
B0−B7
CAB, CBA
SAB, SBA
DIR, OE
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
Publication Order Number:
MC74LCX646/D
MC74LCX646
VCC CBA SBA
OE
B0
B1
B2
B3
B4
B5
B6
B7
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
A0
A1
A2
A3
A4
A5
A6
A7
GND
CAB SAB DIR
Figure 1. Pinout: 24−Lead Package (Top View)
CBA
DIR
OE
SBA
SAB
CAB
1
3
21
22
2
23
C
Q
A0
D
C
Q
B0
D
1 of 8 Channels
To 7 Other Channels
Figure 2. LOGIC DIAGRAM
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MC74LCX646
TRUTH TABLE
Inputs
OE
DIR
H
X
L
L
H
h
L
l
X
↑
↑
QA
QB
*
=
=
=
=
=
=
=
=
=
=
Data Ports
CAB
CBA
SAB
SBA
↑
↑
X
X
↑
↑
X
X
H
↑
X*
↑
X*
↑
X*
↑
Bn
Input
Input
X
X
Isolation, Hold Storage
l
h
X
X
X
X
l
h
Store A and/or B Data
Input
Output
L
X
L
H
L
H
H
X
X
QA
L
X
l
h
L
H
Real Time A Data to B Bus; Store A
Data
H
X
L
H
QA
QA
Clock A Data to B Bus; Store A Data
Output
Input
L
X*
Operating Mode
An
Real Time A Data to B Bus
Stored A Data to B Bus
X
L
L
H
L
H
Real Time B Data to A Bus
X
H
QB
X
Stored B Data to A Bus
X
L
L
H
l
h
Real Time B Data to A Bus; Store B
Data
X
H
QB
QB
L
H
Clock B Data to A Bus; Store B Data
High Voltage Level
High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
Low Voltage Level
Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition
Don’t Care
Low−to−High Clock Transition
NOT Low−to−High Clock Transition
A input storage register
B input storage register
The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be
clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.
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MC74LCX646
BUS APPLICATIONS
BUS A
BUS A
BUS B
Real Time Transfer − Bus A to
Bus B
BUS B
Real Time Transfer − Bus B to
Bus A
OE
DIR
CAB
CBA
SAB
SBA
OE
DIR
CAB
CBA
SAB
SBA
L
L
X
X
X
L
L
H
X
X
L
X
BUS A
BUS A
BUS B
Transfer Storage Data to Bus A
or Bus B
BUS B
Store Data from Bus A, Bus B or
Busses A and B
OE
DIR
CAB
CBA
SAB
SBA
OE
DIR
CAB
CBA
SAB
SBA
X
X
H
X
X
X
↑
X
↑
X
↑
↑
X
X
X
X
X
X
L
L
L
H
X
H or L
H or L
X
X
H
H
X
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MC74LCX646
MAXIMUM RATINGS
Symbol
Parameter
VCC
DC Supply Voltage
VI
VO
Value
Condition
Unit
−0.5 to +7.0
V
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
V
DC Output Voltage
−0.5 ≤ VO ≤ +7.0
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Note 1.
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Output in HIGH or LOW State. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
2.0
1.5
3.3
3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
VCC
Supply Voltage
Operating
Data Retention Only
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current, VCC = 3.0 V − 3.6 V
−24
mA
IOL
LOW Level Output Current, VCC = 3.0 V − 3.6 V
24
mA
IOH
HIGH Level Output Current, VCC = 2.7 V − 3.0 V
−12
mA
IOL
LOW Level Output Current, VCC = 2.7 V − 3.0 V
TA
Operating Free−Air Temperature
Δt/ΔV
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
(HIGH or LOW State)
(3−State)
12
mA
−40
+85
°C
0
10
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
Condition
Min
VIH
HIGH Level Input Voltage (Note 2.)
2.7 V ≤ VCC ≤ 3.6 V
2.0
VIL
LOW Level Input Voltage (Note 2.)
2.7 V ≤ VCC ≤ 3.6 V
VOH
HIGH Level Output Voltage
VOL
Characteristic
LOW Level Output Voltage
Max
V
0.8
2.7 V ≤ VCC ≤ 3.6 V; IOH = −100 μA
VCC − 0.2
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
0.2
VCC = 2.7 V; IOL= 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
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V
V
2.7 V ≤ VCC ≤ 3.6 V; IOL = 100 μA
2. These values of VI are used to test DC electrical characteristics only.
Unit
V
MC74LCX646
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = −40°C to +85°C
Symbol
Characteristic
Condition
Min
Max
Unit
II
Input Leakage Current
2.7 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5.0
μA
IOZ
3−State Output Current
2.7 ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 5.5 V;
VI = VIH or V IL
±5.0
μA
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
μA
ICC
Quiescent Supply Current
2.7 ≤ VCC ≤ 3.6 V; VI = GND or VCC
10
μA
2.7 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±10
μA
2.7 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
500
μA
ΔICC
Increase in ICC per Input
AC CHARACTERISTICS (tR = tF = 2.5 ns; CL = 50 pF; RL = 500 Ω)
Limits
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V
Symbol
Parameter
Waveform
Min
Max
VCC = 2.7 V
Min
Max
Unit
fmax
Clock Pulse Frequency
3
150
MHz
tPLH
tPHL
Propagation Delay
Input to Output
1
1.5
1.5
7.0
7.0
1.5
1.5
8.0
8.0
ns
tPLH
tPHL
Propagation Delay
Clock to Output
3
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPLH
tPHL
Propagation Delay
Select to Output
1
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
8.5
8.5
1.5
1.5
9.5
9.5
ns
ts
Setup Time, HIGH or LOW Data to Clock
3
2.5
2.5
ns
th
Hold Time, HIGH or LOW Data to Clock
3
1.5
1.5
ns
tw
Clock Pulse Width, HIGH or LOW
3
3.3
3.3
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3.)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Condition
Min
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage (Note 4.)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
0.8
V
VOLV
Dynamic LOW Valley Voltage (Note 4.)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
0.8
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
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MC74LCX646
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
CPD
Power Dissipation Capacitance
Condition
Typical
Unit
VCC = 3.3 V, VI = 0 V or VCC
7
pF
VCC = 3.3 V, VI = 0 V or VCC
8
pF
10MHz, VCC = 3.3 V, VI = 0 V or VCC
25
pF
2.7 V
An, Bn,
SBA, SAB
1.5 V
0V
tPLH, tPHL
VOH
Bn, An
1.5 V
VOL
WAVEFORM 1 − SAB to B and SBA to A, An to Bn PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
OE
1.5 V
1.5 V
0V
DIR
tPHZ
tPZH
VOH − 0.3 V
1.5 V
An, Bn
≈0V
tPZL
An, Bn
tPLZ
≈ 3.0 V
1.5 V
VOL + 0.3 V
WAVEFORM 2 − OE/DIR to An/Bn OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
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MC74LCX646
2.7 V
An, Bn
1.5 V
0V
ts
th
2.7 V
CAB,
CBA
tw
1.5 V
1.5 V
0V
fmax
tPLH, tPHL
VOH
Bn, An
1.5 V
VOL
WAVEFORM 3 − CLOCK to Bn/An PROPAGATION DELAYS, CLOCK MINIMUM PULSE WIDTH,
An/Bn to CLOCK SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
tw
NEGATIVE
PULSE
1.5 V
1.5 V
POSITIVE
PULSE
1.5 V
1.5 V
tw
WAVEFORM 4 − INPUT PULSE DEFINITION
tR = tF = 2.5 ns, 10% to 90% of 0 V to 2.7 V
Figure 4. AC Waveforms
VCC
PULSE
GENERATOR
R1
DUT
RT
CL
TEST
RL
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
GND
CL = 50 pF or equivalent (Includes jig and probe capacitance)
RL = R1 = 500 Ω or equivalent
RT = ZOUT of pulse generator (typically 50 Ω)
Figure 5. Test Circuit
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6V
OPEN
GND
MC74LCX646
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948H−01
ISSUE O
24X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
2X
L/2
24
13
B
−U−
L
PIN 1
IDENT.
12
1
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
A
−V−
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
C
0.10 (0.004)
−T− SEATING
PLANE
G
D
H
−W−
DETAIL E
N
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
0.25 (0.010)
K1
J1
M
N
F
SECTION N−N
DETAIL E
J
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MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74LCX646
PACKAGE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E−04
ISSUE E
−A−
24
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
13
−B−
12X
P
0.010 (0.25)
1
M
B
M
12
24X
D
J
0.010 (0.25)
M
T A
S
B
S
F
R
X 45 _
C
−T−
SEATING
PLANE
22X
G
K
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0_
8_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0_
8_
0.395
0.415
0.010
0.029
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74LCX646/D