Quad TTL to MECL Translator

MC10124
Quad TTL to MECL
Translator
The MC10124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The MC10124 has TTL compatible inputs, and
MECL complementary open–emitter outputs that allow use as an
inverting/ non–inverting translator or as a differential line driver.
When the common strobe input is at the low logic level, it forces all
true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels
are standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level information can be
transmitted differentially, via balanced twisted pair lines, to the MECL
equipment, where the signal can be received by the MC10115 or
MC10116 differential line receivers. The MC10124 is useful in
computers, instrumentation, peripheral controllers, test equipment,
and digital communications systems.
• PD = 380 mW typ/pkg (No Load)
• tpd = 3.5 ns typ (+ 1.5 Vdc in to 50% out)
• tr, tf = 2.5 ns typ (20%–80%)
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10124L
AWLYYWW
1
16
PDIP–16
P SUFFIX
CASE 648
MC10124P
AWLYYWW
1
1
PLCC–20
FN SUFFIX
CASE 775
10124
AWLYYWW
LOGIC DIAGRAM
5
6
4
2
7
3
1
10
12
15
11
13
14
PIN 16
PIN 9
PIN 8
Gnd
=
VCC (+5.0Vdc) =
VEE (-5.2Vdc) =
A
WL
YY
WW
ORDERING INFORMATION
Device
DIP PIN ASSIGNMENT
BOUT
1
16
GND
AOUT
2
15
COUT
BOUT
3
14
DOUT
AOUT
4
13
DOUT
AIN
5
12
COUT
COMMON
6
11
DIN
7
10
CIN
8
9
VCC
STROBE
BIN
VEE
= Assembly Location
= Wafer Lot
= Year
= Work Week
Package
Shipping
MC10124L
CDIP–16
25 Units / Rail
MC10124P
PDIP–16
25 Units / Rail
MC10124FN
PLCC–20
46 Units / Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
 Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10124/D
MC10124
ELECTRICAL CHARACTERISTICS
Test Limits
Symbol
Pin
Under
Test
Max
Unit
Negative Power Supply
Drain Current
IE
8
72
66
72
mAdc
Positive
os e Power
o e Su
Supply
y
Drain Current
ICCH
9
16
16
18
mAdc
ICCL
9
25
25
25
mAdc
Reverse Current
IR
6
7
200
50
200
50
200
50
µAdc
Forward Current
IF
6
7
–12.8
–3.2
–12.8
–3.2
–12.8
–3.2
mAdc
BVin
6
7
Clamp Input Voltage
VI
6
7
High Output Voltage
VOH
1
3
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
Low Output Voltage
VOL
1
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
High Threshold Voltage
VOHA
1
3
–1.080
–1.080
Low Threshold Voltage
VOLA
1
3
Characteristic
Input Breakdown Voltage
Switching Times
Load)
–30°C
Min
+25°C
Max
5.5
5.5
Min
Typ
+85°C
Max
5.5
5.5
Min
5.5
5.5
–1.5
–1.5
–1.5
–1.5
–0.980
–0.980
Vdc
–1.5
–1.5
Vdc
–0.890
–0.890
–0.700
–0.700
Vdc
–1.825
–1.825
–1.615
–1.615
Vdc
–0.910
–0.910
–1.655
–1.655
–1.630
–1.630
Vdc
–1.595
–1.595
(50Ω
Propagation Delay
(+3.5Vdc to 50%)1
Vdc
ns
t6+1+
t6–1–
t7+1+
t7–1–
t7+3–
t7–3+
1
1
1
1
3
3
1.5
1.0
1.5
1.0
1.5
1.0
6.8
6.0
6.8
6.0
6.8
6.0
1.0
1.0
1.0
1.0
1.0
1.0
3.5
3.5
3.5
3.5
3.5
3.5
6.0
6.0
6.0
6.0
6.0
6.0
1.0
1.5
1.0
1.5
1.0
1.5
6.0
6.8
6.0
6.8
6.0
6.8
Rise Time
(20 to 80%)
t1+
1
1.0
4.2
1.1
2.5
3.9
1.1
4.3
Fall Time
(20 to 80%)
t1–
1
1.0
4.2
1.1
2.5
3.9
1.1
4.3
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIH
VILmax
VIHA’
VILA’
VF
–30°C
+4.0
+0.40
+2.00
+1.10
+0.40
+25°C
+4.0
+0.40
+1.80
+1.10
+0.40
+85°C
+4.0
+0.40
+1.80
+0.90
+0.40
Symbol
Pin
Under
Test
Negative Power Supply Drain
Current
IE
8
Positive
Supply
os e Power
o e Su
y Drain
a
Current
ICCH
9
ICCL
9
Reverse Current
IR
6
7
Forward Current
IF
6
7
BVin
6
7
5,7,10,11,16
6,16
Clamp Input Voltage
VI
6
7
16
16
High Output Voltage
VOH
1
3
Characteristic
Input Breakdown Voltage
Low Output Voltage
VOL
High Threshold Voltage
Low Threshold Voltage
Switching Times
VOHA
VOLA
VIH
VILmax
VIHA’
VILA’
VF
Gnd
16
5,6,7,10,11
16
5,6,7,10,11,16
5,7,10,11
6
6,7
6,7
1
3
6
6
1
3
6
6
5,7,10,11
6
16
16
6
7
16
16
16
16
6,7
1
3
(50Ω Load)
Propagation Delay
(+3.5Vdc to 50%)1
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
6,7
16
16
7
7
7
16
16
7
16
16
+6.0 V
Pulse In
Pulse Out
+2.0 V
t6+1+
t6–1–
t7+1+
t7–1–
t7+3–
t7–3+
1
1
1
1
3
3
7
7
6
6
6
6
6
6
7
7
7
7
1
1
1
1
3
3
16
16
16
16
16
16
Rise Time
(20 to 80%)
t1+
1
6
7
1
16
Fall Time
(20 to 80%)
t1–
1
6
7
1
16
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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MC10124
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
(mA)
VR
VCC
VEE
II
Iin
–30°C
+2.40
+5.00
–5.2
–10
+1.0
+25°C
+2.40
+5.00
–5.2
–10
+1.0
+85°C
+2.40
+5.00
–5.2
–10
+1.0
Symbol
Pin
Under
Test
Negative Power Supply Drain
Current
IE
Positive
Supply
os e Power
o e Su
y Drain
a
Current
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VCC
VEE
8
9
8
16
ICCH
9
9
8
16
ICCL
9
9
8
5,6,7,10,11,16
Reverse Current
IR
6
7
9
9
8
8
16
16
Forward Current
IF
6
7
9
9
8
8
16
16
BVin
6
7
9
9
8
8
Clamp Input Voltage
VI
6
7
9
9
8
8
High Output Voltage
VOH
1
3
9
9
8
8
16
16
Low Output Voltage
VOL
1
3
9
9
8
8
16
16
High Threshold Voltage
VOHA
1
3
9
9
8
8
16
16
Low Threshold Voltage
VOLA
1
3
9
9
8
8
16
16
+7.0 V
–3.2 V
+2.0 V
Characteristic
Input Breakdown Voltage
Switching Times
VR
6
7
(50Ω Load)
Propagation Delay
(+3.5Vdc to 50%)1
II
Iin
6
7
6
7
Gnd
5,7,10,11,16
6,16
16
16
t6+1+
t6–1–
t7+1+
t7–1–
t7+3–
t7–3+
1
1
1
1
3
3
9
9
9
9
9
9
8
8
8
8
8
8
16
16
16
16
16
16
Rise Time
(20 to 80%)
t1+
1
9
8
16
Fall Time
(20 to 80%)
t1–
1
9
8
16
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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4
MC10124
SWITCHING TIME TEST CIRCUIT
+6.0 Vdc
Vin
Coax
0.1 µF
VCC
Vout
NAND
+7.0 Vdc
25 µF
Pulse Generator
Input Pulse
t+ = t- = 5.5 ±0.5 ns
(10 to 90%)
0.1 µF
5
6
4
2
7
3
1
10
12
15
11
13
14
Input
16
0.1 µF
Vout
AND
Coax
Unused outputs connected to a
50-ohm resistor to ground.
8
25 µF
0.1 µF
50-ohm termination to ground located in each scope channel input.
+ 2.0 Vdc
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
VEE
-3.2 Vdc
NOTE: All power supply and logic levels are shown
shifted 2 volts positive.
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5
Coax
MC10124
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
0.007 (0.180)
B
Y BRK
–N–
M
T L-M
0.007 (0.180)
U
M
N
S
T L-M
S
G1
0.010 (0.250)
S
N
S
D
–L–
–M–
Z
W
20
D
1
X
V
S
T L-M
S
N
S
VIEW D–D
A
0.007 (0.180)
M
T L-M
S
N
S
R
0.007 (0.180)
M
T L-M
S
N
S
Z
0.007 (0.180)
H
M
T L-M
S
N
S
K1
K
C
E
F
0.004 (0.100)
G
J
–T–
VIEW S
G1
0.010 (0.250) S T L-M
S
N
S
0.007 (0.180)
M
T L-M
S
VIEW S
SEATING
PLANE
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
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6
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
--0.025
--0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
--0.020
2
10 0.310
0.330
0.040
---
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
--0.64
--8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2
10 7.88
8.38
1.02
---
N
S
MC10124
PACKAGE DIMENSIONS
–A–
16
9
1
8
–B–
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
S
T A
M
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7
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
--0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
15 0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
--5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
15 0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
10 0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
10 0.51
1.01
MC10124
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC10124/D