MC10135 Dual J-K Master-Slave Flip-Flop The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro– nous set (S) and reset (R) are provided. The set and reset inputs override the clock. A common clock is provided with separate J–K inputs. When the clock is static, the J–K inputs do not effect the output. The output states of the flip–flop change on the positive transition of the clock. • PD = 280 mW typ/pkg (No Load) • fTog = 140 MHz typ • tpd = 3.0 ns typ • tr, tf = 2.5 ns typ (20%–80%) DIP PIN ASSIGNMENT S1 5 VCC1 1 16 VCC2 J1 7 Q1 2 15 Q2 K1 6 Q1 3 14 Q2 R1 4 13 R2 S1 5 12 S2 K1 6 11 K2 J1 7 10 J2 9 C VEE 8 http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 LOGIC DIAGRAM Q1 2 Q1 3 PDIP–16 P SUFFIX CASE 648 1 1 C 9 PLCC–20 FN SUFFIX CASE 775 S2 12 J2 10 Q2 15 K2 11 Q2 14 A WL YY WW R2 13 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 CLOCK J–K TRUTH TABLE* R S Qn+1 J K Qn+1 L L H H L H L H Qn H L N.D. L H L H L L H H Qn L H Qn Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 10135 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device N.D. = Not Defined MC10135P AWLYYWW R1 4 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). R–S TRUTH TABLE MC10135L AWLYYWW Package Shipping MC10135L CDIP–16 25 Units / Rail MC10135P PDIP–16 25 Units / Rail MC10135FN PLCC–20 46 Units / Rail * Output states change on positive transition of clock for J–K input condition present. 1 Publication Order Number: MC10135/D MC10135 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Power Supply Drain Current IE 8 75 IinH 6,7,9,10,11 4,5,12,13 425 620 IinL 4,5,6,7,9, 10,11,12,13 0.5 0.5 Input Current –30°C Min +25°C Max Min +85°C Typ Max Max Unit 54 68 75 mAdc 265 390 265 390 µAdc 0.5 0.5 Min µAdc 0.3 0.3 Output Voltage Logic 1 VOH 2 2 (3.) –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 3 3 (3.) –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 2 (4.) –1.080 –1.080 Threshold Voltage Logic 0 VOLA 3 3 (4.) –0.980 –0.980 –0.910 –0.910 –1.655 –1.655 –1.630 –1.630 Vdc –1.595 –1.595 Switching Times (50Ω Load) Clock Input Propagation Delay Vdc ns t9+2+ t9+2– 2 2 1.8 1.8 5.0 5.0 1.8 1.8 3.0 3.0 4.5 4.5 1.8 1.8 4.6 4.6 Rise Time (20 to 80%) t2+, t3+ 2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7 Fall Time (20 to 80%) t2–, t3– 2, 3 1.1 4.8 1.1 2.0 4.5 1.1 4.7 Set Input ns Propagation Delay t5+2+ t12+15+ t5+3– t12+14– 2 15 3 14 1.8 1.8 1.8 1.8 5.6 5.6 5.6 5.6 1.8 1.8 1.8 1.8 3.0 3.0 3.0 3.0 5.0 5.0 5.0 5.0 1.8 5.2 5.2 5.2 5.2 Reset Input Propagation Delay ns t4+2– t4+3– t13+15– t13+14+ 2 3 15 14 1.8 1.8 1.8 1.8 Setup Time tsetup 7 Hold Time thold 7 Toggle Frequency (Max) ftog 2 5.6 5.6 5.6 5.6 1.8 1.8 1.8 1.8 3.0 3.0 3.0 3.0 2.5 2.5 1.0 2.5 ns 1.5 1.5 1.0 2.5 ns 125 125 140 125 MHz 1. Individually test each input; apply VIHmax to pin under test. 2. Individually test each input; apply VILmin to pin under test. 3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) http://onsemi.com 2 5.0 5.0 5.0 5.0 1.8 1.8 1.8 1.8 VIHmax VILmin VIHAmax VILAmin 5.2 5.2 5.2 5.2 MC10135 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 6,7,9,10,11 4,5,12,13 IinL 4,5,6,7,9, 10,11,12,13 TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax Note 1. Note 1. Note 2. Note 2. VEE (VCC) Gnd 8 1, 16 8 8 1, 16 1, 16 8 8 1, 16 1, 16 Output Voltage Logic 1 VOH 2 2 (3.) 5 6 8 8 1, 16 1, 16 Output Voltage Logic 0 VOL 3 3 (3.) 5 6 8 8 1, 16 1, 16 Threshold Voltage Logic 1 VOHA 2 2 (4.) 5 6 8 8 1, 16 1, 16 3 3 (4.) 5 6 8 8 1, 16 1, 16 Threshold Voltage Switching Times Clock Input Logic 0 VOLA (50Ω Load) Propagation Delay Pulse In Pulse Out –3.2 V +2.0 V t9+2+ t9+2– 2 2 9 9 2 2 8 8 1, 16 1, 16 Rise Time (20 to 80%) t2+, t3+ 2, 3 9 2, 3 8 1, 16 Fall Time (20 to 80%) t2–, t3– 2, 3 9 2, 3 8 1, 16 Propagation Delay t5+2+ t12+15+ t5+3– t12+14– 2 15 3 14 5 12 5 12 2 15 3 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Propagation Delay t4+2– t4+3– t13+15– t13+14+ 2 3 15 14 4 4 13 13 2 3 15 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 Setup Time tsetup 7 6, 9 2 8 1, 16 Hold Time thold 7 6, 9 2 8 1, 16 Toggle Frequency (Max) ftog 2 9 2 8 1, 16 Set Input Reset Input 1. Individually test each input; apply V IHmax to pin under test. 2. Individually test each input; apply VILmin to pin under test. 3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6) VIHmax VILmin VIHAmax VILAmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 3 MC10135 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 4 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10135 PACKAGE DIMENSIONS –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M http://onsemi.com 5 INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 MC10135 Notes http://onsemi.com 6 MC10135 Notes http://onsemi.com 7 MC10135 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 MC10135/D