NCP1927: Combination Power Factor Correction Controller and Flyback Controller for Flat Panel TV

NCP1927
Combination Power Factor
Correction Controller and
Flyback Controller for Flat
Panel TVs
MARKING DIAGRAM
POVUV
IENABLE
PFB
PSKIP
Shutdown
PDRV
PControl
PCT
PZCD
SOIC−16
CASE 751B
A
WL
Y
WW
G
VCC
FDRV
GND
PCS
FFB
GTS
FCS
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Common General Features
• Wide VCC Range from 10 V to 30 V
• Very Low Startup Current Consumption
•
•
•
•
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NCP1927
AWLYWWG
This combination IC integrates the primary side control blocks −
power factor correction (PFC) and flyback controllers with
sequencing circuitry − necessary to implement a compact highly
efficient Flat Panel TV Switched Mode Power Supply.
The PFC controller exhibits near−unity power factor while
operating in Critical Conduction Mode (CrM) with an internal
frequency clamp. The circuit incorporates all the features necessary
for building a robust and compact PFC stage while minimizing the
number of external components.
The fixed−frequency current−mode flyback controller features a
proprietary Soft−Skip™ mode combined with frequency foldback
enabling excellent efficiency during light load conditions while
achieving very low standby power consumption. Soft−Skip
dramatically reduces the risk of acoustic noise, therefore enabling the
use of inexpensive transformers and capacitors in the clamping
network. Frequency jittering and ramp compensation make this
controller an excellent fit for converters where ruggedness and
component cost are the key constraints.
Package
Shipping†
SOIC−16
(Pb−Free)
2500 / Tape & Reel
Device
NCP1927DR2G
(v 20 mA MAX)
Inverter Enable Output
Shutdown Pin to Disable IC
Go To Standby Input
This is a Pb−Free Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
PFC Controller Features
• Critical Conduction Mode (CrM) with Constant On
•
•
•
•
•
•
•
Flyback Controller Features
• 65 kHz Fixed−Frequency Operation with Built−In
Time Control
Internal Frequency Clamp
Skip Mode Operation During Light Load Conditions
Fast Line / Load Transient Compensation
Accurate and Programmable Maximum On Time
Control
Negative Current Sensing
Programmable Overvoltage/Undervoltage Protection
800 mA Source / 1200 mA Sink Gate Drive
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 0
•
•
•
•
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•
1
Ramp Compensation
Frequency Jittering for Softened EMI Signature
Frequency Foldback then Soft−Skip for Improved
Performance in Standby
Timer−Based Overload Protection with Auto−Recovery
Protection Against Winding Short−Circuit
4 ms Soft−Start Timer
800 mA Source / 1200 mA Sink Gate Drive
Publication Order Number:
NCP1927/D
Line Input
F1
R2
R1
CX1
L1
L2
CX2
DB1
C1
T1
R4
R5
R3
Q1
D1
D2
Figure 1. Typical Application Example
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2
R7
D6
R6
C2
VCC_AUX
C10
R16
ZD1
C11
R15
R14
VCC_AUX
U5
OVP
on / off
R9
R8
R19
PSKIP
GND
FFB
PCS
C13
FCS
GTS
NCP1927
FDRV
PZCD
VCC
PCT
PControl
Shutdown PDRV
PFB
POVUV IENABLE
U1
R11
R10
HV to Inverter
C15
C9
R23
R18
R17
D4
D3
R22
U4
R27
D7
R26
R28
Inverter Enable
C8
R25
R24
VCC_AUX
D5
R21
C12
Q2
T2
CY1
U3
C5
D9
C3
D8
U6
C14
R30
R29
L4
L3
C6
C4
C7
R33
on / off
on / off
R32
13 V
5.3V
5.3 V Standby
NCP1927
NCP1927
Flyback_OVLD
VDD
Latch
GOS Timer
IShutdown
Shutdown
30 ms
Filter
GTS
PFC FAULT MANAGEMENT
GTS Timer
Vstandby
30 ms
Filter
VUVP
POVUV
IUVP
30 ms
Filter
30 ms
Filter
TSD
OVP_int
VOVP
VCC & LATCH MANAGEMENT
RGTS
FFAULT
CS_STOP
Shutdown
VSHDN
VCC
VDD Reg
VCC(on)
VDD
5V Reg
VCC(off)
SS_enable
FFAULT
START_DELAY
PFAULT
PFC_OK
VCC(reset)
Vdisable
30 ms
Filter
VDD
RR
Q
VFFB(open)
Saw In
Saw
S
Soft−Skip
Timer Reset
IPControl(boost)
PFC_OK
IENABLE
RFFB
FFB
VFSKIP
Skip Out
B5
0.955*VREF
FFAULT
Timer
FFAULT
VILIM
Reset
PFB
VREF
10 ms
Filter
0 mA
Detect
Flyback_OVLD
PControl
LEB
PFAULT
Ramp
R
VDD
9*R
IPSKIP
SS_enable
Soft−Start
Timer
SS_end
CS_STOP
VILIM
VCS(stop)
PSKIP
LEB
START_DELAY
PFC_OK
FFAULT
VDD
Saw
Rramp
VCC
Latch
Clamp
Shutdown
IPCT(charge)
FCS
tON(MAX)
Timer
RR
PCT
Q
FDRV
S
PDRV
FFB
Frequency
Foldback
PFM SQUARE
OSC
Jittering
SS_end
PCS
R
IPCS > IOCP
Q
FM
START_DELAY
S
S
PFAULT
PDRV
VZCD(rising)
S
R
PZCD
Q
DRV CLK
PDRV
ZCD
Reset
WDT
Frequency Clamp
VZCD(falling)
* Values are typical values
* All latches are Reset Dominant
Q
VCC
Clamp
PDRV
R
OVP_int
PDRV
Saw
S AW
Figure 2. Internal Block Diagram
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3
GND
NCP1927
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
POVUV
Pin Description
2
PFB
3
Shutdown
Pull this pin above 1.0 V (typ) to disable the part. Ground this pin when not in use.
4
PControl
The error amplifier output is available on this pin. The capacitor connected between this pin and
ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve a high power
factor. This pin is internally grounded when the circuit is off so that when it starts operation, the power
increases gradually (soft−start).
5
PCT
The PCT pin sources a 210 mA (typ) current to charge an external timing capacitor. The circuit
controls the power switch on time by comparing the PCT voltage to an internal voltage derived from
the regulation block.
6
PZCD
The voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized
for operation in critical conduction mode.
7
PCS
This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the
maximum coil current and protect the PFC stage during overload conditions.
8
GTS
Pull this pin low to disable the PFC controller during standby mode. Standby mode can also be
entered by monitoring the feedback voltage of the flyback stage with an external resistor divider.
9
FCS
This pin senses the primary current for current−mode operation of the flyback stage. Ramp
compensation can be added with an external resistor.
10
FFB
Connecting this pin to ground through an optocoupler allows regulation of the flyback stage.
11
GND
This is the the controller ground.
12
FDRV
This is the driver’s output to an external MOSFET gate of the flyback power stage.
13
VCC
14
PDRV
This is the driver’s output to an external MOSFET gate of the PFC power stage.
15
PSKIP
To adjust the power level below which the PFC stage will enter skip mode, connect a resistor between
this pin and ground. To disable skip mode, connect this pin directly to ground.
16
IENABLE
This pin voltage is high (5 V) when the output of the PFC stage is in steady state regulation and low
at all other times. This signal serves to “inform” the backlight inverter that the PFC output is ready and
that it can start operation. It can also be used as a stable 5 V reference.
The gate drive is disabled while VPOVUV is below VUVP (300 mV typ) or above VOVP (2.5 V typ).
This pin receives a portion of the pre−converter output voltage. This information is used for the
regulation and the “output low” detection that speeds up the loop response when the output voltage
drops below 95.5% (typ) of the programmed level.
This pin is connected to an external auxiliary voltage.
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NCP1927
MAXIMUM RATINGS (Note 1)
Rating
Symbol
Value
Unit
VCC(MAX)
ICC(MAX)
−0.3 to 30
$30
V
mA
PFC Drive Pin (pin 14) (Note 2)
Voltage Range
Current Range
VPDRV(MAX)
IPDRV(MAX)
−0.3 to 20
−800, +1200
V
mA
Flyback Drive Pin (pin 12) (Note 2)
Voltage Range
Current Range
VFDRV(MAX)
IFDRV(MAX)
−0.3 to 20
−800, +1200
V
mA
Inverter Enable Pin (pin 16) (Note 2)
Voltage Range
Current Range
VIENABLE(MAX)
IIENABLE(MAX)
−0.3 to 6
$20
V
mA
Control Pin (pin 4) (Note 2)
Voltage Range
Current Range
VPControl(MAX)
IPControl(MAX)
−0.3 to 6
$10
V
mA
PFC Current Sense Pin (pin 7) (Note 2)
Voltage Range
Current Range
VPCS(MAX)
IPCS(MAX)
−0.3 to 3
$10
V
mA
ZCD Pin (pin 6) (Note 2)
Voltage Range
Current Range
VPZCD(MAX)
IPZCD(MAX)
−0.9 to 12
$10
V
mA
VMAX
IMAX
−0.3 to 10
$10
V
mA
RθJA
140
°C/W
TJSTRG(MAX)
TJ(MAX)
−60 to 150
−25 to 125
Supply Pin (pin 13) (Note 2)
Voltage Range
Current Range
All Other Pins (Note 2)
Voltage Range
Current Range
Thermal Resistance
Junction−to−Air, 100 mm2 Single Layer of 1 oz Copper
Temperature Range
Storage Temperature
Operating Junction Temperature
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Charged Device Model 2000 V per JEDEC Standard JESD22-C101D
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model 200 V per JEDEC Standard JESD22−A115A
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1927
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VPFB = 2.4 V, VPOVUV = 2.3 V, VPControl = 4 V, VPZCD = 0 V, VPCS = 0 V, VGTS =
1 V, VPSKIP = 0 V, VFFB = 2.4 V, VFCS = 0 V, VShutdown = 0 V, VIENABLE = open, CPCT = 1 nF, CPDRV = 1 nF, CFDRV = 1 nF, for typical
values TJ = 25°C, for min/max values, TJ is − 25°C to 125°C, unless otherwise noted)
Test Condition
Symbol
Min
Typ
Max
VCC increasing, dV/dt = 1.25 mV/ms
VCC decreasing, dV/dt = 125 mV/ms
VCC decreasing
VCC(on)
VCC(off)
VCC(reset)
16
8
5.0
17
9
6.5
18
10
8.0
CFDRV = open, CPDRV = open
ICC1
ICC2
ICC3
2.4
3.8
1.0
3.3
5.1
1.5
4.2
6.4
2.0
mA
mA
mA
ICC4
ICC5
1.0
−
1.5
−
2.5
20
mA
mA
Equivalent Internal Pull−Up Resistor
RFFB
14
20
31
kW
VFFB to Internal Current Setpoint
Division Ratio
KFFB
4.8
5.0
5.2
tdelay(FOVLD)
−
10
−
ms
VFFB = 4.5 V to FDRV turn−off
tFOVLD
60
80
100
ms
VFFB = open
VFFB(open)
4.5
5.0
5.5
V
VFFB = 4.5 V
VILIM
0.655
0.700
0.725
V
tLEB
190
250
310
ns
tdelay(ILIM)
tCS(stop)
−
−
80
80
110
110
ns
ns
VCS(stop)
0.95
1.05
1.15
V
tLEB(stop)
90
120
150
ns
Characteristics
Unit
SUPPLY CIRCUIT
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Internal latch reset level
Supply Current
PFC is switching at 70kHz
PFC is switching at 70kHz
Flyback Switching, PFC is in GTS
During Faults
Startup
VFFB = Vfold − 0.2 V, CFDRV = open,
VFCS = 0.8 V
VCC = VCC(on) − 0.2 V
V
FLYBACK FEEDBACK
Overload Detection Filter
Flyback Fault Timer
FFB Pin Voltage
FLYBACK CURRENT SENSE
Current Sense Voltage Threshold
Leading Edge Blanking Duration
Propagation Delay
Current Sense Voltage Threshold
Immediate Fault Protection
Step VFCS 0 V to 2 V, to FDRV
falling edge
Immediate Fault Protection Threshold
VFFB = 3 V, VFCS dV/dt = 500 mV/ms
Leading Edge Blanking Duration for
ICS(stop)
Input Bias Current
VFCS = VILIM
IFCS(bias)
−1
−
+1
mA
VFCS = 0 V, 80% Duty Ratio
Iramp(MAX)
100
150
200
mA
1st FDRV pulse to VFCS = VILIM
tSSTART
2.8
4.0
5.2
ms
Base Oscillator Frequency
fOSC
60
65
70
kHz
Maximum Duty Ratio
DMAX
76
80
84
%
Frequency Modulation in Percentage of
fOSC
fMOD
−
$6
−
%
fjitter
−
125
−
Hz
fOSC(VSTAB)
−1
−
+1
%
Current Sourced by the FCS Pin
FLYBACK SOFT−START
Soft−Start Period
OSCILLATOR
Frequency Modulation Frequency
Oscillator Frequency Voltage Stability
VCC(MIN) < VCC < VCC(MAX)
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NCP1927
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VPFB = 2.4 V, VPOVUV = 2.3 V, VPControl = 4 V, VPZCD = 0 V, VPCS = 0 V, VGTS =
1 V, VPSKIP = 0 V, VFFB = 2.4 V, VFCS = 0 V, VShutdown = 0 V, VIENABLE = open, CPCT = 1 nF, CPDRV = 1 nF, CFDRV = 1 nF, for typical
values TJ = 25°C, for min/max values, TJ is − 25°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
VFDRV = 10 V
VFDRV = 2 V
RFDRV(SNK)
RFDRV(SRC)
−
−
12.5
14
−
−
W
W
FDRV Rise Time (10% to 90%)
tFDRV(r)
15
30
80
ns
FDRV Fall Time (90% to 10%)
tFDRV(f)
12
25
70
ns
FLYBACK GATE DRIVE
FDRV Impedance
Sink
Source
FDRV Low Voltage
IFDRV = 0 mA
VFDRV(low)
−
0.06
0.5
V
FDRV Voltage Drop
VCC = VCC(off) + 0.2 V,
RFDRV = 33 kW
VFDRV(drop)
−
−
1
V
VCC = 30 V, IFDRV = 0 mA
VFDRV(clamp)
11
13.5
16
V
VFFB Decreasing
VFSKIP
630
700
770
mV
VFSKIP(HYS)
65
100
135
mV
tSSKIP
50
100
140
ms
FDRV Clamp Voltage
FLYBACK SKIP MODE/FREQ FOLDBACK
Skip Threshold
Skip Comparator Hysteresis
Soft−Skip Duration
1st
Pulse to VFCS = Vfold/KFFB
Frequency Foldback Threshold
VFFB Decreasing, dV/dt = 500 mV/ms
Vfold
1.26
1.40
1.54
V
Minimum Switching Frequency
VFFB = VFSKIP + 150 mV
fOSC(MIN)
21
26
31
kHz
Frequency Foldback or Skip Mode
ton(MAX)
10.0
13.0
16.0
ms
RPCS = 2.5 kW, IPCS = 265 mA
VPCS
−20
0
20
mV
RPCS = 2.5 kW
IOCP
230
250
265
mA
step IPCS 0 mA to 400 mA
IOCP to PDRV falling edge
RPCS = 1 kW
tOCP
−
100
210
ns
PCT Charge Current
VPCT = 1.5 V
IPCT(charge)
189
210
231
mA
CPCT Discharge Time
VPControl = open, CPControl = 10 nF
VPCT = VPCT(MAX) −100 mV to
600 mV
tCPCT(discharge)
−
−
500
ns
Maximum PCT Level Before PDRV
Switches Off
VPControl = open, CPControl = 10 nF
VPCT(MAX)
4.7
5.0
5.3
V
step VPCT from 3.5 V to 5.0 V
tPWM
−
150
200
ns
fclamp
330
385
440
kHz
RPDRV(SNK)
RPDRV(SRC)
−
−
12.5
14
−
−
W
W
PDRV Rise Time (10 % to 90 %)
tPDRV(r)
15
30
80
ns
PDRV Fall Time (90 % to 10 %)
tPDRV(f)
12
25
70
ns
Maximum On Time
PFC CURRENT SENSE
PCS Pin Voltage
Overcurrent Protection Threshold
Propagation Delay
PFC RAMP CONTROL
Propagation Delay of the PWM
Comparator
PFC Frequency Clamp
PFC GATE DRIVE
PDRV Impedance
Sink
Source
VPDRV = 10 V
VPDRV = 2 V
PDRV Low Voltage
IPDRV = 0 mA
VPDRV(low)
−
0.06
0.5
V
PDRV Voltage Drop
VCC = VCC(off) + 0.2 V,
RPDRV = 33 kW
VPDRV(drop)
−
−
1
V
VCC = 30 V, IPDRV = 0 mA
VPDRV(clamp)
11
13.5
16
V
PDRV Clamp Voltage
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7
NCP1927
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VPFB = 2.4 V, VPOVUV = 2.3 V, VPControl = 4 V, VPZCD = 0 V, VPCS = 0 V, VGTS =
1 V, VPSKIP = 0 V, VFFB = 2.4 V, VFCS = 0 V, VShutdown = 0 V, VIENABLE = open, CPCT = 1 nF, CPDRV = 1 nF, CFDRV = 1 nF, for typical
values TJ = 25°C, for min/max values, TJ is − 25°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
VZCD(rising)
VZCD(falling)
1.12
0.56
1.40
0.70
1.68
0.84
Unit
PFC ZERO CURRENT DETECTION
Zero Current Detection Threshold
Rising
Falling
Hysteresis on Voltage Threshold
V
VZCD(rising) − VZCD(falling)
VZCD(HYS)
560
700
840
mV
Propagation Delay
Step VPZCD from 2 V to 0 V
tZCD
−
100
170
ns
Clamp Voltage
Upper Clamp
Negative Clamp
IPZCD = 3 mA
IPZCD = −2 mA
VCL(POS)
VCL(NEG)
8
−0.9
10
−0.7
12
0
tSYNC
−
70
100
Minimum detectable ZCD pulse width
V
ns
Maximum Off Time
PDRV off = 10% to PDRV on = 90%
tstart
75
180
300
ms
Input Bias Current
VPZCD = 5 V
VPZCD = −0.2 V
IPZCD(bias)
IPZCD(bias)
−2
−2
−
−
2
2
mA
mA
IPSKIP
27
30
33
mA
VPSKIP(HYS)
10
12
16
%
VREF
2.463
2.500
2.537
V
VPFB = 2.4 V, VPOVUV = 3 V
VPFB = 2.6 V, VPOVUV = 3 V
IEA(SRC)
IEA(SNK)
16
16
20
20
24
24
mA
mA
VPFB = VREF $ 100 mV,
VPOVUV = 3 V
gm
100
200
300
mS
VPFB = 2.5 V
IPFB(bias)
−0.5
−
0.5
mA
Maximum EA Output Voltage
VPFB = 2 V
VPControl = open, CPControl = 10 nF
VPControl(MAX)
5.05
5.6
6.1
V
Minimum EA Output Voltage
VPFB = 3 V
VPControl = open, CPControl = 10 nF
VPControl(MIN)
0.35
0.6
0.8
V
VPControl(MAX) − VPControl(MIN)
DVPControl
4.7
5.0
5.3
V
Ratio (Vout Low Detect Threshold /
VREF)
VOLOW/VREF
95.0
95.5
96.0
%
Vout Low Detect / VREF Hysteresis
VOLOW(HYS)/
VREF
−
−
1.0
%
Source Current During VOUT Low
Detect
IPControl(boost)
190
240
290
mA
PFC SKIP MODE
Skip Pin Internal Current Source
Hysteresis of the skip cycle detection
level
VPSKIP = 1 V
PFC REGULATION BLOCK
Voltage Reference
Error Amplifier Current Capability
Maximum Source Current
Maximum Sink Current
Error Amplifier Transconductance
PFB Bias Current
EA Output Regulation Voltage Swing
GO TO STANDBY (GTS)
Internal Pull−Down Resistor
Standby Threshold
VGTS Decreasing
Standby Hysteresis
Go To Standby Timer
Step VGTS from 1 V to 0 V
Step VGTS from 0 V to 1 V
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8
RGTS
80
200
320
kW
Vstandby
270
300
330
mV
Vstandby(HYS)
85
100
125
mV
tGTS(off)
tGTS(on)
37.5
30
50.0
50
62.5
70
ms
ms
NCP1927
ELECTRICAL CHARACTERISTICS (VCC = 12 V, VPFB = 2.4 V, VPOVUV = 2.3 V, VPControl = 4 V, VPZCD = 0 V, VPCS = 0 V, VGTS =
1 V, VPSKIP = 0 V, VFFB = 2.4 V, VFCS = 0 V, VShutdown = 0 V, VIENABLE = open, CPCT = 1 nF, CPDRV = 1 nF, CFDRV = 1 nF, for typical
values TJ = 25°C, for min/max values, TJ is − 25°C to 125°C, unless otherwise noted)
Characteristics
Test Condition
Symbol
Min
Typ
Max
Unit
Overvoltage Protection Threshold
VOVP
2.450
2.500
2.550
V
Overvoltage Protection Hysteresis
VOVP(HYS)
20
40
60
mV
Overvoltage Protection Filter Delay
tdelay(OVP)
−
30
−
ms
Undervoltage Protection Threshold
VUVP
285
300
315
mV
Undervoltage Protection Hysteresis
VUVP(HYS)
20
40
60
mV
Undervoltage Protection Filter Delay
tdelay(UVP)
−
30
−
ms
IUVP
0.7
1.0
1.3
mA
VOVP/VREF
99.5
100.0
100.5
%
Vdisable
1.809
1.865
1.921
V
PFC FAULT PROTECTION
UVP Pull Down Current Source
Ratio Between VOVP and VREF (Note 3)
INVERTER ENABLE/REFERENCE
Disable Threshold
Disable Filter Delay
Voltage Reference
IIENABLE(SRC) = 8 mA
IIENABLE(SRC) = 1 mA
IIENABLE(SNK) = 250 mA
Reference Pin Decoupling Capacitor
tdelay(disable)
−
30
−
ms
VIENABLE(high)
VIENABLE(high)
VIENABLE(low)
4.5
4.7
−
5.0
5.0
60
5.4
5.4
120
V
V
mV
CREF
0
−
1
mF
THERMAL PROTECTION
Thermal Shutdown
Thermal Shutdown Delay
TTSHDN
−
150
−
°C
tdelay(TSHDN)
−
30
−
ms
SHUTDOWN PIN
Shutdown Threshold
VShutdown Increasing
VSHDN
0.90
1.00
1.10
V
Shutdown Filter Delay
VShutdown Increasing
tdelay(SHDN)
−
30
−
ms
IShutdown
2.3
3.3
4.3
mA
Pull Up Current Source
3. Guaranteed by design
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NCP1927
DETAILED OPERATING DESCRIPTION
INTRODUCTION
When VCC reaches VCC(reset) (typically 6.5 V), a Power
On Reset occurs. This resets all logic states on the device. As
VCC continues to rise, the IC bias current remains at ICC5
until VCC reaches VCC(on) (typically 17 V). Once VCC
reaches VCC(on), the flyback controller is enabled and the IC
bias current increases to ICC3 (1.5 mA typical). However,
the total ICC current is greater than this due to the gate charge
load at the flyback drive output (FDRV). Once the flyback
is in regulation, the PFC controller can be enabled. When the
PFC is enabled, the ICC current increases further due to the
gate charge load at the PFC drive output (PDRV). The
increase in ICC per MOSFET is calculated using Equation 2.
The NCP1927 is a combination power factor correction
(PFC) and flyback controller optimized for use in Flat Panel
TVs. This device includes all the features needed to
implement a highly efficient and compact power supply. It
integrates a critical conduction mode (CrM) PFC controller
and a fixed−frequency current mode flyback controller with
proper sequencing for simplified system design.
This device includes frequency jittering, a shutdown
input, an inverter enable output, a go to standby input, and
a dedicated pin for under/overvoltage protection.
SUPPLY SEQUENCING
I CC(x) + f OSC @ Q G(x)
The flyback controller of the NCP1927 is enabled once
VCC reaches VCC(on), provided it is not in thermal shutdown
and has not been latched off or shutdown. Once the flyback
controller is enabled, a soft−start timer is activated, and it
begins switching. The soft−start timer provides a ramp
signal that increases over tSSTART (typically 4.0 ms). This
ensures that the peak current gradually increases to
minimize power component stress and limit output voltage
overshoot. Frequency jittering is disabled while the
soft−start timer is running.
Once the flyback controller detects regulation on the
output (it is no longer in overload), the PFC controller can
be enabled. As soon as the PFC controller is enabled, the
error amplifier begins to source its maximum output current,
IEA(MAX), (typically 20 mA) to linearly charge the PControl
pin capacitor (CPControl). Soft−start is achieved as CPControl
charges. An internal grounding switch on the PControl pin
is turned on each time the PFC controller is disabled, and
turned off when it is enabled. This ensures that CPControl is
always fully discharged at the beginning of soft−start.
As the PFC stage approaches regulation on the output, the
error amplifier output current, IEA, gradually reduces to
0 mA. Once the output is in regulation and IEA reaches 0 mA,
the IENABLE pin is set to VIENABLE(high) (typically 5 V).
where, fOSC is the switching frequency and QG(X) is the gate
charge of the external MOSFET X.
CVCC must be sized such that a VCC voltage greater than
VCC(off) (9 V typical) is maintained while the auxiliary
supply voltage increases during startup. If CVCC is too small,
VCC falls below VCC(off) and the controller turns off before
the auxiliary winding powers up the controller. The total ICC
current after the flyback controller is enabled (ICC3 plus
ICC(FDRV)) must be considered to correctly size CVCC. It is
often useful to connect a small VCC capacitor (C1) directly
to the VCC pin, while a larger capacitor (C2) is connected to
the VCC pin through a diode and charged by the aux winding.
This allows minimum startup time while providing enough
VCC capacitance to operate during light load conditions.
This implementation is shown in Figure 3 and the startup
sequence is shown in Figure 4.
VCC MANAGEMENT
When power is initially applied to the application, the VCC
capacitor (CVCC) begins charging through a resistor
connected to the high voltage line (Vin). The resistor value
must be chosen so that the charging current is greater than
the IC bias current during startup. The maximum value for
the startup resistor is calculated using Equation 1.
R start +
V in
I CC5
(eq. 2)
(eq. 1)
where Vin is the rectified dc input voltage and ICC5 is the IC
bias current during startup (20 mA maximum).
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NCP1927
Vin
VCC
Fault
Occurs
Device
Restarts
VCCON
Rstart
VCCOFF
+
D1
C1
+
D2
C2
Aux Winding
Fault is Reset
time
ICC
DRV
VCC
time
ICC
ICC2
ICC4
NCP1927
ICC5
Figure 5. VCC During a VCC Hiccup
Figure 3. Operation with Dual VCC Capacitors
SHUTDOWN PIN
The Shutdown pin allows for external disabling of the
NCP1927. When VShutdown is pulled above the shutdown
threshold, VSHDN (typically 1.0 V), both the flyback and
PFC drive outputs are immediately turned off, and a VCC
hiccup occurs (see Figure 5). When VCC reaches VCC(on),
the cycle repeats unless the NCP1927 is taken out of
shutdown. This is achieved when VShutdown becomes less
than VSHDN. The NCP1927 leaves shutdown mode and will
start when VCC reaches VCC(on) according to the initial
power−on sequence. The VCC behavior during shutdown
mode is shown in Figure 6.
VCC
VCC(on)
VCC(off)
VCC(reset)
0V
Time
DRV
PDRV
PDRV
FDRV
FDRV
ICC
ICC1+ICC(FDRV)+ICC(PDRV)
Time
ICC3+ICC(FDRV)
ICC5
time
Time
Figure 4. Startup Sequence of the NCP1927
FAULT MANAGEMENT
When the NCP1927 detects a non−latching fault
(Shutdown Mode, TSD, and Flyback Overload), the drivers
are disabled, and VCC falls towards VCC(off) due to the IC
internal current consumption. Once VCC falls below
VCC(off), the fault is reset and the IC internal current
consumption is reduced to the startup current, ICC5. VCC
begins to rise as if power was initially applied and the device
resumes normal operation once VCC reaches VCC(on). This
cycle between VCC(on) and VCC(off) is commonly referred to
as a VCC hiccup and is shown in Figure 5.
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NCP1927
(125 Hz typical). The frequency jittering is fully disabled
during soft−start and frequency foldback. Figure 7 depicts
the jittering operation.
fOSC
fOSC + fMOD
Nominal fOSC
fOSC - fMOD
Time
8 ms
(125 Hz)
Figure 7. Frequency Jittering
Current Sensing
NCP1927 is a current−mode controller, which means that
the feedback voltage sets the peak current flowing in the
transformer and the MOSFET. This is done through the
PWM comparator. The switch current is sensed across a
resistor and the resulting voltage is applied to the FCS pin.
It is then applied to one input of the PWM comparator
through a 250 ns leading edge blanking (LEB) block. On the
other input, the feedback voltage divided by KFFB (typically
5) sets the current limit threshold. When the current reaches
this threshold, the output driver is turned off. A dedicated
comparator monitors the current sense voltage, and if it
reaches the maximum value, VILIM (typically 0.7 V), the
output driver is turned off immediately. This occurs even if
the limit imposed by the feedback voltage is higher than
VILIM. Figure 8 shows the schematic of the current sense
circuit.
Figure 6. VCC Behavior During Shutdown Mode
THERMAL SHUTDOWN
When the junction temperature exceeds TTSHDN (140°C
minimum), a temperature sensing circuit disables the gate
drives and a VCC hiccup occurs (see Figure 5). When VCC
reaches VCC(on), the cycle repeats unless the junction
temperature drops below TTSHDN.
CLAMPED DRIVERS
The NCP1927 includes two powerful MOSFET drivers
capable of sourcing 800 mA and sinking 1200 mA each.
Since VCC is rated at 30 V (maximum), each driver output
is internally clamped to 16 V (maximum) to allow the use of
20 V MOSFETs.
VFFB(open)
RFFB
FLYBACK CONTROLLER
FFB
The NCP1927 flyback stage implements a standard
current mode architecture where the switch−off event is
dictated by the peak current setpoint.
÷
KFFB
VCC
Oscillator with Maximum Duty Ratio and Frequency
Jittering
FDRV
FCS
Q
The NCP1927 flyback controller includes an oscillator
that sets the switching frequency with an accuracy of
$7.7%. The maximum duty ratio of the FDRV pin is 80%
(typical).
In order to improve the EMI signature, the switching
frequency jitters at fMOD ($6% typical) around its nominal
value, with a triangle−wave shape and at a frequency of fjitter
tLEB
R
S
f(OSC)
VILIM
Figure 8. Current Sense Block Schematic
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NCP1927
Short−Winding Protection
soft−start is applied when VCC reaches VCC(on). The current
limit threshold is linearly increased from 0 until it reaches
VILIM (in 4.0 ms), or until the feedback loop imposes a
setpoint lower than the one imposed by the soft−start (the 2
comparator outputs are OR’ed together). Figure 10 shows a
typical startup sequence.
Under some conditions, like a transformer winding or
output diode short−circuit, the primary current increases
above VILIM before the LEB timer expires. To prevent
dangerously high current from flowing, an additional
comparator senses when VFCS reaches VCS(stop). Once this
comparator toggles, the controller immediately latches off.
The effect of latching off the IC is identical to shutdown
mode, however, the VCC cycle repeats indefinitely until the
input power is removed and CVCC is allowed to discharge
below VCC(reset). When input power is reapplied, the
NCP1927 operates according to the initial power−on
sequence. The VCC behavior during short winding
protection is shown in Figure 9.
FCS Pin
VFB
Soft−start ramp
Time
VFB takes
over soft−start
VILIM
Short
Winding
Detected
VCS(stop)
tSSTART
CS Setpoint
time
Time
VCC
VILIM
VCC(on)
VCC(off)
Time
time
Figure 10. Soft−Start Timing
DRV
Ramp Compensation
time
Ramp compensation is a known method for preventing
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) when the duty ratio is
greater than 50%. To prevent these oscillations, one
typically lowers the current loop gain by injecting between
50% and 75% of the inductor downslope. This is done by
inserting a resistor (RSCOMP) between the FCS pin and the
current sense resistor. Figure 11 shows an example of this.
The ramp signal is disconnected from the FCS pin during the
off time.
ICC
ICC2
ICC4
ICC6
time
Figure 9. VCC Behavior During Short Winding
Protection
Feedback
The ratio from the feedback voltage to the current limit
threshold, KFFB (typically 5), determines the peak current
limit threshold. This means that the feedback voltage when
the current limit threshold equals VILIM is 3.5 V (typical).
The FFB pin is connected to the internal VDD rail through
a resistor divider. To ease system design, the FFB pin is
represented by a Thevenin equivalent circuit containing a
voltage source and series resistor, VFFB(open) (typically 5 V)
and RFFB (typically 20 kW).
Iramp(MAX)
0 mA
ON
FDRV
Reset
Iramp
+
−
RSCOMP
L.E.B.
FCS
from FFB Setpoint
Soft−Start
The NCP1927 flyback controller features an internal
soft−start circuit. Every time the controller starts (i.e. the
controller was off and starts, or restarts due to a fault), a
Rsense
Figure 11. Inserting a Resistor
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NCP1927
When calculating the proper value for RSCOMP, it is
necessary to express the internal ramp signal in terms of its
slope (dIOSC/dt). This is done using Equation 3.
dl OSC
dt
+
I ramp(MAX) @ f OSC
Output Load
dt
+ R sense @
ǒV out ) V DǓ @
N
S
N
P
Fault
timer
starts
R SCOMP +
dI
Restart
At VCC(on)
V CC(off)
Fault is
reset
(eq. 4)
time
DRV
Controller
stops
where VD is the forward drop of the output rectifier, NS/NP
is the turns ratio, and LP is the primary inductance.
Using the results from Equations 3 and 4, RSCOMP can be
calculated using Equation 5.
dV
time
V CC
V CC(on)
LP
a@
time
Fault Flag
The inductor downslope (dVP(off)/dt) projected across the
current sense resistor (Rsense) is then calculated using
Equation 4.
dV P(off)
time
Fault Timer
80 ms
P(off)
dt
Fault
disappears
Max Load
(eq. 3)
D MAX
Overcurrent
applied
time
t FOVLD
(eq. 5)
Figure 12. Operation During Overload
OSC
dt
where a is the percentage of dVP(off)/dt to be injected.
Frequency Foldback
In order to improve the efficiency at light load conditions,
the frequency of the internal oscillator is linearly reduced
from its nominal value down to fOSC(MIN) (typically
26 kHz). The frequency foldback starts when the voltage on
the FFB pin goes below Vfold, and is completed before VFFB
reaches VFSKIP. The current−mode control remains active
while the oscillator frequency decreases. This is shown in
Figure 13.
Overload Protection with Fault Timer
When an overload occurs on the output of the power
supply, the feedback loop asks for more power than the
controller can deliver, and the current limit threshold
reaches VILIM. When this event occurs, a fault timer
(tFOVLD) is enabled.
When the timer expires, FDRV pulses are stopped, the
PFC is disabled, and a VCC hiccup occurs. When VCC
reaches VCC(on), the controller starts according to the initial
power−on sequence. If the overload is still present, the fault
timer continues to run and the cycle repeats when it expires.
The fault timer is reset if the current limit threshold goes
back below VILIM. A short delay, tdelay(FOVLD), is added to
prevent the fault timer from resetting due to noise. This
autorecovery operation is depicted in Figure 12.
Oscillator Frequency
fOSC
Skip
fOSC(MIN)
FFB
VFSKIP
Vfold
Figure 13. Switching Frequency as VFFB Decreases
Skip Cycle Mode with Soft−Skip
When the feedback voltage reaches VFSKIP while
decreasing, skip mode is activated and the driver stops
switching. While the driver is disabled, VFFB begins to rise.
As soon as VFFB rises above VFSKIP + VFSKIP(HYS), the
driver starts to switch again, but the duty ratio is gradually
increased from nearly 0% over a short Soft−Skip duration
(tSSKIP). This is accomplished by comparing the current
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NCP1927
mode instead of current mode. Once the CS signal reaches
the feedback voltage, the controller resumes normal
operation in current mode. The skip mode block diagram is
shown in Figure 14. The ramp timing and overall timing
diagrams are shown in Figures 15 and 16.
sense signal to an internal ramp generated by the Soft−Skip
timer instead of the feedback voltage. Since the LEB of the
FCS Pin prevents operation at nearly 0% duty ratio, the
controller instead compares the soft−skip ramp to an internal
sawtooth signal generated by the oscillator (not subjected to
LEB). This causes the controller to operate briefly in voltage
Soft−skip ramp
Sawtooth
tSSKIP
Reset
Oscillator
DMAX
VFSKIP
S
Q
R
KFFB
FFB
+
−
−
+
tLEB
FCS
FDRV stage
Figure 14. Skip Cycle with Soft−Skip Architecture
During the Soft−Skip duration if the feedback voltage
goes above Vfold, the Soft−Skip ends instantaneously
allowing the controller to operate in current mode.
This transient load detection feature avoids large output
drops if a load transient occurs while the controller is in skip
mode.
VFFB
Vfold
VFSKIP(HYS)
VFSKIP
Time
Enters
Soft−Skip
FDRV
Exits
Soft−Skip
Time
CS Setpoint
Soft−Skip
Soft−Skip
Time
Figure 15. Skip Cycle with Soft−Skip Timing Diagram
Figure 16. Soft−Skip Timing Diagram
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NCP1927
PFC CONTROLLER
ideal choice for medium power PFC boost stages because it
combines the lower peak currents of CCM operation with
the zero current switching of DCM operation. The operation
and waveforms in a PFC boost converter are illustrated in
Figure 17.
The PFC stage operates in critical conduction mode
(CrM). CrM occurs at the boundary between discontinuous
conduction mode (DCM) and continuous conduction mode
(CCM). In CrM, the driver on time is initiated when the
boost inductor current reaches zero. CrM operation is an
Diode Bridge
Diode Bridge
+
Vin
+
IL
L
IL
Vin
+
Vdrain
L
+
−
+
Vout
−
The power switch is ON
The power switch is OFF
The power switch being about zero, the input voltage
is applied across the coil. The coil current linearly
increases with a (Vin/L) slope.
The coil current flows through the diode. The coil voltage is (Vout −
Vin) and the coil current linearly decays with a (Vout − Vin)/L slope.
Coil
Current
Vin/L
(Vout − Vin)/L
IL(peak)
Critical Conduction Mode:
Next current cycle starts as
soon as the core is reset.
time
Vdrain
Vout
Vin
If next cycle does not
start then Vdrain rings
towards Vin
time
Figure 17. Schematic and Waveforms of an Ideal CrM Boost Converter
constant on time CrM control in a cost−effective and robust
manner.
When the switch is closed, the inductor current increases
linearly to its peak value. When the switch opens, the
inductor current linearly decreases to zero. At this point, the
drain voltage of the switch (Vdrain) begins to drop. If the next
switching cycle does not start, the voltage rings with a
dampened frequency around Vin. A simple derivation of
equations (such as those found in AND8123) leads to the
result that good power factor correction in CrM operation is
achieved when the on time is constant across a single ac
cycle. Equation 6 shows the relationship between on time
and system operating conditions.
t on +
2 @ P out @ L
h @ Vac 2
Vin(peak)
IL(peak)
Vin(t)
IL(t)
Iin(peak)
Iin(t)
time
(eq. 6)
where Pout is the output power, L is the boost inductor
inductance and h is the system efficiency.
A plot of the MOSFET on/off time over an ac line cycle
is illustrated in Figure 18. The MOSFET off time varies
based on the instantaneous line voltage, but the on time is
constant. This causes the peak inductor current (IL(peak)) to
follow the ac line voltage. The NCP1927 implements
MOSFET
ON
OFF
time
Figure 18. Inductor Waveform During CrM Operation
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NCP1927
Output Regulation
where Idivider is the resistor divider current.
Using RPFB1, RPFB2 is calculated with Equation 9.
The NCP1927 error amplifier (EA) consists of an
operational transconductance amplifier (OTA) with the
inverting input connected to the PFB pin and the output
connected to the PControl pin to regulate the output voltage.
It features a typical transconductance (gm) of 200 mS and a
maximum output (IEA(SRC) and IEA(SNK)) of $20 mA
(typical). The non−inverting input is connected internally to
a voltage reference (VREF) with a typical value of 2.5 V
$1.5% over process and temperature. During normal
operation, the voltage on the PControl pin varies between
VPControl(MIN) (typically 0.6 V) and VPControl(MAX)
(typically 5.6 V). A simplified diagram of the OTA circuit
is shown in Figure 19.
R PFB2 +
R PFB1 @ V REF
V out * V REF
(eq. 9)
Compensation
A compensation network must be connected between the
PControl pin and ground due to the nature of an active PFC
circuit. The PFC stage generates a sinusoidal current from
the ac line voltage and provides the load with a power that
matches the average demand. When the input voltage is at
its peak, the PFC stage delivers more power than the load
requires, and the output capacitor charges. Conversely,
when the input voltage is at a valley, the load requires more
power than the PFC stage can deliver, and the output
capacitor discharges. The situation is depicted in Figure 20.
Vin(t)
Iin(t)
time
CPControl
Pin(t)
Pout(t)
Figure 19. Error Amplifier and On Time Regulation
Circuits
time
A resistor divider from the boost output to the PFB pin
provides a scaled−down representation of the output voltage
(Vout) to the EA. When Vout is in regulation, VPFB equals
VREF. If Vout drops below regulation, the feedback voltage
(VPFB) drops and the EA sources current until VPFB returns
towards VREF. This increases the control voltage (VPControl)
and the on time of the driver (ton), which in turn increases the
power delivered to the load and brings Vout back into
regulation. Alternatively, if Vout (and also VPFB) is too high,
the EA sinks current and VPControl decreases, thus
shortening ton until Vout returns to regulation. The output
voltage is calculated using Equation 7.
V out + V REF @
R PFB1 ) R PFB2
R PFB2
Vout(t)
time
Figure 20. Output Voltage Ripple for a Constant
Output Power
This creates a ripple on the output with frequency equal to
twice the line frequency (fline). Since the on time must
remain constant during each ac line cycle to maintain good
power factor correction, the EA must reject the output
ripple. This is commonly achieved by setting the regulation
bandwidth below 20 Hz. A type 1 compensation network is
typically used for simplicity, as it only requires a single
capacitor (CPControl) connected between the PControl pin
and ground (see Figure 19). For a type 1 network, CPControl
is calculated using Equation 10.
(eq. 7)
where RPFB1 is the upper resistor of the resistor divider, and
RPFB2 is the lower resistor.
The impedance of the feedback network determines its
noise immunity and power dissipation. While a lower
impedance provides better noise immunity, it also increases
power dissipation. Once the divider current is chosen, RPFB1
is determined using Equation 8.
R PFB1 +
V out
I divider
C PControl +
gm
2p @ f c
(eq. 10)
where gm is the transconductance of the EA (typically
200 mS), and fc is the desired crossover frequency (typically
less than 20 Hz).
(eq. 8)
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NCP1927
Transient Load Detection
bulk capacitor voltage ripple, the on time remains constant
over the entire ac line cycle.
The maximum on time of the controller occurs when
VPControl is at its maximum value. Therefore, Ct must be
sized to ensure that the required on time can be achieved at
maximum output power and minimum input voltage. The
maximum on time is calculated using Equation 11.
Due to the low bandwidth of the regulation loop, fast load
transients may result in output voltage over and undershoots.
Overshoots are limited by the overvoltage protection (see
OVP section). To control the undershoots, an internal
comparator monitors the ratio between VPFB and VREF.
When it is lower than VOLOW/VREF (95.5% typical),
IPControl(boost) (240 mA typical) is connected to the PControl
pin to speed up the charging of CPControl. This has the effect
of increasing the EA gain by a factor of approximately 13.
The transient load detection circuit is disabled during the
startup sequence of the PFC stage to prevent it from
interfering with the operation of the soft−start circuit.
t on(MAX) +
C t @ V PCT(MAX)
I PCT(charge)
(eq. 11)
where VPCT(MAX) = 5 V (typical) and IPCT(charge) = 210 mA
(typical).
Combining Equation 11 with Equation 6, results in
Equation 12.
On Time Control
Since the NCP1927 is designed to control a CrM boost
converter, the switching pattern consists of constant on
times and variable off times. The on time is set via an
external capacitor (Ct) connected to the PCT pin. At the
beginning of each switching cycle, Ct is charged linearly by
IPCT(charge) (210 mA typical). An internal comparator
monitors the voltage on the PCT pin (VPCT) and compares
it to an internal regulation limit set by VPControl. The internal
limit is determined by shifting VPControl down by a voltage
equal to one diode drop (0.6 V typical) to account for the
offset of the control voltage range. Once this level is
exceeded, the drive is turned off. Ct is then discharged within
tCPCT(discharge) (maximum 500 ns) and held low until the
beginning of the next switching cycle. This sequence is
shown in Figure 21.
Ct +
2 @ P out @ L @ I PCT(charge)
h @ Vac LL 2 @ V PCT(MAX)
(eq. 12)
Where, VacLL is the minimum ac rms input voltage.
Off Time Control
The off time varies with the instantaneous line voltage and
is adjusted every cycle so that the inductor is demagnetized
before the next switching cycle begins. The inductor is
demagnetized once its current reaches zero. When this
happens, the drain voltage begins to drop. This is detected
by sensing the voltage across an inductor auxiliary winding.
This winding, commonly known as a zero crossing detection
(ZCD) winding, provides the NCP1927 with a scaled
version of the inductor voltage. Figure 22 shows a typical
ZCD winding arrangement.
VPControl
PControl
VDD
PCT
Ct
PWM
−
+
IPCT(charge)
ton
PDRV
Figure 22. ZCD Winding Implementation
VPCT
While the switch is on, a negative voltage appears at the
PZCD pin. When the switch turns off, the ZCD voltage
swings positive, arming the ZCD detector. The ZCD voltage
remains positive until the inductor current falls to zero and
the inductor is demagnetized. The voltage then drops to 0 V
and triggers the ZCD detector to begin the next switch cycle.
The arming threshold of the ZCD detector is typically 1.4 V
(VZCD(rising)) and the triggering threshold is typically 0.7 V
(VZCD(falling)).
The PZCD pin is internally clamped to VCL(POS)
(typically 10 V) and VCL(NEG) (typically −0.7 V). A resistor
in series with the PZCD pin is required to limit the current
into the pin and prevent it from exceeding 3 mA at VCL(POS)
or −2 mA at VCL(NEG). Figure 23 shows typical ZCD
waveforms.
VPControl − 0.6 V
ton
PDRV
Figure 21. On Time Generation
Since VPControl varies with the RMS line voltage and
output load, this naturally satisfies Equation 6. If the values
of compensation components are sufficient to filter out the
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NCP1927
protection keeps the output voltage within an acceptable
range.
While traditional PFC controllers often use one single pin
for both under/overvoltage protections and feedback, the
NCP1927 uses a dedicated pin for undervoltage protection
(UVP) and OVP. This configuration allows the
implementation of two separate feedback networks as
shown in Figure 24.
VPDRV
time
Vdrain
Vout
Vout
time
VPZCD
VCL(POS)
VZCD(rising)
VZCD(falling)
R POVUV1
R PFB1
PFB
time
VCL(NEG)
POVUV
ZCD Winding
R POVUV2
VZCD(off)
R PFB2
time
VZCD(on)
Figure 23. Voltage Waveforms for Zero Current
Detection
Figure 24. Configuration with Two Separate
Feedback Networks
During startup, there are no ZCD transitions to enable the
PFC switch. A watchdog timer, tstart, enables the PFC driver
when no switch pulses are detected before it times out
(180 ms typical). The watchdog timer is also useful while
operating at light load because the amplitude of the ZCD
signal may be too small to cross the ZCD thresholds.
The double feedback configuration provides an increased
level of safety, as it protects the PFC stage even if there is a
failure of one of the two feedback arrangements.
A 1 mA (typical) current source, IUVP, pulls the POVUV
pin voltage below the UVP threshold if the pin is left floating
to ensure the PFC stage will be protected.
A comparator connected to the POVUV pin provides the
OVP protection. The output voltage that activates the OVP
fault detection is calculated using Equation 13.
Frequency Clamp
Since the NCP1927 operates in CrM mode over the ac line
half cycle, the switching frequency naturally increases as the
line voltage approaches zero. In order to minimize the PFC
inductor size, the NCP1927 features an internal oscillator
that clamps the maximum switching frequency to fclamp
(typically 385 kHz).
V out(OVP) + V OVP @
R POVUV1 ) R POVUV2
R POVUV2
) I UVP @ R POVUV1
(eq. 13)
where Vout(OVP) is the peak value of the output voltage
including ripple and VOVP is the OVP threshold (2.5 V
typical).
When the OVP comparator is activated, the PFC driver is
immediately turned off. Once the feedback voltage drops
below the hysteresis of VOVP (VOVP(HYS)), the PFC driver
is re−enabled. This helps to limit overshoots on the output
during startup and transient loads. Figure 25 depicts the
operation of the OVP circuitry, while Figure 26 shows the
internal block diagram.
Overvoltage/Undervoltage Protection
The low bandwidth of the PFC stage feedback network
causes it to have a slow transient response. This increases the
risk of overshoots during transient conditions (startup, load
steps, etc.). For safe operation, overvoltage protection
(OVP) is utilized to prevent the output voltage from rising
too high and overstressing the power stage components. The
NCP1927 detects high Vout levels and disables the driver
until the output voltage returns to nominal levels. This
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NCP1927
Vout
power path to the bulk capacitor (i.e. the capacitor is unable
to charge up) or if the controller is unable to sense the output
voltage (i.e. the POVUV Pin is floating). The output voltage
that causes a UVP fault is calculated using Equation 14.
Vout(nom)
time
V out(UVP) + V UVP @
PDRV
R POVUV1 ) R POVUV2
R POVUV2
) I UVP @ R POVUV1
(eq. 14)
Overcurrent Protection (OCP)
The NCP1927 contains an OCP circuit to protect the PFC
stage by limiting the coil current. A current sense resistor
(Rsense) is inserted in the return path to generate a negative
voltage proportional to the coil current (VRsense) as
portrayed by Figure 27. The circuit uses VRsense to detect
when the coil current exceeds its maximum permissible
level. To do so, the circuit incorporates an operational
amplifier that sources the current necessary to maintain the
PCS pin at zero volts. A resistor (RPCS) inserted between the
PCS pin and Rsense allows the current sourced by the PCS
pin (IPCS) to be adjusted via Equation 15.
time
OVP
time
Figure 25. OVP Timing Diagram
Vout
OVP
VOVP
−ǒR sense @ I LǓ ) ǒR PCS @ I PCSǓ + 0
R POVUV1
POVUV
where IL is the current flowing through the boost inductor.
Rearranging Equation 15 allows IPCS to be calculated
using Equation 16.
UVP
I PCS +
VUVP
IUVP
R POVUV2
R sense
R PCS
The NCP1927 detects a UVP fault when the output
voltage falls below the UVP limit. During a UVP fault, the
drive output and error amplifier (EA) are disabled, and
CPControl is discharged. It is important to note that the PFC
stage does not start if VPOVUV is lower than VUVP. This
protects the application when there is a problem with the
I L(MAX) +
R PCS
R sense
@ I OCP
where IOCP is the OCP threshold current.
VDD
IPCS
IPCS > IOCP
PCS
−
+
IPCS
Rsense
IL
@ IL
(eq. 16)
If IPCS exceeds IOCP (typically 250 mA), an OCP
condition is detected and the driver is turned off. The driver
remains off until IPCS falls below IOCP, and the next ZCD
transition occurs or the watchdog timer expires. The
maximum coil current (IL(MAX)) is calculated with
Equation 17.
Figure 26. POVUV Pin Block
RPCS
(eq. 15)
Figure 27. Current Sense Block
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20
To PDRV disable
(eq. 17)
NCP1927
Skip Mode Operation
P skip(lower) +
The NCP1927 automatically skips switching cycles when
the power demand drops below a given level. This is
accomplished by monitoring the internal offset PControl
voltage. This voltage is compared to the PCT ramp to control
the power level in a particular design. During normal
operation, the circuit generates the input line current
necessary for matching the load power demand. If the need
for power decreases, the regulation loop lowers the
regulation voltage to reduce the power delivery accordingly.
When the regulation voltage goes below a programmable
pre−set level, the PFC stage stops switching. This causes the
output voltage to decrease, and the regulation voltage to
increase. When the regulation voltage exceeds the skip
threshold, switching resumes.
This operation allows the PFC stage to deliver 10% power
for 10% of the time, as opposed to 1% power for 100% of the
time. This skip cycle mode, also called controlled burst
operation, is much more efficient than a continuous power
flow since it drastically reduces the number of switching
pulses and their associated switching losses. To ensure
stability, hysteresis is added.
The PSKIP pin provides the possibility to adjust these
levels by connecting it through a single resistor to ground.
Since the skip threshold power levels can vary with line
voltage, they are calculated using Equations 18 and 19.
V PSKIP
5V@
P skip(upper) +
ǒ Ǔ
Vac
LL
2
@ P out(MAX)
Vac
V PSKIP
4.5 V @
(eq. 18)
ǒ Ǔ
Vac
LL
2
@ P out(MAX)
(eq. 19)
Vac
where VPSKIP is the voltage applied to the PSKIP pin, VacLL
is the minimum ac line voltage, Vac is the operating line
voltage, and Pout(MAX) is the maximum output power.
The skip pin voltage is adjusted through a resistor to
ground using Equation 20.
V PSKIP + I PSKIP @ R PSKIP
(eq. 20)
where IPSKIP is the value of the internal current source
(30 mA typical) and RPSKIP is the external resistor connected
to ground.
If desired, skip mode can be easily disabled by connecting
the PSKIP pin directly to ground. If the PSKIP pin is left
floating, VPSKIP will rise towards the internal voltage rail
and disable the drive. Since the PControl Pin is low during
startup, the PFC skip mode is disabled until the PFC output
reaches regulation and the IENABLE Pin is high. A
simplified schematic of the PSKIP pin is shown in
Figure 28.
OTA Output
PControl
To PWM Comparator
R
PFAULT
9*R
IPSKIP
VDD
PSKIP
RPSKIP
SKIP
PFC_OK
Figure 28. Schematic for PSKIP Pin
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21
NCP1927
Go To Standby Pin
The Go To Standby (GTS) pin is used to disable the PFC
stage during system standby based on the flyback stage load
condition. This can be done by connecting it to the flyback
stage feedback pin (FFB) through a resistor divider or by
directly driving the pin with an optocoupler. These
implementations are shown in Figures 29 and 30.
The GTS pin contains an internal pull down resistor, RGTS
(typically 200 kW), for use with an optocoupler and to
ensure the PFC is disabled if the pin is floating.
GTS
Rlimit
VCC_AUX
GTS
CGTS
from secondary side
Figure 30. GTS Implementation with Optocoupler
IENABLE Pin
The IENABLE pin is designed to drive an optocoupler
that enables the Flat Panel TV backlight inverter once the
PFC stage reaches regulation. The NCP1927 achieves this
by monitoring the current sourced by the EA. Once this
current drops to 0 mA, the IENABLE pin voltage switches
to VIENABLE(high) (typically 5.0 V). This operation is shown
in Figure 31.
FFB
RGTS1
Vout
CGTS
Vout(MAX)
Vout(NOM)
Vout(MIN)
RGTS2
Undershoot from Inverter
Load
time
IEA(out)
Figure 29. GTS Implementation with Feedback Pin
0 μA
The resistor divider from the FFB pin is used to setup the
GTS power level threshold. When VGTS is brought below
the GTS threshold, Vstandby, the PFC controller stops
switching and enter standby mode. It remains in standby
until VGTS is brought above the hysteresis of Vstandby
(Vstandby(HYS)). A timer is included on the GTS pin to ensure
transients on the flyback converter do not trigger GTS.
However, the PFC must come out of standby as soon as
possible if there is a request to turn on the TV. Therefore, the
timer is bypassed when coming out of standby. The FFB
voltage at which the PFC enters GTS is expressed using
Equation 21.
V FFB(GTS) + V GTS @
R GTS1 ) R equiv
R equiv
−20 μA
time
VIENABLE
5V
Inverter
Starts
0V
A separate comparator on the PFB pin is used to protect
the inverter from undervoltage conditions by detecting
when the PFB voltage falls below Vdisable. When this occurs,
the IENABLE pin voltage switches to VIENABLE(low). Using
the result from Equation 7, the output threshold that sets the
IENABLE pin low can be calculated with Equation 23.
(eq. 21)
where Requiv is the parallel resistor combination of RGTS and
RGTS2 and is calculated using Equation 22.
R equiv +
R GTS @ R GTS2
R GTS ) R GTS2
time
Figure 31. IENABLE Pin Timing
(eq. 22)
V out(disable) +
If direct control of the PFC standby mode is desired, the
GTS pin can instead be driven with an optocoupler from the
secondary side to force the PFC stage in and out of standby
mode. A resistor (Rlimit) is placed in series with the
optocoupler to limit the current into the GTS pin.
V out @ V disable
V REF
(eq. 23)
where Vdisable is the disable threshold (1.865 V typical).
The IENABLE pin can also be used as a voltage reference.
To filter noise, a decoupling capacitor (CREF) may be
connected to the pin.
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NCP1927
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
9
1
8
−B−
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
B
M
S
DIM
A
B
C
D
F
G
J
K
M
P
R
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1927/D