NCP1901 Advance Information Primary Side Combination Resonant and PFC Controllers The NCP1901 is a combination of PFC and half−bridge resonant controllers optimized for off−line adapter applications. This device includes all the features needed to implement a highly efficient and small form factor adapter. It integrates a critical conduction mode (CrM) power factor correction (PFC) controller and a half−bridge controller with a built−in 600 V driver. The half−bridge stage operates at a fixed frequency. Regulation is achieved by adjusting the PFC stage output voltage. This device includes an enable input on the PFC feedback pin, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCP1901 are a 600 V startup circuit and an adjustable frequency oscillator. The controllers are properly sequenced, simplifying system design. http://onsemi.com SO−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM 16 NCP1901G AWLYWW 1 Features • • • • • • • • • • • SOIC−16 D SUFFIX CASE 751B Adjustable Half−Bridge Frequency up to 75 kHz Open Feedback Loop Protection CrM Power Factor Correction Controller PFC Undervoltage Detector PFC Overvoltage Detector Half−Bridge Controller with 600 V High Side Gate Drive State Machine Ensures Proper Turn−on and Turn−off of Half−Bridge Stage Enable Input on the PFC Feedback Pin Disables Controllers and Reduces Power Controllers are Properly Sequenced for Fault Free Operation Internal 600 V Startup Circuit This is a Pb−Free Device 20 NCP1901 AWLYYWWG 1 NCP1901 = Specific Device Code A = Assembly Location WL = Wafer Lot Y or YY = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION Package Shipping† NCP1901DR2G SOIC−16 (Pb−Free) 2500/Tape & Reel NCP1901DWR2G SO−20 WB (Pb−Free) 1000/Tape & Reel Device Typical Applications • High Efficiency Notebook Adapter • Solid State Lighting †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Semiconductor Components Industries, LLC, 2009 February, 2009 − Rev. P0 1 Publication Order Number: NCP1901/D NCP1901 SO−20 WB SOIC−16 HV 20 HBoost OSC NC 2 19 HDRVhi GND NC 3 18 HVS HV 1 OSC 4 17 NC GND 5 16 NC PFB 7 14 PDRV PCS 8 13 PGND PZCD 9 12 VCC PControl 10 11 PCT HDRVhi HVS VREF 15 HDRVlo VREF 6 HBoost 1 HDRVlo PFB PDRV PCS PGND PZCD VCC PControl PCT Figure 1. Pin Connections VCC HV PDRV ZCD Comparator VDD + > 5.65 V Clamp < 2.25 V Clamp VDD IPCT(C) PCT + − VPREF On time Comparator + PFC UVP VPOVP − Comparator LEB + − + − PCS + − + VPUVP − PCS Comparator VPCS(ILIM) HVS HDRVlo Delay Q CLK Q Q Enable S UVLO R VDD Q Clock PDRV Q http://onsemi.com GND IOSC(C) CLK + − + 5V/ 3V − VDD Figure 2. Functional Block Diagram 2 Dboost VCC Delay VCCGood CCC HDRVhi Pulse Trigger PFC OVP Comparator VCC HBoost S Dominant Reset Q Latch R Level Shifter Level Shifter VCC(on)/ VCC(off)/ UVLO Undervoltage Detector − + IPFB + − PFB S Q Dominant Reset Latch Q R PFC Error Amplifier + − + − VCC Management VCC Good VZCD + − PControl − + PZCD Istart UVLO OSC 4*IOSC(C) Voltage Reference VREF Cboost NCP1901 Table 1. PIN FUNCTION DESCRIPTION 20 Pin 16 Pin Name Description 1 1 HV This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A constant current source supplies current from this pin to the VCC capacitor, eliminating the need for an external startup resistor. The charge current is 7.5 mA (typical). 4 2 OSC A capacitor on this pin adjusts the frequency of the internal oscillator. The oscillator sets the frequency of the half−bridge controller. The half−bridge operates at half the oscillator frequency. 5 3 GND Analog ground. 6 4 VREF Reference voltage. The capacitor on this pin decouples the internal reference. A 0.1 mF capacitor needs to be connected between this pin and ground. 7 5 PFB PFC voltage feedback input. The voltage on this pin is compared to a 2.5 V reference (typical) to regulate the PFC output voltage. The voltage on this pin is also used to detect PFC undervoltage and overvoltage conditions. 8 6 PCS PFC regulator current sense input. A voltage ramp proportional to the PFC switch current is applied to this pin. The current sense threshold, VPCS(ILIM), is typically 0.84 V. A 110 ns (typical) leading edge blanking circuit filters the current sense signal at the start of each cycle. 9 7 PZCD PFC inductor zero current detector. The inductor current is monitored using an auxiliary winding on the PFC inductor. The PFC drive signal is enabled during a high to low transition on the PZCD pin. A series resistor limits the current into the PZCD pin. 10 8 PControl PFC control voltage. This pin connects to the output of the PFC error amplifier. The error amplifier is a transconductance amplifier. A compensation network between this pin and grounds sets the PFC loop bandwidth. The PFC control voltage is compared to a level shifted version of VPCT to control the PFC duty ratio. 11 9 PCT PFC on time control capacitor. A 270 mA (typical) current source charges a capacitor connected between this pin and ground. Once the level shifted PCT voltage reaches VPControl, the PFC drive signal is disabled and the PCT capacitor is discharged. 12 10 VCC Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from HV to this pin. Once the VCC voltage reaches VCC(on) (15.3 V typical), the current source turns off and the controller is enabled. The current source turns on once VCC falls to VCC(off) (9.3 V typical). During normal operation, power is supplied to the IC via this pin by means of an auxiliary winding. 13 11 PGND Ground connection for PDRV and HDRVlo. Tie to the power stage return with a short trace. 14 12 PDRV PFC switch gate drive control signal. The source and sink drive capability is limited to 60 W and 15 W (typical), respectively. A discrete driver may be needed to drive the external MOSFET. 15 13 HDRVlo Half−bridge low side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. A discrete driver may be needed to drive the half bridge switch. 18 14 HVS Half−bridge high side driver source connection. This pin connects directly to the bridge terminal and can float up to 600 V. 19 15 HDRVhi Half−bridge high side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. The supply terminals of the high side driver connect to the HBoost and HVS pins. 20 16 HBoost Supply voltage of the high side gate driver. A charge pump generates a bootstrap voltage floating on top of the HVS voltage. A diode between the VCC and HBoost pins provides a charge path. The bootstrap voltage is VCC minus a diode drop. http://onsemi.com 3 NCP1901 Table 2. MAXIMUM RATINGS (Notes 1 and 2) Rating Symbol Value Unit High Voltage Input Voltage VHV −0.3 to 600 V High Voltage Input Current IHV 10 mA Supply Input Voltage VCC −0.3 to 20 V Supply Input Current ICC 10 mA Oscillator Input Voltage VOSC −0.3 to 10 V Oscillator Input Current IOSC 10 mA Bandgap Reference Decoupling Output Voltage VREF −0.3 to 9 V Bandgap Reference Decoupling Output Current IREF 10 mA PFC Feedback Voltage Input Voltage VPFB −0.3 to 10 V PFC Feedback Voltage Input Current IPFB 10 mA PFC Current Sense Input Voltage VPCS −0.3 to 10 V PFC Current Sense Input Current IPCS 10 mA PFC Zero Current Detection Input Voltage VPZCD −0.3 to 10 V PFC Zero Current Detection Input Current IPZCD 10 mA PFC Control Input Voltage VPControl −0.3 to 10 V PFC Control Input Current IPControl 1.2 mA PFC On Time Control Input Voltage VPCT −0.3 to 10 V PFC On Time Control Input Current IPCT 9 mA PFC Drive Signal Voltage VPDRV −0.3 to VCC V PFC Drive Signal Current IPDRV 100 mA Half−Bridge Low Side Driver Input Voltage VHDRVlo −0.3 to VCC V Half−Bridge Low Side Driver Input Current IHDRVlo 100 mA Half−Bridge High Side Driver Source Connection Input Voltage VHVS −1.0 to 600 V Half−Bridge High Side Driver Source Connection Input Current IHVS 100 mA Half−Bridge High Side Driver Input Voltage VHDRVhi −1.3 to 600 V Half−Bridge High Side Driver Input Current IHDRVhi 100 mA Half−Bridge High Side Driver Charge Pump Input Voltage VHBoost −0.3 to 600 V Half−Bridge High Side Driver Charge Pump Input Current IHBoost 100 mA High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) VHBoost(supply) −0.3 to VCC V High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) IHBoost(supply) 100 mA dVHVS/dt TBD V/ns Operating Junction Temperature TJ −40 to 150 °C Storage Temperature Range Tstg –60 to 150 °C Power Dissipation (TA = 25°C, 1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B−05 (SOIC−16) PD 0.95 W RθJA 130 °C/W Half−Bridge High Side Driver Source Connection Slew Rate Thermal Resistance, Junction to Ambient (1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B−05 (SOIC−16) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device(s) contains ESD protection and exceeds the following tests: Pins 1, 14, 15 and 16 rated to the maximum voltage of the part, or 600 V. All Other Pins: Human Body Model 1500 V per JEDEC Standard JESD22−A114E. All Other Pins: Machine Model 150 V per JEDEC Standard JESD22−A115−A. 2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78. http://onsemi.com 4 NCP1901 Table 3. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VCC Increasing VCC Decreasing VCC Decreasing VCC(on) VCC(enable) VCC(off) 14.3 13.6 8.5 15.3 14.6 9.3 16.3 15.6 10.0 VPFB = VPUVP(low) (Note 4) ICC1 ICC2 1.0 1.5 1.4 2.4 2.0 3.0 Startup Current VCC = VCC (on) – 0.2 V, VHV = 50 V Istart 3.0 7.5 10.5 mA Startup Circuit Off−State Leakage Current VHV = 600 V, VCC = VCC (on) + 0.2 V IHV(off) – 15 50 mA CREF = 0.1 mF VREF 6.605 7.000 7.295 V STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Enable Threshold Minimum Operating Voltage Supply Current Device Disabled/Fault Device Switching V mA BANDGAP REFERENCE Reference Voltage OSCILLATOR Half−Bridge Clock Frequency VHVS = 50 V fclock 13.5 15.5 16.5 kHz Maximum Half−Bridge Clock Frequency COSC = open fclock(MAX) 75 – – kHz 2.42 2.40 2.50 − 2.58 2.60 PFC ERROR AMPLIFIER PFC Feedback Voltage Reference VPREF 0°C < TJ < 125°C −40°C < TJ < 125°C PFC Feedback Voltage Reference Regulation with Line Error Amplifier Drive Capability Sink Source Open Loop Error Amplifier Transconductance V VCC(on) + 0.2 V < VCC < 20 V VPREF(line) −15 – 15 mV VPControl = 4 V, VPFB = 5 V VPControl = 4 V, VPFB = 0.5 V IEA(SNK) IEA(SRC) 60 −60 80 −80 – – VPControl = 4 V, VPFB = 2.4 V and 2.6 V Gm 60 95 – mS mA Feedback Input Pulldown Current Source VPFB = 3 V IPFB 0.5 1.2 1.5 mA Error Amplifier Maximum Output Voltage IPControl = 10 mA VEA(OH) 5.30 5.65 6.00 V Error Amplifier Minimum Output Voltage IPControl = −10 mA VEA(OL) 2.10 2.25 2.40 V Error Amplifier Output Voltage Range VEA(OH) − VEA(OL) ΔVEA 3.1 3.4 3.7 V 3. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins. http://onsemi.com 5 NCP1901 Table 4. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VPCS(ILIM) 0.78 0.84 0.92 V IPCS −1 0 1 mA tPCS(LEB) 40 110 200 ns VPCS = VPCS(ILIM) + 1 V tPCS(delay) – 90 250 ns VPZCD increasing VPZCD decreasing VZCD(high) VZCD(low) 1.9 1.3 2.1 1.5 2.3 1.7 V VZCD(HYS) 400 600 800 mV IPZCD(bias1) IPZCD(bias2) −1 −1 – – 1 1 mA tPFC(off) 50 180 350 ms PFC CURRENT SENSE Current Sense Threshold Voltage Current Sense Input Bias Current VPCS = 2 V Leading Edge Blanking Duration Propagation Delay PFC ZERO CURRENT DETECTION ZCD Threshold Voltage ZCD Voltage Hysteresis ZCD Input Bias Current VPZCD = 1 V VPZCD = 5 V PFC MAXIMUM OFF TIME Maximum Off Time PFC ON TIME RAMP GENERATOR ON time Capacitor Charge Current VPCT = 0 V IPCT(C) 220 270 300 mA On Time Capacitor Discharge Time CPCT= 1 nF, VPCT = 2.4 V to 0.6 V tPCT(D) – 70 300 ns VPCT(peak) 2.6 3.0 3.4 V VPFB = 3.0 V, VPZCD = 0 V DPMIN 0 – – % VPCT = VPCT(peak) + 1 V tPCT(delay) – 250 375 ns DVEA − VPCT(peak) VPCT(offset) 250 400 550 mV Midpoint between high and low threshold, VPControl = 4 V VPOVP 1.03* VPREF 1.05* VPREF 1.07* VPREF V Between increasing and decreasing thresholds, VPControl = 4 V VPOVP(HYS) 5 30 60 mV VPFB = VPREF + 1 V tPOVP(delay) – 400 800 ns Undervoltage Detector Threshold Voltage VPFB increasing VPFB decreasing VPUVP(high) VPUVP(low) − 175 290 230 350 − mV Undervoltage Comparator Hysteresis VPFB increasing VPUVP(HYS) 20 60 100 mV PFC Driver Rise Time 10% to 90% (Note 4) tPDRV(rise) − 18 − ns PFC Driver Fall Time 90% to 10% (Note 4) tPDRV(fall) − 9 − ns PFC Driver High State Voltage IPDRV = −8 mA VPDRV(OH) 14.00 14.55 − V PFC Driver Low State Voltage IPDRV = 8 mA VPDRV(OL) − 0.12 0.50 V ON Time Capacitor Peak Voltage Minimum Duty Ratio Maximum On Time Detect Delay Voltage Delta between PControl Voltage Needed to Generate PDRV Pulses and VEA(OL) PFC OVERVOLTAGE and UNDERVOLTAGE Overvoltage Detector Threshold Voltage Overvoltage Comparator Hysteresis Propagation Delay PFC DRIVER 4. Resistor/capacitor parallel combination (39 pF || 20 kW) between PDRV and driver supply and between PDRV and GND pins. http://onsemi.com 6 NCP1901 Table 5. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit Half−Bridge High Side Driver Rise Time 10% to 90% (Note 5) tHDRVhi(rise) – 18 – ns Half−Bridge High Side Driver Fall Time 90% to 10% (Note 5) tHDRVhi(fall) – 9 – ns High State Voltage IHDRVhi = −4 mA VHDRVhi(OH) 14.0 14.7 – V Low State Voltage IHDRVhi = 4 mA VHDRVhi(OL) – 0.06 0.5 V 10 to 90% to 10% transitions, VHSVS = 50 V (Note 5) DHDRVhiMAX 44 48 50 % VHBoost(UVLO) 4 6.1 8.0 V HDRVhi switching, between HDRVhi and HVS (Note 5) ICC(Boost) – 0.1 0.5 mA TJ = 25°C, VHVS = 600 V, VHBoost = 600 V IHVS(off) – 0.1 1 mA Half−Bridge Low Side Driver Rise Time 10% to 90% (Note 5) tHDRVlo(rise) – 18 – ns Half−Bridge Low Side Driver Fall Time 90% to 10% (Note 5) tHDRVhi(fall) – 9 – ns Half−Bridge Low Side Driver High State Voltage IHDRVlo = −4 mA VHDRVlo(OH) 14 14.7 – V Half−Bridge Low Side Driver Low State Voltage IHDRVlo = 4 mA VHDRVlo(OL) – 0.06 0.5 V Half−Bridge Low Side Driver Duty Ratio 10 to 90% to 10% transitions (Note 5) DHDRVloMAX 44 48 50 % Delay from HDRVlo high to low to HDRVhi low to high transition VHVS = 50 V tHDRVhi(h−l) 500 785 950 ns Delay from HDRVhi high to low to HDRVlo low to high transition VHVS = 50 V tHDRVhi(h−l) 500 785 950 ns HALF BRIDGE HIGH SIDE DRIVER High Side Driver Duty Ratio Boost Supply Undervoltage Threshold Boost Current Consumption HVS Leakage Current HALF BRIDGE LOW SIDE DRIVER CROSSOVER DEAD TIME 5. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins. http://onsemi.com 7 NCP1901 DETAILED OPERATING DESCRIPTION Introduction remains disabled until the lower supply threshold, VCC(off), (typically 9.3 V) is reached. Once reached, the drive outputs are disabled and the startup current source is enabled. Once the outputs are disabled, the bias current of the NCP1901 is reduced, allowing VCC to charge back up. The supply capacitor provides power to the controller while operating in the power up or self−bias mode. During the converter power up, CCC must be sized such that a VCC voltage greater than VCC(off) is maintained while the auxiliary supply voltage is building up. Otherwise, VCC will collapse and the controller will turn off. The IC bias current and gate charge load at the drive outputs must be considered to correctly size CCC. The increase in current consumption due to external gate charge is calculated using Equation 1. The NCP1901 is a combination of PFC and half−bridge resonant controllers optimized for off−line adapter applications. This device includes all the features needed to implement a highly efficient and small form factor adapter. It integrates a critical conduction mode (CrM) power factor correction (PFC) controller and half−bridge controller with a built−in 600 V driver. The half−bridge stage operates at a fixed frequency. Regulation is achieved by adjusting the PFC stage output voltage. This device includes an enable input, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCP1901 are a 600 V startup circuit and an adjustable frequency oscillator. The controllers are properly sequenced, simplifying system design. ICC(gate charge) + f @ QG Supply Sequencing (eq. 1) where, f is the operating frequency and QG is the gate charge of the external MOSFETs. The PFC controller is enabled once VCC reaches VCC(on) and the PFB voltage exceeds VUVP(high), typically 290 mV. Once the PFC controller is enabled the PControl pin begins to charge. Once the control voltage exceeds VEA(OL) the first PFC drive pulse is observed. The half−bridge driver is enabled once the first PFC drive pulse is generated. This ensures a monotonic output voltage rise as the input voltage to the half bridge stage is regulated. The controller will not start in the event that VCC falls below VCC(MIN) before PFB goes above VUVP(high). This ensures there is enough time to start the controller before VCC reaches VCC(off). Main Oscillator The oscillator frequency is set by the oscillator capacitor, COSC, on the OSC pin. The oscillator operates at a fixed 80% duty ratio. A current source charges COSC to its peak voltage, typically 5 V. Once the peak voltage is reached, the charge current is disabled and COSC is discharged down to 3 V by another current source. The charge and discharge currents are typically 173 and 692 mA, respectively. The oscillator frequency vs oscillator capacitance graph is shown in Figure 3. 100 fOSC, OSCILLATOR FREQUENCY (kHz) Output Voltage Regulation The half−bridge stage operates at a fixed frequency. Output voltage regulation is achieved by adjusting the half−bridge input voltage (PFC output voltage). The PFC output voltage is sensed using a resistor divider. The mid point of the resistor divider connects to the PFB pin. Subtracting current out of the feedback resistor divider increases the PFC output voltage and thus regulation is achieved. High Voltage Startup Circuit The NCP1901 internal startup regulator eliminates the need for external startup components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The startup regulator consists of a constant current source that supplies current from the high voltage line (Vin) to the supply capacitor on the VCC pin (CCC). The startup current (Istart) is typically 7.5 mA. The startup circuit is rated at a maximum voltage of 600 V. Once CCC is charged to 15.3 V (VCC(on)), the startup regulator is disabled and the PFC controller is enabled if the PFB voltage exceeds VPUVP(high). The startup regulator 90 80 70 60 50 40 30 20 10 0 400 800 1200 1600 2000 2400 COSC, OSCILLATOR CAPACITOR (pF) Figure 3. Oscillator Frequency vs. Oscillator Capacitor An internal clock signal is generated dividing by two the oscillator frequency. This clock signal is used to control the half−bridge controller. The half−bridge duty ratio is limited to 50%. The PFC is not synchronized to the oscillator as it operates in CrM. http://onsemi.com 8 NCP1901 ZCD Comparator Voltage Reference PZCD VDD − + The internal voltage reference, VREF, is brought out of the controller to ease compensation requirements. The reference voltage is typically 7.0 V. A 0.1 mF is required for stability. The reference should not be loaded with external circuitry. + > 5.65 V Clamp VZCD S Q Dominant Reset Latch Q R PControl < 2.25 V Clamp IPFB VDD + − VPREF On time Comparator IPCT(C) Level Shifter PCT PFC OVP Comparator + PFC UVP VPOVP − Comparator LEB + − VCCGood PCS Comparator VPCS(ILIM) The PControl voltage is internally clamped between 2.25 V and 5.65 V. An offset voltage greater than the minimum PControl clamp voltage is added to the CT ramp prior to comparing it to the control voltage signal. This allows the PFC stage to stop the drive pulses (0% duty ratio) and regulate at light loads. The delta between the Pcontrol voltage needed to generate a PDRV pulse and the minimum PControl Clamp voltage is VPCT(offset). The timing capacitor is discharged and held low once the CT ramp voltage plus offset reaches VPControl. The PFC drive pulse terminates once the CT voltage reaches its peak voltage threshold, VPCT(peak). A new cycle starts once the inductor current reaches zero detected by a transition on the ZCD pin or the maximum off has been reached. The timing capacitor is sized such that the CT ramp peak voltage is reached at low line and full load. In this operating mode VPControl is at its maximum. Equation 3 is used to calculate the on time for a given CT. High power factor is achieved in CrM by maintaining a constant on time (ton) for a given RMS input voltage (Vac(RMS)) and load conditions. Equation 2 shows the relationship between on time and system operating conditions. 2 @ P out @ L h @ Vac(RMS) 2 PFCoff Figure 5. Constant On Time Control Block Diagram Figure 4. Inductor Current in CrM ton + + − PCS + − + VPUVP − − + PFB + − The PFC stage operates in critical conduction mode (CrM). In CrM, the PFC inductor current, IL(t), reaches zero at the end of the switch cycle as shown in Figure 4. As seen in Figure 4, the average input current, Iin(t), is in phase with the ac line voltage, Vin(t). PFC Error Amplifier + − PFC Regulator (eq. 2) where, Pout is the output power, L is the PFC inductor inductance and h is the system efficiency. On Time Control The NCP1901 controls the on time by charging an external timing capacitor on the PCT pin, CT, with a constant current source, IPCT(C). The CT ramp is then compared to the control voltage, VPControl. The control voltage is constant for a given RMS line voltage and output load, satisfying Equation 2. A voltage offset, VPCT(offset), is added to the CT ramp to account for the control voltage range. The block diagram of the constant on time section is shown in Figure 5. ton(MAX) + C T @ V PCT(MAX) I PCT(C) (eq. 3) Substituting ton in Equation 2 with Equation 3 and rearranging Equation 4 provides a maximum value for CT. CT w 2 @ P out @ L @ I PCT(C) h @ Vac(RMS) 2 @ VPCT(MAX) (eq. 4) where, VPCT(MAX), is the maximum PCT voltage, typically 3.0 V. http://onsemi.com 9 NCP1901 Off Time Control timer is reset at the beginning of a PFC drive pulse and in a PFC undervoltage fault. The PFC off time varies with the instantaneous line voltage and it is adjusted every cycle to allow the inductor current to reach zero before the next switch cycle begins. The inductor is demagnetized once its current reaches zero. Once the inductor is demagnetized the drain voltage of the PFC switch begins to drop. The inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the inductor voltage. Figure 6 shows the ZCD winding arrangement. PFC Compensation A transconductance error amplifier regulates the PFC output voltage, VPFC, by comparing the PFC feedback signal to an internal 2.5 V reference. As shown in Figure 28 a resistor divider from the PFC output voltage consisting of R1 and R2 generates the PFC feedback signal. VPFC R1 PFC Error Amplifier PFB − + R2 IPFB − + VPREF Figure 8. The feedback signal is applied to the amplifier inverting input. The internal 2.5 V reference, VPREF, is applied to the amplifier non−inverting input. The reference is trimmed during manufacturing to achieve an accuracy of ±3.2%. Figure 5 shows the PFC error amplifier and sensing network. Equation 5 is used to calculate the values of the PFC feedback network. Figure 6. ZCD Winding Implementation A negative voltage appears on the ZCD winding while the PFC switch is on. The PZCD voltage is positive while the PFC switch is off and current is flowing through the inductor. The PZCD voltage drops to and rings around zero volts once the inductor is demagnetized. Once a negative transition is detected in the PZCD pin the next switch cycle commences. A positive transition (corresponding to the PFC switch turn off) arms the ZCD detector to prevent false triggering. The arming of the ZCD detector is typically 2.1 V (VPZCD increasing) and the triggering is typically 1.5 V (VPZCD decreasing). The PZCD pin is internally clamped to 10 V with a zener diode. A resistor in series with the ZCD pin is required to limit the current into the PZCD pin. The zener diode prevents the voltage from exceeding the 10 V clamp or going below ground. Figure 7 shows typical ZCD waveforms. VPFC + V PREF @ (eq. 5) A transconductance amplifier has a voltage−to−current gain, gm. That is, the output current is controlled by the differential input voltage. The NCP1901 amplifier has a typical gm of 95 mS. The PControl pin provides access to the amplifier output for compensation. The compensation network is ground referenced allowing the PFC feedback signal to be used to detect an overvoltage condition. The compensation network on the PControl pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle. A capacitor between the PControl pin and ground sets a pole. A pole at or below 20 Hz is enough to filter the ripple voltage for a 50 and 60 Hz system. The low frequency pole, fp, of the system is calculated using Equation 6. Drain Voltage of PFC Switch fp + PDRV gm 2pC PControl (eq. 6) where, CPControl is the capacitor on the PControl pin to ground. A key feature to using a transconductance type amplifier, is that the input is allowed to move independently with respect to the output, since the compensation capacitor is connected to ground. This allows dual usage of the feedback pin by the error amplifier and by the overvoltage comparator. 10 V VPZCD R1 ) R2 ) I PFB @ R1 R2 VZCD(high) VZCD(low) 0V Figure 7. ZCD Winding Waveforms During startup there are no ZCD transitions to enable the PFC switch. A watchdog timer enables the PFC controller if no switch pulses are detected for a period of 180 ms (typical). The watchdog is also useful while operating at light load because the amplitude of the ZCD signal may be very small to cross the ZCD thresholds. The watchdog http://onsemi.com 10 NCP1901 PFC Undervoltage The half−bridge controller has a low side driver, HDRVlo, and a 600 V high side driver, HDRVhi. The built in high voltage driver eliminates the need for an external transformer or dedicated driver. A built−in delay between each drive transition eliminates the risk of cross conduction. The delay is typically 785 ns. The typical duty ratio of each half−bridge driver is 48%. The high side driver is connected between the HBoost and the HVS pins as shown in Figure 10. The NCP1901 safely disables the controller if the PFB pin is left open. An undervoltage detector disables the controller if the voltage on the PFB pin is below VPUVP(low), typically 0.23 V. A 1.2 mA (typical) pull down current source, IPFB, ensures VPFB falls below VPUVP(low) if the PFB pin is floating. The PFB pull down current source affects the PFC output voltage regulation setpoint. PFC Overvoltage An overvoltage detector monitors the PFC feedback voltage and disables the PFC driver if the PFC output voltage is greater than 5% of its nominal value. PFC drive pulses are suppressed until the overvoltage condition is removed. The overvoltage detector tolerance is better than ±2% across the operating temperature voltage range. The overvoltage comparator hysteresis is typically 30 mV (1.2%). PFC Overcurrent The PFC current is monitored by means of an overcurrent detector. The PCS pin provides access to the overcurrent detector. The PFC drive pulse is terminated if the voltage on the PCS pin exceeds the overcurrent threshold, VPCS(ILIM). This comparison is done on a cycle by cycle basis. The overcurrent threshold is typically 0.84 V. The current sense signal is prone to leading edge spikes caused by the power switch transitions. The NCP1901 has leading edge blanking circuitry that blocks out the first 110 ns (typical) of each current pulse. Figure 10. Half−bridge High Side Driver A boost circuit comprised of Dboost and Cboost generates the supply voltage for the high side driver. Once HDRVlo turns on, the HVS pin is effectively grounded through the external power switch. This allows Cboost to charge to VCC. Once HDRVlo turns off, HVS floats high and Dboost is reversed biased. An undervoltage detector monitors the HBoost voltage. Once the HBoost voltage is greater than VBoost(UV), typically, 6.1 V, the high side driver is enabled. The low side driver generally starts before the high side driver because the boost voltage is generated by the low side driver switch transitions. The half−bridge low side driver source and sink impedances are typically 75 and 15 W, respectively. The half−bridge high side driver source and sink impedances are typically 75 and 15 W, respectively. Depending on the external MOSFETs gate charge requirements, an external driver may be needed to drive the low and high side power switches. PFC Driver The PFC driver source and sink impedances are typically 60 and 15 W, respectively. Depending on the external MOSFET gate charge requirements, an external driver may be needed to drive the PFC power switch. A driver as the one shown in Figure 9 can be easily implemented. Analog and Power Ground The NCP1901 has an analog ground, GND, and a power ground, PGND, terminal. GND is used for analog connections such as VREF and OSC. PGND is used for high current connections such as the gate drivers. It is recommended to have independent analog and power ground planes and connect them at a single point, preferably at the ground terminal of the system. This will prevent high current flowing on PGND from injecting noise in GND. The PGND connection should be as short and wide as possible to reduce inductance−induced spikes. Figure 9. External Driver Half−Bridge Driver The half−bridge stage operates at a fixed 50% duty ratio. The oscillator frequency is divided by two before it is applied to the half−bridge controller. http://onsemi.com 11 NCP1901 PACKAGE DIMENSIONS SO−20 WB CASE 751D−05 ISSUE G A 20 q X 45 _ 1 10 20X B B 0.25 M T A S B S A L M E h H 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 12 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ NCP1901 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− P 1 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS The products described herein (NCP1901) may be covered by one or more of the following U.S. patents: 6,373,734. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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