NCL30051 PFC and Half-Bridge Resonant Combo Controller for LED Lighting The NCL30051 is a combination of PFC and half−bridge resonant controllers optimized for off−line LED lighting solutions. This device integrates all the features needed to implement a highly efficient and small form factor LED Driver/Power Supply. It contains a critical conduction mode (CrM) power factor correction (PFC) boost controller and a half−bridge resonant controller with a built−in 600 V driver. The half−bridge stage operates at a fixed frequency, greatly simplifying the control implementations. The output (current or voltage) regulation is achieved by adjusting the PFC stage output voltage − based on a control signal generated external to the NCL30051. This device includes an enable input on the PFC feedback pin, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCL30051 are a 600 V startup circuit and an adjustable frequency oscillator with a divide by 2 circuit to assure true symmetric duty ratio. The controllers are properly sequenced, simplifying system design. http://onsemi.com MARKING DIAGRAM SOIC−16 D SUFFIX CASE 751B A WL Y WW G • • • • • Typical Applications • High Efficiency LED Drivers and Power Supplies • Electronic Control Gear • Lighting Ballasts November, 2011 − Rev. 0 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package 1 Voltage Mode CrM Power Factor Correction Controller PFC Open Feedback Loop Protection PFC Undervoltage Detector PFC Overvoltage Detector Half−Bridge Stage with 600 V High Side Gate Drive State Machine Ensures Proper Turn−on and Turn−off of Half−Bridge Stage Controllers are Properly Sequenced for Fault Free Operation Non−Latching Fault Management Internal 600 V Startup Circuit Wide Temperature Range of −40°C to +125°C This is a Pb−Free Device © Semiconductor Components Industries, LLC, 2011 NCL30051G AWLYWW PIN CONNECTIONS Features • • • • • • 16 HV HBoost OSC HDRVhi GND HVS VREF HDRVlo PFB PDRV PCS PGND PZCD VCC PControl PCT SOIC−16 ORDERING INFORMATION Device Package Shipping† NCL30051DR2G SOIC−16 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: NCL30051/D NCL30051 VCC PDRV tPFC(off)Timer UVLO Disable ZCD Comparator 10V + − + PZCD UVLO VCC Good > 5.65 V Clamp VDD − VPREF On time Comparator Level Shifter PFC OVP Comparator IPCT(C) LEB + − + − PCS − PFCUVP Delay + − VPOVP HBoost HDRVhi Cboost HVS VCC HDRVlo Delay Q Clock Disable VCCGood CLK Q Q Enable PCS Comparator VPCS(ILIM) PDRV S Q UVLO R Figure 1. Functional Block Diagram http://onsemi.com 2 CCC Dboost S Dominant Reset Latch Q R GND − + + Q + − VPUVP + VCC(on)/ VCC(off)/ UVLO Pulse Trigger − + PFC UVP Comparator VCC Undervoltage Detector Level Shifter + − PCT + + − IPFB + − + − VCC Management S Q Dominant Reset Latch Q R < 2.25 V Clamp PFC PFC UVP Error Amplifier UVLO PFB HV Istart Edge Detector VDD VZCD PControl Reset PDRV VHB(DIS) − VDD IOSC(C) CLK + − + 5 V/ 3V − VDD OSC 4*IOSC(C) Voltage Reference VREF NCL30051 Table 1. PIN FUNCTION DESCRIPTION Pin Name Description 1 HV 2 OSC A capacitor on this pin adjusts the frequency of the internal oscillator. The oscillator sets the frequency of the half−bridge controller. Each half−bridge switch operates at half the oscillator frequency. The OSC pin also serves as a disable input for the half−bridge stage. The half−bridge stage is disabled by pulling down this pin below its disable threshold, VHB(DIS), typically 1.955 V. 3 GND Analog ground. 4 VREF Reference voltage. The capacitor on this pin decouples the internal reference. A 0.1 mF capacitor needs to be connected between this pin and ground. 5 PFB PFC voltage feedback input. Connect to PFC output using a resistive divider network. The voltage on this pin is compared to a 2.5 V reference (typical) to regulate the PFC output voltage. The voltage on this pin is also used to detect PFC undervoltage and overvoltage conditions. In the typical intended application, the PFB pin voltage will set an upper bound on the PFC output voltage, while the actual PFC voltage control will be exercised by a control signal generated on the secondary side to provide accurate LED current/voltage control. 6 PCS PFC regulator current sense input. A voltage ramp proportional to the PFC switch current is applied to this pin. The current sense threshold, VPCS(ILIM), is typically 0.84 V. A 110 ns (typical) leading edge blanking circuit filters the current sense signal at the start of each cycle. 7 PZCD PFC inductor zero current detector. The inductor current is monitored using an auxiliary winding on the PFC inductor. The PFC drive signal is enabled during a high to low transition on the PZCD pin. A series resistor limits the current into the PZCD pin. The watchdog timer is disabled while the PZCD voltage is above the ZCD arming threshold, VZCD(high). It is re−enabled once the voltage drops below the ZCD trigger threshold, VZCD(low). This feature can be used to disable PFC drive pulses. 8 PControl PFC control voltage. This pin connects to the output of the PFC error amplifier. The error amplifier is a transconductance amplifier. A compensation network between this pin and grounds sets the PFC loop bandwidth. The PFC control voltage is compared to a level shifted version of VPCT to control the PFC duty ratio. In the typical intended application, the PControl voltage will be controlled by a secondary side control signal through an optocoupler. The optocoupler signal is diode ORed to the internally generated PControl signal and the lower of the two signals dictates the PFC on-time. 9 PCT PFC on time control capacitor. A 270 mA (typical) current source charges a capacitor connected between this pin and ground. Once the level shifted PCT voltage reaches VPControl, the PFC drive signal is disabled and the PCT capacitor is discharged. 10 VCC Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from HV to this pin. Once the VCC voltage reaches VCC(on) (15.3 V typical), the current source turns off and the controller is enabled. The current source turns on once VCC falls to VCC(off) (9.3 V typical). During normal operation, power is supplied to the IC via this pin by means of an auxiliary winding. 11 PGND Ground connection for PDRV and HDRVlo. Tie to the power stage return with a short trace. 12 PDRV PFC switch gate drive control signal. The source and sink drive capability is limited to 60 W and 15 W (typical), respectively. A discrete driver may be needed to drive the external MOSFET. 13 HDRVlo Half−bridge low side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. A discrete driver may be needed to drive the half bridge switch. 14 HVS Half−bridge high side driver source connection. This pin connects directly to the bridge terminal and can float up to 600 V. 15 HDRVhi Half−bridge high side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. The supply terminals of the high side driver connect to the HBoost and HVS pins. A discrete driver may be needed to drive the half bridge switch. 16 HBoost Supply voltage of the high side gate driver. A charge pump generates a bootstrap voltage floating on top of the HVS voltage. A diode between the VCC and HBoost pins provides a charge path. The bootstrap voltage is VCC minus a diode drop. This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A constant current source supplies current from this pin to the VCC capacitor, eliminating the need for an external startup resistor. The charge current is 7.5 mA (typical). http://onsemi.com 3 NCL30051 Table 2. MAXIMUM RATINGS (Notes 1 and 2) Rating Symbol Value Unit High Voltage Input Voltage VHV −0.3 to 600 V High Voltage Input Current IHV 10 mA Supply Input Voltage VCC −0.3 to 20 V Supply Input Current ICC 10 mA Oscillator Input Voltage VOSC −0.3 to VREF V Oscillator Input Current IOSC 10 mA Bandgap Reference Decoupling Output Voltage VREF −0.3 to 9 V Bandgap Reference Decoupling Output Current IREF 10 mA PFC Feedback Voltage Input Voltage VPFB −0.3 to 10 V PFC Feedback Voltage Input Current IPFB 10 mA PFC Current Sense Input Voltage VPCS −0.3 to 10 V PFC Current Sense Input Current IPCS 10 mA PFC Zero Current Detection Input Voltage VPZCD −0.3 to 10 V PFC Zero Current Detection Input Current IPZCD 10 mA PFC Control Input Voltage VPControl −0.3 to VREF V PFC Control Input Current IPControl 1.2 mA PFC On Time Control Input Voltage VPCT −0.3 to VREF V PFC On Time Control Input Current IPCT 9 mA PFC Drive Signal Voltage VPDRV −0.3 to VCC V PFC Drive Signal Current IPDRV 100 mA Half−Bridge Low Side Driver Input Voltage VHDRVlo −0.3 to VCC V Half−Bridge Low Side Driver Input Current IHDRVlo 100 mA Half−Bridge High Side Driver Source Connection Input Voltage VHVS −1.0 to 600 V Half−Bridge High Side Driver Source Connection Input Current IHVS 100 mA Half−Bridge High Side Driver Input Voltage VHDRVhi −1.3 to VHVS+VCC V Half−Bridge High Side Driver Input Current IHDRVhi 100 mA Half−Bridge High Side Driver Charge Pump Input Voltage VHBoost −0.3 to VHVS+VCC V Half−Bridge High Side Driver Charge Pump Input Current IHBoost 100 mA High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) VHBoost(supply) −0.3 to VCC V High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) IHBoost(supply) 100 mA dVHVS/dt 50 V/ns Junction Temperature (Biased) TJ 150 °C Storage Temperature Range Tstg –60 to 150 °C Power Dissipation (TA = 25°C, 1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B−05 (SOIC−16) PD 0.95 W RθJA 130 °C/W Half−Bridge High Side Driver Source Connection Slew Rate Thermal Resistance, Junction to Ambient (1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B−05 (SOIC−16) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device(s) contains ESD protection and exceeds the following tests: Pins 1, 14, 15 and 16 rated to the maximum voltage of the respective pins based on the maximum ratings table. All Other Pins: Human Body Model 1500 V per JEDEC Standard JESD22−A114E. All Other Pins: Machine Model 150 V per JEDEC Standard JESD22−A115−A. 2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78. http://onsemi.com 4 NCL30051 Table 3. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VCC Increasing VCC Decreasing VCC Decreasing VCC(on) VCC(enable) VCC(off) 14.3 13.6 8.5 15.3 14.6 9.3 16.3 15.6 10.0 VPFB = VPUVP(low) (Note 3) ICC1 ICC2 1.0 1.8 1.4 2.4 1.8 3.0 Startup Current VCC = VCC (on) – 0.2 V, VHV = 50 V Istart 3.0 7.5 10.5 mA Startup Circuit Off−State Leakage Current VHV = 600 V, VCC = VCC (on) + 0.2 V IHV(off) – 15 50 mA CREF = 0.1 mF VREF 6.605 7.000 7.295 V STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Enable Threshold Minimum Operating Voltage Supply Current Device Disabled/Fault Device Switching V mA BANDGAP REFERENCE Reference Voltage OSCILLATOR Half−Bridge Clock Frequency VHVS = 50 V fclock 13.5 15.5 16.5 kHz Maximum Half−Bridge Clock Frequency COSC = open fclock(MAX) 75 – – kHz 2.42 2.40 2.50 − 2.58 2.60 PFC ERROR AMPLIFIER PFC Feedback Voltage Reference VPREF 0°C < TJ < 125°C −40°C < TJ < 125°C PFC Feedback Voltage Reference Regulation with Line Error Amplifier Drive Capability Sink Source Open Loop Error Amplifier Transconductance V VCC(on) + 0.2 V < VCC < 20 V VPREF(line) −15 – 15 mV VPControl = 4 V, VPFB = 5 V VPControl = 4 V, VPFB = 0.5 V IEA(SNK) IEA(SRC) 60 −60 80 −80 – – VPControl = 4 V, VPFB = 2.4 V and 2.6 V Gm 60 95 – mS mA Feedback Input Pulldown Current Source VPFB = 3 V IPFB 0.5 1.2 1.5 mA Error Amplifier Maximum Output Voltage IPControl = 10 mA VEA(OH) 5.30 5.65 6.00 V Error Amplifier Minimum Output Voltage IPControl = −10 mA VEA(OL) 2.10 2.25 2.40 V Error Amplifier Output Voltage Range VEA(OH) − VEA(OL) ΔVEA 3.1 3.4 3.7 V 3. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins. http://onsemi.com 5 NCL30051 Table 4. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit VPCS(ILIM) 0.78 0.84 0.92 V IPCS −1 0 1 mA tPCS(LEB) 40 110 200 ns VPCS = VPCS(ILIM) + 1 V tPCS(delay) – 90 250 ns VPZCD increasing VPZCD decreasing VZCD(high) VZCD(low) 1.9 1.3 2.1 1.5 2.3 1.7 VZCD(HYS) 400 600 800 mV IPZCD(bias1) IPZCD(bias2) −1 −1 – – 1 1 mA tPFC(off) 50 180 350 ms PFC CURRENT SENSE Current Sense Threshold Voltage Current Sense Input Bias Current VPCS = 2 V Leading Edge Blanking Duration Propagation Delay PFC ZERO CURRENT DETECTION ZCD Threshold Voltage Arming Threshold Trigger Threshold ZCD Voltage Hysteresis ZCD Input Bias Current VPZCD = 1 V VPZCD = 5 V V PFC MAXIMUM OFF TIME Maximum Off Time PFC ON TIME RAMP GENERATOR ON time Capacitor Charge Current VPCT = 0 V IPCT(C) 220 270 300 mA On Time Capacitor Discharge Time VPCT = 2.4 V to 0.6 V tPCT(D) – 70 300 ns VPCT(peak) 2.6 3.0 3.4 V VPFB = 3.0 V, VPZCD = 0 V DPMIN 0 – – % VPCT = VPCT(peak) + 1 V tPCT(delay) – 250 375 ns DVEA − VPCT(peak) VPCT(offset) 250 400 550 mV Overvoltage Detector Threshold Voltage Midpoint between high and low threshold, VPControl = 4 V VPOVP 1.03* VPREF 1.05* VPREF 1.07* VPREF V Overvoltage Comparator Hysteresis Window VPControl = 4V VPOVP(HYS) 5 30 60 mV VPFB = VPREF + 1 V tPOVP(delay) – 400 800 ns Undervoltage Detector Threshold Voltage VPFB increasing VPFB decreasing VPUVP(high) VPUVP(low) − 175 290 230 350 − mV Undervoltage Comparator Hysteresis VPFB increasing VPUVP(HYS) 20 60 100 mV PFC Driver Rise Time 10% to 90% (Note 4) tPDRV(rise) − 18 − ns PFC Driver Fall Time 90% to 10% (Note 4) tPDRV(fall) − 9 − ns PFC Driver High State Voltage IPDRV = −8 mA VPDRV(OH) 14.00 14.55 − V PFC Driver Low State Voltage IPDRV = 8 mA VPDRV(OL) − 0.12 0.50 V ON Time Capacitor Peak Voltage Minimum Duty Ratio Maximum On Time Detect Delay Voltage Delta between PControl Voltage Needed to Generate PDRV Pulses and VEA(OL) PFC OVERVOLTAGE and UNDERVOLTAGE Propagation Delay PFC DRIVER 4. Resistor/capacitor parallel combination (39 pF || 20 kW) between PDRV and driver supply and between PDRV and GND pins. http://onsemi.com 6 NCL30051 Table 5. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V, VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25°C, for min/max values, TJ is −40°C to 125°C, unless otherwise noted) Characteristics Conditions Symbol Min Typ Max Unit Half−Bridge High Side Driver Rise Time 10% to 90% (Note 5) tHDRVhi(rise) – 18 – ns Half−Bridge High Side Driver Fall Time 90% to 10% (Note 5) tHDRVhi(fall) – 9 – ns High State Voltage IHDRVhi = −4 mA VHDRVhi(OH) 14.0 14.7 – V Low State Voltage IHDRVhi = 4 mA VHDRVhi(OL) – 0.06 0.5 V 10 to 90% to 10% transitions, VHSVS = 50 V (Note 5) DHDRVhiMAX 44 48 50 % VHBoost(UVLO) 4 6.1 8.0 V HDRVhi switching, between HDRVhi and HVS (Note 5) ICC(Boost) – 0.1 0.5 mA TJ = 25°C, VHVS = 600 V, VHBoost = 600 V IHVS(off) – 0.1 1 mA Half−Bridge Low Side Driver Rise Time 10% to 90% (Note 5) tHDRVlo(rise) – 18 – ns Half−Bridge Low Side Driver Fall Time 90% to 10% (Note 5) tHDRVhi(fall) – 9 – ns Half−Bridge Low Side Driver High State Voltage IHDRVlo = −4 mA VHDRVlo(OH) 14 14.7 – V Half−Bridge Low Side Driver Low State Voltage IHDRVlo = 4 mA VHDRVlo(OL) – 0.06 0.5 V Half−Bridge Low Side Driver Duty Ratio 10 to 90% to 10% transitions (Note 5) DHDRVloMAX 44 48 50 % Delay from HDRVlo high to low to HDRVhi low to high transition VHVS = 50 V tHDRVhi(h−l) 500 785 950 ns Delay from HDRVhi high to low to HDRVlo low to high transition VHVS = 50 V tHDRVhi(h−l) 500 785 950 ns Half−Bridge Disable VOSC Decreasing VHB(DIS) 1.550 1.955 2.300 V Half−Bridge Disable Hysteresis VOSC Increasing VHB(DIS−HYS) − 130 − mV HALF BRIDGE HIGH SIDE DRIVER High Side Driver Duty Ratio Boost Supply Undervoltage Threshold Boost Current Consumption HVS Leakage Current HALF BRIDGE LOW SIDE DRIVER CROSSOVER DEAD TIME HALF−BRIDGE DISABLE 5. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between HDRVxx and GND pins. http://onsemi.com 7 NCL30051 DETAILED OPERATING DESCRIPTION EMI AC Input Filter LBST DBST Vbulk T1 Cbulk QH QBST DR1 Cout Vout LR DR2 QL VREF 6 12 7 1 4 9 3 11 PCS PFB PDRV VCC PZCD HBoost HV VREF HDRVhi HVS PCT HDRVlo GND PControl PGND OSC 5 10 16 15 14 13 8 2 VCC VDD Z 2.5 V Z 2.5 V VDD Secondary Side Compensation (CCCV) Logic PWM Figure 2. Simplified Application Block Diagram OVERVIEW same time places constraints that have to be taken into account during the converter design. Traditional 2-stage converters have independent control loops for the PFC stage and the step-down stage, allowing each converter output to be regulated on its own. The PFC stage is often designed for critical conduction (CrM) or continuous conduction mode (CCM) operation and the step-down stage is typically a current-mode/voltage-mode PWM controller geared for forward or flyback applications. More recently, some solutions such as the NCP1910 CCM PFC two stage combo from ON Semiconductor have become available which incorporates the half-bridge resonant converter topology which offers significant efficiency and EMI advantages. However, this HBR topology involves varying the switching frequency to regulate the output and hence adds further complexity to such combination controllers. In contrast, the NCL30051 simplifies the overall approach significantly by implementing the HBR approach for the second stage converter at a fixed frequency. This simply means that the second-stage converter now operates in a non-regulating fixed-ratio voltage conversion mode. The implication of this approach is that output regulation control has to be provided by adjusting the output of the PFC front-end converter. The benefits of this approach can be summarized as follows: The NCL30051 is a combination of a PFC boost controller and a half−bridge resonant controller optimized for off-line LED lighting solutions. This device integrates all the features needed to implement a highly efficient and small form factor LED driver. It contains a critical conduction mode (CrM) power factor correction (PFC) controller and a half−bridge resonant (HBR) controller with a built−in 600 V driver. The half−bridge stage operates at a fixed frequency − greatly simplifying the control implementation. Output (current or voltage) regulation can be achieved by adjusting the PFC stage output voltage based on a control signal generated external to the NCL30051. This device includes an enable input on the PFC feedback pin, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCL30051 are a 600 V startup circuit and an adjustable frequency oscillator. The controllers are properly sequenced, simplifying the system design. THEORY OF OPERATION The NCL30051 provides an innovative control mechanism compared to traditional two stage power conversion architectures. This unique regulation scheme offers extreme simplicity for certain applications, but at the http://onsemi.com 8 NCL30051 • Low pin-count of controller combines strong feature • • • • • • load current. The output voltage follows this discharge rate with a fixed ratio. By increasing the bulk capacitance value, this discharge rate can be slowed down increasing hold-up time. However, this approach has practical limits and is not recommended for applications requiring a long hold-up time with no output voltage variation. Figure 2 illustrates a typical NCL30051 2-stage converter implementation. As seen in the figure, the isolated second stage converter output value is processed by a compensation circuit in the secondary and an error signal is generated and coupled to the primary using an opto-coupler. On the primary side, this signal is fed to the PControl pin of NCL30051 through a reverse ORing diode. The PControl pin also has a default error signal generated by the PFC error amplifier. The lower of these two signals dominates and helps set the fixed ON time for the PFC block as described in earlier sections. In the intended implementation, the NCL30051’s PFC error amplifier should be configured to set the maximum value of the output voltage and the secondary side feedback should be allowed to control it lower based on the output conditions. set Low external component count ZVS of the second stage FETs without any tuning requirements High efficiency facilitates improved thermal performance Low EMI and easy filtering due to fixed frequency Facilitation of synchronous rectification control design Easier design of magnetic components (esp. Resonant transformer and inductor) While the above listed benefits make this approach a very interesting proposition for many isolated applications with PFC front-end, it has to be implemented with some additional considerations. The fact that the output regulation is achieved by adjusting the PFC output voltage, places additional limits on the PFC stage that is not needed in the traditional approach. Depending on the application and output requirements, this may not be much of a constraint. However, if the output variation requirements are significant, the PFC stage may not have enough dynamic range to provide sufficient output power control. The other consideration is related to the response time to any output variations. In a true 2-stage conversion, the decoupling of the two stages allows a better transient response. In that case the PFC converter is constrained to a bandwidth much below the line frequency (typically < 20 Hz), whereas the second stage can be optimized to have a very fast dynamic response. In the NCL30051 application, the second stage has no independent output regulation ability, so the dynamic response is constrained by the PFC stage bandwidth. This limitation means that the approach is not suited for very fast-transient loads. However, a large number of applications (such as LED drivers and battery chargers) can easily accept the response times offered by the NCL30051 approach. Output voltage ripple is another consideration when designing with the NCL30051. The low frequency ripple on the PFC output stage is determined by the size of the PFC capacitor. With no compensation in the second stage, the final output voltage ripple is simply a scaled version of the PFC output ripple determined by the fixed ratio of the second stage. Normally this type of ripple is not a concern for lighting applications as the ripple frequency (100/120 Hz) is above the eye response frequency or in the case of fixed output LED power supplies, there are secondary side constant current regulators that further reduces the ripple. Finally, hold-up time is another matter to be considered when using this fixed-ratio converter approach. When the input voltage droops, the output of the PFC starts dropping at a rate determined by the bulk capacitance value and the DESIGN CONSIDERATIONS – POWER STAGE Given the unique nature of the NCL30051, certain power stage design considerations are applicable (for PFC and second-stage) as below. These design considerations are described for a constant current LED lighting application, but can also apply to constant voltage applications with minor variations. PFC Output (Vbulk) Voltage Range The minimum bulk voltage setting is dictated by the requirement that the PFC output voltage be higher than the peak of the input line voltage at all times. Even though many lighting applications operate from a single voltage range which simplifies the analysis, we will consider an input range of 85-265 Vac which covers most regional requirements, this means the minimum bulk voltage is set in the range of 385-400 Vdc. However, if the circuit has to handle 277 Vac ±10% input also (as in the case of US commercial lighting applications), the minimum bulk setting goes up to 435 Vdc. The maximum bulk setting is limited by component stress factors and other considerations. The major constraints are bulk capacitor, output (boost) diode, boost FET and the NCL30051 voltage rating. While other power stage considerations are covered in the paragraphs below, the application of NCL30051 requires that the bulk voltage be limited to below 600 V maximum under all conditions. The NCL30051 high-voltage section is rated at 600 V − this includes pins HV and HVS. The HBoost and HDRVhi pins see the highest potential, given by Vbulk+Vcc. In normal operation the bulk is limited to 540 V based on the derating criteria. This is the same derating which would be applied to the 600 V output rectifier in the PFC stage. http://onsemi.com 9 NCL30051 PFC Output Capacitor - Cbulk inductance required. Thus, variation in PFC voltage results in higher boost inductor value and size (and/or higher ripple current when the output voltage is higher). The bulk capacitor is one of the most critical components in the PFC design. High value, high voltage capacitors are expensive and take up a large space. In traditional PFC applications, the voltage rating of this capacitor is about 450 V (some designers cut it to 420 V for cost savings), but for 277 Vac lighting applications, 450 V rating is not sufficient. As shown in the table above, if the output voltage is allowed to vary, the bulk voltage can go even higher. Availability of bulk capacitors above 450 V is limited. One solution is to take two capacitors and put them in series. The effective value of two series capacitors is lower, but for low-medium power applications, this should not be a big issue. For 600 V maximum bulk voltage, two 400 V capacitors need to be used, but for 90−135 Vac only applications, lower rated capacitors can be used. When putting capacitors in series, it is required to have a parallel high value resistor pair in order to ensure voltage sharing. The effective bulk capacitance value also depends on the application requirements. Normal rule of thumb for traditional PFC circuits is to use around 1 mF/W to achieve desired hold-up time and ripple performance. In this approach, due to absence of a regulated second stage, it may be prudent to increase the capacitance value if low ripple or fast transient response is required. Another factor in selecting the capacitor is that it handles high ripple current due to the CrM topology implemented here. The equations for ripple current through the capacitor are derived in ON Semiconductor application note AND8123 and should be used to determine that the selected capacitor can handle the ripple current without overheating or lifetime degradation. HBR Converter Design The half-bridge resonant converter utilizes an LLC resonant circuit to achieve the ZVS of the primary switches and also to reduce the transition losses in the secondary. Additionally, this circuit offers a major benefit wherein the output inductor can be eliminated. In traditional LLC approaches, when the second stage converter is regulated, the switching frequency of the HBR converter has to be varied to respond to load or line changes. As a result, operation near the resonant frequency is not always guaranteed and the efficiency takes a hit. Also, varying the frequency imposes additional design burden on the designer to ensure that the control circuit is stable and provides desired results over the full load and line range. The feedback design and loop closure is more challenging in this type of converter. By keeping a constant switching frequency, not only is the control circuit simplified, the magnetics design also becomes easier. The transformer size can be reduced as it is designed for a single frequency and full optimization is available. Studies have shown that this approach leads to about 25-40% reduction in total magnetics area-product. Other design considerations for the LLC resonant converter remain the same as given in ON Semiconductor application note AND8311 and are not repeated here. The power conversion architecture of the NCL30051 is ideal for many LED Lighting applications since it provides higher efficiency and power factor correction. Since hold-up time and output ripple are not major considerations in these applications, NCL30051 fits in very well. This means that it is ideal for fixed output voltage LED power supplies (ex: 24 Vdc and 48 Vdc) as well as constant current schemes where the output voltage varies depending on the number of LEDs and the variation of the LED forward voltage. This topology is best suited for applications where the output voltage variation is constrained to a ratio of about 1.5 for designs that require operation at 230 Vac. PFC Diode (DBST) The PFC diode provides the rectification function and has to be rated above the peak value of Vbulk. In the CrM operation, with the diode current going to zero every cycle prior to its turn-off, the reverse recovery is not that prominent and an ultrafast diode can be used. In addition, there is little or no overshoot caused by the reverse recovery, so the FET voltage is also well contained. In most cases a 600 V diode is sufficient depending on the derating criteria. Supply Sequencing The error amplifier of the PFC controller is enabled once VCC reaches VCC(on) and the PFB voltage exceeds VPUVP(high), typically 290 mV. Once enabled, the PControl voltage starts rising and when it exceeds VEA(OL) and VCC is above VCC(enable), the first PFC drive pulse is generated. The half-bridge driver is enabled after the first PFC drive pulse is generated. This ensures a monotonic output voltage rise as the input voltage to the half bridge stage is regulated. In the event that VCC falls below VCC(enable) before the control voltage exceeds VEA(OL), the error amplifier will remain on and VCC will fall to Vcc(OFF) at which time the HV startup circuit will be enabled and a new startup sequence will be initiated. PFC Switch (QBST) Typically, the PFC switch is a MOSFET rated anywhere from 500 V to 650 V. Better commercial availability of higher voltage rated FETs in recent years has meant that the QBST is not a major constraint in implementation of variable Vbulk approach offered by NCL30051. However, depending on derating guidelines and practices, the 600 V rating of the FET may not be sufficient. In that case, a higher voltage FET is required. PFC Inductor (LBST) The PFC inductor is designed using the standard CrM design equations. When the output voltage goes up from 390 V to 540 V, there is about 20% increase in value of http://onsemi.com 10 NCL30051 High Voltage Startup Circuit fOSC, OSCILLATOR FREQUENCY (kHz) 100 The NCL30051 internal startup regulator eliminates the need for external startup components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The startup regulator consists of a constant current source that supplies current from the high voltage line (Vin) to the supply capacitor on the VCC pin (CCC). The startup current (Istart) is typically 7.5 mA. The startup circuit is rated at a maximum voltage of 600 V. Once CCC is charged to 15.3 V (VCC(on)), the startup regulator is disabled and the PFC controller is enabled if the PFB voltage exceeds VPUVP(high). The startup regulator remains disabled until the lower supply threshold, VCC(off), (typically 9.3 V) is reached. Once reached, the drive outputs are disabled and the startup current source is enabled. Once the outputs are disabled, the bias current of the NCL30051 is reduced, allowing VCC to charge back up. The supply capacitor provides power to the controller while operating in the power up or self−bias mode. During the converter power up, CCC must be sized such that a VCC voltage greater than VCC(off) is maintained while the auxiliary supply voltage is building up. Otherwise, VCC will collapse and the controller will turn off. The IC bias current and gate charge load at the drive outputs must be considered to correctly size CCC. The increase in current consumption due to external gate charge is calculated using Equation 1. ICC(gate charge) + f @ QG 90 80 70 60 50 40 30 20 10 0 400 800 1200 1600 2000 COSC, OSCILLATOR CAPACITOR (pF) 2400 Figure 3. Oscillator Frequency vs. Oscillator Capacitor An internal clock signal is generated by dividing the oscillator frequency by two. This clock signal is used to control the half−bridge driver. The half−bridge duty ratio is limited to 50%. The PFC is not synchronized to the oscillator as it operates in variable frequency mode. Half−Bridge Disable The half−bridge oscillator and the half−bridge low and high side drivers are disabled once the voltage on the OSC pin is brought below the half−bridge disable threshold, VHB(DIS) (typically 1.955 V). This can be accomplished by pulling down on the oscillator pin using a transistor or open collector/drain device. Once the oscillator pin is released the oscillator capacitor returns to its normal operating range and the half bridge is re−enabled. The low side half−bridge driver generates the first drive pulse during initial power up or re−starting of the half−bridge. This ensures boost voltage is generated to supply the high side driver. (eq. 1) where, f is the operating frequency and QG is the gate charge of the external MOSFETs. Main Oscillator The oscillator frequency is set by the oscillator capacitor, COSC, on the OSC pin. The oscillator operates at a fixed 80% duty ratio. A current source charges COSC to its peak voltage, typically 5 V. Once the peak voltage is reached, the charge current is disabled and COSC is discharged down to 3 V by another current source. The charge and discharge currents are typically 173 and 692 mA, respectively. The oscillator frequency vs oscillator capacitance graph is shown in Figure 3. Voltage Reference The internal voltage reference, VREF, is brought out of the controller to ease compensation requirements. The reference voltage is typically 7.0 V. A 0.1 mF bypass capacitor is required for stability. The reference should not be loaded with external circuitry. http://onsemi.com 11 NCL30051 ZCD Comparator PFC Regulator PZCD VDD < 2.25 V Clamp S Q Dominant Reset Latch Q R IPCT(C) PCT t + − VPREF On time Comparator Level Shifter PFC OVP Comparator + PFC UVP VPOVP − Comparator Figure 4. Inductor Current in CrM + VPUVP − PCS LEB + − (eq. 2) + − High power factor is achieved in CrM by maintaining a constant on time (ton) for a given RMS input voltage (Vac(RMS)) and load conditions. Equation 2 shows the relationship between on time and system operating conditions. + − t − + VDD Iin(t) + − IPFB PFC Error Amplifier + − PFB 2 @ P out @ L h @ Vac(RMS) 2 VZCD PControl IL(t) ton + + 10V > 5.65 V Clamp Vin(t) PFC MOSFET Drive Signal − + The PFC inductor current, IL(t), reaches zero at the end of the switch cycle as shown in Figure 4 and the average input current, Iin(t), is in phase with the ac line voltage, Vin(t). PFCoff VCCGood PCS Comparator VPCS(ILIM) Figure 5. Constant On Time Control Block Diagram where, Pout is the output power, L is the PFC inductor inductance and h is the system efficiency. The PControl voltage is internally clamped between 2.25 V and 5.65 V. A voltage offset, VPCT(offset), is added to the CT ramp to account for the control voltage range. This allows the PFC stage to stop the drive pulses (0% duty ratio) and regulate at light loads. The delta between the PControl voltage needed to generate a PDRV pulse and the minimum PControl Clamp voltage is VPCT(offset). The timing capacitor is discharged and held low once the CT ramp voltage plus offset reaches VPControl. The PFC drive pulse terminates once the CT voltage reaches its peak voltage threshold, VPCT(peak). A new cycle starts once the inductor current reaches zero detected by a transition on the ZCD pin or the maximum off time has been reached. The timing capacitor is sized such that the CT ramp peak voltage is reached at low line and full load. In this operating mode VPControl is at its maximum. Equation 3 is used to calculate the on time for a given CT. On Time Control The NCL30051 controls the on time by charging an external timing capacitor on the PCT pin, CT, with a constant current source, IPCT(C). The CT ramp is then compared to the control voltage, VPControl. The control voltage is constant for a given RMS line voltage and output load, satisfying Equation 2. The block diagram of the constant on time section is shown in Figure 5. ton(MAX) + C T @ V PCT(peak) IPCT(C) (eq. 3) Substituting ton in Equation 2 with Equation 3 and rearranging Equation 4 provides a maximum value for CT. CT w 2 @ Pout @ L @ IPCT(C) h @ Vac(RMS) 2 @ VPCT(peak) (eq. 4) where, VPCT(peak), is the maximum PCT voltage, typically 3.0 V. http://onsemi.com 12 NCL30051 PFC Startup Drain Voltage of PFC Switch The output of the error amplifier is pulled low with an internal pull down transistor when the supply voltage has not reached VCC(on) or if there is a PFC undervoltage fault. This ensures a soft−start sequence once the PFC is enabled and eliminates output voltage overshoot during on/off tests. Once the error amplifier is enabled the output of the error amplifier charges quickly to the minimum clamp voltage. PDRV 10 V VPZCD Figure 7. ZCD Winding Waveforms Off Time Control The PFC off time varies with the instantaneous line voltage and it is adjusted every cycle to allow the inductor current to reach zero before the next switch cycle begins. The inductor is demagnetized once its current reaches zero. Once the inductor is demagnetized the drain voltage of the PFC switch begins to drop. The inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the inductor voltage. Figure 6 shows the ZCD winding arrangement. + RPZCD − + VZCD − During startup there are no ZCD transitions to enable the PFC switch. A watchdog timer enables the PFC controller if no switch pulses are detected for a period of 180 ms (typical). The watchdog timer is also useful while operating at light load because the amplitude of the ZCD signal may be very small to cross the ZCD thresholds. The watchdog timer is reset at the beginning of a PFC drive pulse and in a PFC undervoltage fault. The watchdog timer is disabled if the voltage on the PZCD pin is above VZCD(high). It is re−enabled once the voltage on the PZCD pin drops below VZCD(low). Disabling the watchdog timer allows the PFC to be disabled by pulling up on the PZCD pin. Care should be taken to limit the current into the PZCD pin to prevent exceeding the internal 10 V zener clamp. M1 PFC Drive Signal PFC Output Voltage PFC Compensation − A transconductance error amplifier regulates the PFC output voltage, Vbulk, by comparing the PFC feedback signal to an internal 2.5 V reference. As shown in Figure 8 a resistor divider from the PFC output voltage consisting of R1 and R2 generates the PFC feedback signal. PZCD Figure 6. ZCD Winding Implementation A negative voltage appears on the ZCD winding while the PFC switch is on. The PZCD voltage is positive while the PFC switch is off and current is flowing through the inductor. The PZCD voltage drops to and rings around zero volts once the inductor is demagnetized. Once a negative transition is detected in the PZCD pin the next switch cycle commences. A positive transition (corresponding to the PFC switch turn off) arms the ZCD detector to prevent false triggering. The arming of the ZCD detector is typically 2.1 V (VPZCD increasing) and the triggering is typically 1.5 V (VPZCD decreasing). The PZCD pin is internally clamped to 10 V with a zener diode. A resistor in series with the ZCD pin is required to limit the current into the PZCD pin. The zener diode prevents the voltage from exceeding the 10 V clamp or going below ground. Figure 7 shows typical ZCD waveforms. Vbulk R1 PFC Error Amplifier PFB − R2 + + Rectified ac line voltage VZCD(high) VZCD(low) 0V IPFB − + VPREF Figure 8. PFC Voltage Sensing The feedback signal is applied to the amplifier inverting input. The internal 2.5 V reference, VPREF, is applied to the amplifier non−inverting input. The reference is trimmed during manufacturing to achieve an accuracy of ±3.2%. Figure 8 shows the PFC error amplifier and sensing network. Equation 5 is used to calculate the values of the PFC feedback network. http://onsemi.com 13 NCL30051 VPFC + V PREF @ R1 ) R2 ) I PFB @ R1 R2 VPCS(ILIM). This comparison is done on a cycle by cycle basis. The overcurrent threshold is typically 0.84 V. The current sense signal is prone to leading edge spikes caused by the power switch transitions. The NCL30051 has leading edge blanking circuitry that blocks out the first 110 ns (typical) of each current pulse. (eq. 5) A transconductance amplifier has a voltage−to−current gain, gm. That is, the output current is controlled by the differential input voltage. The NCL30051 amplifier has a typical gm of 95 mS. The PControl pin provides access to the amplifier output for compensation. The compensation network is ground referenced allowing the PFC feedback signal to be used to detect an overvoltage condition. The compensation network on the PControl pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle. A capacitor between the PControl pin and ground sets a pole. A pole at or below 20 Hz is enough to filter the ripple voltage for a 50 and 60 Hz system. The low frequency pole, fp, of the system is calculated using Equation 6. fp + gm 2pC PControl PFC Driver The PFC driver source and sink impedances are typically 60 and 15 W, respectively. Depending on the external MOSFET gate charge requirements, an external driver may be needed to drive the PFC power switch. A driver such as the one shown in Figure 9 can be easily implemented using small bipolar transistors. VCC (eq. 6) where, CPControl is the capacitor on the PControl pin to ground. A key feature to using a transconductance type amplifier, is that the input is allowed to move independently with respect to the output, since the compensation capacitor is connected to ground. This allows dual usage of the feedback pin by the error amplifier and by the overvoltage comparator. xDRVx PFC Undervoltage Figure 9. External Driver To gate of MOSFET The NCL30051 safely disables the controller if the PFB pin is left open. An undervoltage detector disables the controller if the voltage on the PFB pin is below VPUVP(low), typically 0.23 V. A 1.2 mA (typical) pull down current source, IPFB, ensures VPFB falls below VPUVP(low) if the PFB pin is floating. The PFB pull down current source affects the PFC output voltage regulation setpoint. Half−Bridge Driver The half−bridge stage operates at a fixed 50% duty ratio. The oscillator frequency is divided by two before it is applied to the half−bridge controller. The half−bridge controller has a low side driver, HDRVlo, and a 600 V high side driver, HDRVhi. The built in high voltage driver eliminates the need for an external transformer or dedicated driver. A built−in delay between each drive transition eliminates the risk of cross conduction. The delay is typically 785 ns. The typical duty ratio of each half−bridge driver is 48%. The high side driver is connected between the HBoost and the HVS pins as shown in Figure 10. PFC Overvoltage An overvoltage detector monitors the PFC feedback voltage and disables the PFC driver if an overvoltage condition is detected. This is set internal to the IC at 5% above the nominal setting of the PFC voltage If an OVP event is detected, drive pulses are suppressed until the over voltage condition is removed. The overvoltage detector tolerance is better than ±2%. The overvoltage detector threshold, VPOVP, is the midpoint between the PFC driver disable and enable thresholds. The overvoltage comparator hysteresis is the voltage difference between the disable and enable thresholds. An overvoltage condition is detected once VPFB exceeds VPOVP by half of VPOVP(HYS). The controller is re-enabled once VPFB drops below VPOVP by half of VPOVP(HYS). VCC D boost HBoost HDRVhi PFC Overcurrent C boost HVS The PFC current is monitored by means of an overcurrent detector. The PCS pin provides access to the overcurrent detector. The PFC drive pulse is terminated if the voltage on the PCS pin exceeds the overcurrent threshold, Figure 10. Half−bridge High Side Driver http://onsemi.com 14 NCL30051 A boost circuit comprised of Dboost and Cboost generates the supply voltage for the high side driver. Once HDRVlo turns on, the HVS pin is effectively grounded through the external power switch. This allows Cboost to charge to VCC. Once HDRVlo turns off, HVS floats high and Dboost is reversed biased. An undervoltage detector monitors the HBoost voltage. Once the HBoost voltage is greater than VBoost(UV), typically, 6.1 V, the high side driver is enabled. The low side driver generally starts before the high side driver because the boost voltage is generated by the low side driver switch transitions. The half−bridge low side driver source and sink impedances are typically 75 and 15 W, respectively. The half−bridge high side driver source and sink impedances are typically 75 and 15 W, respectively. Depending on the external MOSFETs gate charge requirements, an external driver may be needed to drive the low and high side power switches. Analog and Power Ground The NCL30051 has an analog ground, GND, and a power ground, PGND, terminal. GND is used for analog connections such as VREF and OSC. PGND is used for high current connections such as the gate drivers. It is recommended to have independent analog and power ground planes and connect them at a single point, preferably at the ground terminal of the system. This will prevent high current flowing on PGND from injecting noise in GND. The PGND connection should be as short and wide as possible to reduce inductance−induced spikes. http://onsemi.com 15 NCL30051 PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− P 1 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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