NCP1611GEVB Evaluation Board User's Manual

NCP1611GEVB
160-W, Wide Mains, PFC
Stage Driven by the
NCP1611 Evaluation Board
User's Manual
http://onsemi.com
EVAL BOARD USER’S MANUAL
Introduction
stage is intended to deliver 160 W under a 390 V output
voltage from a wide mains input. This is a PFC boost
converter as used in Flat TVs, High Power LED Street Light
power supplies, and all-in-one computer supplies. The
evaluation board embeds the NCP1611 B-version which is
best appropriate for the self-biased configuration. The board
is also configurable to have the NCP1611 powered from an
external power source. In this case, apply a VCC voltage that
exceeds the NCP1611B start-up level (18.2 V max) to ensure
the circuit start of operation or solder the NCP1611A
instead. The A-version start-up level is lower than 11.25 V
to allow the circuit powering from a 12 V rail. Both versions
feature a large VCC operating range (from 9.5 V up to 35 V).
Housed in a SO-8 package, The NCP1611 is designed to
drive PFC boost stages in so-called Current Controlled
Frequency Fold-back (CCFF). In this mode, the circuit
classically operates in Critical conduction Mode (CrM)
when the inductor current exceeds a programmable value.
When the current is below this preset level, the NCP1611
linearly decays the frequency down to about 20 kHz when
the current is nearly zero. CCFF maximizes the efficiency
throughout the load range. Incorporating protection features
for rugged operation, it is furthermore ideal in systems
where cost-effectiveness, reliability, low stand-by power
and high-efficiency are the key requirements.
Extremely slim, the NCP1611 evaluation board is
designed to be less than 13 mm high. This low-profile PFC
Table 1. ELECTRICAL SPECIFICATIONS
Value
Units
Input Voltage Range
Description
90-265
Vrms
Line Frequency Range
45 to 66
Hz
160
W
Minimum Output Load Current(s)
0
Adc
Number of Outputs
1
Output Power
Nominal Output Voltage
390
Vdc
Maximum Startup Time
<3
s
< 250
mW
95
%
10-100
%
93
%
No-Load Power (115 Vrms)
Target Efficiency at Full Load (115 Vrms)
Load Conditions For Efficiency Measurements (10%, 20%,..)
Minimum Efficiency At 20% Load, 115 Vrms
Minimum PF Over The Line Range At Full Load
95
%
Hold-Up Time (the output voltage remaining above 300 V)
> 10
ms
Peak To Peak Low Frequency Output Ripple
<8
%
© Semiconductor Components Industries, LLC, 2012
November, 2012 − Rev. 4
1
Publication Order Number:
EVBUM2049/D
NCP1611GEVB
THE BOARD
Figure 1. A Slim Board (Height < 13 mm)
APPLICATION SCHEMATIC
Vin
U1
GBU606
C4
220nF
Type = X2
L2
200 μH (np/ns=10)
.
.
+
C5
470 nF / 400 V
IN
D2
1N5406
D1
MUR550
Rth1
B57153S150M
Vaux
−
R2
1000k
V line
R1
1000k
DRV
C1
1 nF
Type = Y2
D3
1N4148
Q1
IPA50R250
R6
22
C2
1 nF
Type = Y2
CM1
R5
2.2
R4
10k
I sense
R3
80m 3W
L1
C6a
68μF/450V
C6b
68μF/450V
GND
C3
680nF
Type = X2
D4
1N4148
F1
C7
22μF/50V
DZ2
33V
V CC
Earth
+
N
90−265 Vrms
−
L
Vbulk
Socket for
External VCC
Power Source
Figure 2. Application Schematic − Power Section
If an external VCC is applied to the board (as allowed by
the socket for external VCC power source), it must be less
than 33 V not to exceed the reverse ZENER voltage of
ZENER diode DZ2 of Figure 2.
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NCP1611GEVB
V line
Vbulk
R22
560k
R15
120k
R8
560k
Vin
R16
120k
R23
1800k
R9
1800k
V CC
R11
27k
R24
1800k
R17
120k
R10
1800k
C8
1nF
D6
1N4148
R25
1800k
1
C10
220nF
C16
470pF
R26
120k
C13
10nF
R18
27
2
7
3
6
4
Vaux
D5
1N4148
8
R7
0
R20
4.7k
5
DRV
R21
4.7k
I sense
R12
22k
C9
2.2μF
C11
470pF
R14
270k
R13
0
C15
220nF
C12
NC
DZ1
22V
C14
NC
R19
NC
GND
Figure 3. Application Schematic − Control Section
GENERAL BEHAVIOR − TYPICAL WAVEFORMS
VBULK
Line current (2 A/div)
VBULK
Line current (2 A/div)
VIN
VIN
Voltage on FF CONTROL pin
Voltage on FF CONTROL pin
a.) 115 V
a.) 230 V
Figure 4. General Waveforms at Full Load
CCFF Operation
To further optimize the efficiency, the circuit skips cycles
near the line zero crossing where the power transfer is
particularly inefficient. This is at the cost of some current
distortion. If superior power factor is needed, forcing a
minimum 0.75 V voltage on the “FFcontrol” inhibits this
function.
The NCP1611 operates in so called Current Controlled
Frequency Fold-back (CCFF) where the circuit operates in
Critical conduction Mode (CrM) when the instantaneous
line current is medium or high. When this current is lower
than a preset level, the frequency linearly decays to about 20
kHz. CCFF maximizes the efficiency at both nominal and
light loads (*). In particular, stand-by losses are minimized.
*Like in FCCrM controllers, internal circuitry allows near-unity power factor even when the switching frequency is reduced.
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NCP1611GEVB
is proportional to the difference between 2.5 V reference and
the FFcontrol voltage. This delay is maximum when the
FFcontrol voltage is 0.75 V (about 45 ms) so that a nearly
20 kHz operation is obtained. Below this 0.75 V level, the
circuit skips cycles.
Practically, the FFcontrol pin of the NCP1611 generates
a voltage representative of the instantaneous line current.
When this voltage exceeds 2.5 V, the circuit operates in CrM.
If the FFcontrol voltage is below 2.5 V, the circuit forces a
delay (or dead-time) before re-starting a DRV cycle which
Line current
VIN
Line current
Voltage on FF CONTROL pin
Voltage on FF CONTROL pin
DRV
VAUX
VAUX
a) CrM operation at the top of the sinusoid
b) Reduced frequency at a lower level of the sinusoid
Line current
VIN
Line current
VIN
Voltage on
FFCONTROL pin
Voltage on FF CONTROL pin
VAUX
VAUX
c) Low frequency near the line zero crossing
d) Skip cycle at the line zero crossing
Figure 5. CCFF operation (230 V, 0.2 A Load Current)
4. At the line zero crossing, the circuit skips cycle
when the FFcontrol pin voltage goes below 0.65 V
and resumes when the FFcontrol pin voltage
exceeds 0.75 V.
In all cases, the circuit turns on at a valley:
• Classical valley turn on in CrM operation
• At the first valley following the completion of the
dead-time generated by the CCFF function to reduce
the frequency.
Figure 5 illustrates the CCFF operation at 230 V, 200 mA
loading the PFC stage:
1. At the top of the sinusoid, the FFcontrol pin
voltage (that is representative of the line current)
exceeds 2.5 V and the circuit operates in critical
conduction mode.
2. As the input voltage decays, so do the line current
and the FFcontrol pin voltage. The FFcontrol
being lower than 2.5 V, the circuit starts to reduce
the frequency. In this figure, we can note that the
circuit nicely transitions from a 3rd valley turning
on to 4th valley turning on. This is one of the
CCFF merits, the system is “locked” on to valley n
until it needs to jump to valley (n-1) or valley
(n+1). In other words, there is no inappropriate
transitions between two valleys
3. Near the zero crossing the frequency is further
decreased
One can also note that the switching frequency being less
when the line current is low, the frequency is particularly
low at light load, high line, CrM operation being more likely
to occur at heavy load, low line. Experience shows that such
a behaviour helps optimize the efficiency in conditions.
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NCP1611GEVB
Similarly, the skipping period of time (near the line zero
crossing) visible in Figure 9 (for the particular case of the
operation at 265 V and 25% of the load):
• Is very short at low line, heavy load
• Is longer when the load diminishes and the line
magnitude
Let us remind that the skip function optimizes the efficiency
but this is at the cost of a limited current distortion. If superior
power factor is needed, forcing a minimum 0.75 V voltage on the
“FFcontrol” pin inhibits this function.
Refer to the data sheet for a detailed explanation of the
CCFF operation and of its implementation in the
NCP1611 [3].
Line current
Line current
VIN
VIN
DRV
Voltage on FF CONTROL pin
Voltage on FF CONTROL pin
a) Soft Skip Beginning
DRV
b) Soft Operation Recovery
Figure 6. The NCP1611 Enters and Leaves Skip Mode in a Soft Manner
As illustrated by Figure 8, the circuit does not abruptly
interrupt the switching when it enters skip mode. Instead, the
on-time is gradually decreased to zero in 3 to 4 switching
periods typically. Similarly, the circuit recovers operation in
a soft manner.
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NCP1611GEVB
POWER FACTOR AND EFFICIENCY
current is less compared to the input side. However, this
component still consumes some power. That is why the
efficiency is given with the NTC and with the NTC being
shorted.
The NCP1611 evaluation board embeds a NTC to limit the
in-rush current that takes place when the PFC stage is
plugged in. The NTC placed in series with the boost diode.
This location is rather optimum in term of efficiency since
it is in the in-rush current path at a place where the rms
Efficiency at 90 V
Efficiency at 115 V
Efficiency at 230 V
Efficiency at 265 V
Figure 7. Efficiency versus Load of the Evaluation Board (blue dotted line), of the Evaluation Board where
the NTC is shorted (red solid line)
Figure 7 displays the efficiency versus load at different
line levels. When considering efficiency versus load, we
generally think of the traditional bell-shaped curves:
• At low line, the efficiency peaks somewhere at a
medium load and declines at full load as a result of the
conduction losses and at light load due to the switching
losses.
• At high line, the conduction losses being less critical,
efficiency is maximal at or near the maximum load
point and decays when the power demand diminishes
because the increasing impact of the switching losses.
Curves of Figure 7 meet this behavior in the right-hand
side where our demo-board resembles a traditional CrM
PFC stage. In the left-hand side, the efficiency normally
drops because of the switching losses until an inflection
point where it rises up again as a result of the CCFF
operation. As previously detailed, CCFF makes the
switching frequency decay linearly as a function of the
instantaneous line current when it goes below a preset level.
As detailed in [1], the CCFF threshold is set to 17% of the
line maximum current. Hence, the PFC circuit switching
frequency is permanently reduced when the power is below
17% of its maximum level @ 90 V and below about 50% @
265 V. That is why the aforementioned inflection point is
around 20% of the load at low line and 50% of the load at
high line, as confirmed by the curves of Figure 8.
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NCP1611GEVB
Efficiency comparison to a traditional CrM operation.
Let’s remind that CCFF works as a function of the
instantaneous line current: when the signal representative of
the line current (generated by the FFcontrol pin) is lower
than 2.5 V, the circuit reduces the switching frequency. This
is the case near the line zero crossing whatever the load is.
Hence, the switching frequency reduces at the lowest values
of the line sinusoid even in heavy load conditions. That is
why the efficiency is also improved the load is high. This is
particularly true at high line where CCFF has more effect
than at low line since the line current is less.
3 V have been forced on the FFcontrol pin of the NCP1611
so that the circuit CCFF function is disabled. Hence, the PFC
stage operates in a traditional critical conduction mode
(CrM) in all conditions. Figure 8 compares the efficiency
with CCFF (demo-board) to that without CCFF. Otherwise
said, CCFF operation is compared to the traditional critical
mode solution.
As expected, as long as the switching frequency is not
significantly reduced by CCFF, that is above 20% load at
low line and above 50% at high line (see previous section),
the CCFF and CrM curves matches. At lighter loads, the
efficiency is much improved with CCFF.
Efficiency at 115 V
Efficiency at 230 V
Figure 8. Efficiency versus Load of the Evaluation Board (red solid line), of the Evaluation Board Operated in
Full CrM (purple dotted line). In both Cases, the NTC is Shorted.
Skip Mode
mode is inhibited by forcing a 0.75 V minimum voltage on
the FFcontrol pin. The efficiency is improved below 20 %
of the load at low line while some benefit is visible starting
from 50% of the load at 230 V.
As it will be shown, PF is slightly affected by the skip
mode function.
When the instantaneous line current tends to be very low
(below about 5% of its maximum level in our application –
refer to [1]), the circuit enters a skip cycle mode. In another
words, the circuit stops operating at a moment when the
power transfer is particularly inefficient.
This improves the efficiency in light load as shown by
Figure 10. The dotted line portrays the efficiency when skip
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NCP1611GEVB
Line Current (5 A/div)
Rectified
Input Voltage
DRV
VCONTROL
Figure 9. The Circuit Skips Cycle Near the Line Zero Crossing (265 V, 25% Load)
Efficiency at 115 V
Efficiency at 230 V
Figure 10. Efficiency versus Load of the Evaluation Board (red solid line) and of the Evaluation Board where Skip
Mode is Disabled (green dotted line). In both Cases, the NTC is Shorted.
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NCP1611GEVB
POWER FACTOR (PF) AND TOTAL HARMONIC DISTORTION (THD)
Power Factor at 115 V
Power Factor at 230 V
Figure 11. Power Factor versus Load of the Evaluation Board (red solid line), of the Evaluation Board where Skip
Mode is Disabled (green dotted line) and of the Evaluation Board Operated in CrM.
sine-wave. On the other hand, CCFF slightly degrades the
THD performance at light load. This is due to skip-mode
operation. As attested by the green curve, when skip mode
is disabled, CCFF even exhibits better THD performance
than CrM operation. One can easily play with the FFcontrol
pin to further improve the PF and THD performance in
CCFF
operation
if
needed.
Refer
to
http://www.onsemi.com/PowerSolutions/product.do?id=N
CP1611 for more information.
PF and THD performance were measured by means of a
CHROMA 66202 Digital Power Meter.
Figure 11 and Figure 12 show that CCFF exhibits very
similar PF ratios compared those obtained with CrM
traditional operation. At high line and very light load, it even
improves the PF performance thanks to the skip-mode
operation which stops operation near the line zero crossing
and hence, in return, forces more current at the top of the line
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NCP1611GEVB
THD at 115 V
THD at 230 V
Figure 12. Total Harmonic Distortion (THD) versus Load of the Evaluation Board (red solid line), of the Evaluation
Board where Skip Mode is Disabled (green dotted line) and of the Evaluation Board Operated in CrM.
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NCP1611GEVB
PROTECTION OF THE PFC STAGES
The NCP1611 protection features allow for the design of
very rugged PFC stages
Brown-out
full load. As a line drop result, the bulk voltage decreases
and the circuit responds increasing the control signal
(VCONTROL). This lasts for the 50 ms blanking time of the
brown-out function.
At the end of the 50 ms delay, a brown-out situation is
detected. VCONTROL is gradually reduced down to its
bottom clamp value (0.5 V) leading the line current to
steadily decay as well.
When VCONTROL has reached 0.5 V, the circuit stops
pulsing and grounds the VCONTROL pin to ensure a smooth
running resumption (soft-start) when the line is brought
back to level allowing operation.
An external 15 V VCC power source is applied to the
board. The load is 100 mA. The rms input voltage is
decreased with 0.1 V steps.
• (Vin,rms)BOL = 71.3 V (rms line voltage below which
the circuit stops operating)
• (Vin,rms)BOH = 78.6 V (rms line voltage above which
the circuit starts to operate)
a) shows the re-start when the input voltage exceeds the
78.6-V BOH level. The circuit smoothly recovers operation
(soft start).
b) shows the NCP1611 behaviour when the line voltage is
too low. The line is abruptly changed from 90 V to 70 V at
Line Current (2 A/div)
VBULK
Line Current (2 A/div)
VCC
VCONTROL gradual
decrease
50−ms blanking time
VBULK
VCONTROL
Vaux
VCONTROL
a) Start of operation when Vin,rms exceeds (Vin,rms)BOH
b) Abrupt line drop (90 V to 70 V)
Figure 13. Total Harmonic Distortion (THD) versus Load of the Evaluation Board (red solid line), of the Evaluation
Board where Skip Mode is Disabled (green dotted line) and of the Evaluation Board Operated in CrM.
Over−Current Protection (OCP)
In our application, the theoretical maximal line current is
500mV
1 .
that is about 3.1 A.
2 80mW
Figure 14 shows the line current when clamped. The
over-current situation was obtained @ 85 V with a 500 mA
load. A 15 V VCC power source was applied to the board.
The NCP1611 is designed to monitor the current flowing
through the power switch. A current sense resistor (R3 of
Figure 2) is inserted between the MOSFET source and
ground to generate a positive voltage proportional to the
MOSFET current (VCS). When VCS exceeds a 500 mV
internal reference, the circuit forces the driver low. A 200 ns
blanking time prevents the OCP comparator from tripping
because of the switching spikes that occur when the
MOSFET turns on.
ǒ
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NCP1611GEVB
VBULK
Line Current (5 A/div)
DRV
Figure 14. Over−Current Situation (85 V, 0.5 A Load Current)
DYNAMIC PERFORMANCE
The NCP1611 features the dynamic response enhancer
(DRE) that increases the loop gain by an order of magnitude
when the output voltage goes below 95.5% of its nominal
level. This function dramatically reduces undershoots in
case of an abrupt increase of the load demand.
As an example, Figure 15a illustrates a load step from 100
to 400 mA (2-A/ms slope) @ 115 V. One can note that as a
result of the DRE function, the control signal (VCONTROL)
steeply rises when the bulk voltage goes below 370 V,
leading to a sudden increase of the line current (in our case,
this is so sharp that the over-current protection trips to limit
the line current to about 3 A). This sharp reaction
dramatically limits the bulk voltage decay. VBULK stays
above 365 V and recovers within about 15 ms.
One can further note that the VCONTROL rapidly decrease
back to its new steady state level. This is allowed by the use
of a type-2 compensation: DRE leads to the charge of the C10
capacitor to the high VCONTROL level but C9 is partly
charged only. Our compensation reduces to nearly zero the
overshoot that can follow a fast response to an
under-voltage.
Line Current (5 A/div)
Line Current (5 A/div)
VBULK
VBULK
VCC
VCC
VCONTROL
VCONTROL
a) Load abrupt rise
b) Load abrupt decay
Figure 15. Bulk voltage variations when the load changes from 100 to 400 mA (2 A/ms slope)
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NCP1611GEVB
for a reduced acoustic noise. The circuit reduces the power
delivery by smoothly decaying the on-time to zero within
about 50 ms that is 2 to 10 switching periods according to the
conditions of a typical application. If the output voltage rise
is so fast that VBULK still significantly increases during this
braking phase, a second comparator immediately disables
the driver if the output voltage exceeds 107% of its desired
level (fast OVP).
Figure 15b shows the other transition from (400 mA to
100 mA). Again the bulk voltage deviation is very small:
VBULK remains below 410 V. This is because the soft Over
Voltage Protection (softOVP) triggers when VBULK exceeds
105% of its nominal voltage and prevents the DRV from
pulsing until VBULK has dropped down to a safe level (103%
of its nominal voltage).
Figure 16 shows a magnified view of Figure 15b. It
illustrates the gradual interruption of the drive pulses flow
Load current (0.5 A/div)
VBULK
VCONTROL
DRV
Figure 16. Soft Over−Voltage Protection
BEHAVIOR UNDER FAILURE SITUATIONS
As an example, we will illustrate here the circuit operation
when the PFC bypass diode is shorted. When the PFC stage
is plugged in, a large in-rush current takes place that charges
the bulk capacitor to the line peak voltage. Traditionally, a
bypass diode (D2 in the application schematic of Figure 2)
is placed between the input and output high-voltage rails to
divert this inrush current from the inductor and boost diode.
When it is shorted, the bulk voltage being equal to the input
voltage, the inductor slightly demagnetizes by the only
virtue of the conduction losses caused by the inductor losses
mainly within the boost diode. This is generally far
insufficient to prevent a cycle-by-cycle cumulative rise of
Elements of the PFC stage can be accidently shorted,
badly soldered or damaged as a result of manufacturing
incidents, of an excessive operating stress or of other
troubles. In particular, adjacent pins of controllers can be
shorted, a pin, grounded or badly connected. It is often
required that such open/short situations do not cause fire,
smoke nor loud noise. The NCP1611 integrates functions
that help meet this requirement, for instance, in case of an
improper pin connection (including GND) or of a short of
the boost or bypass diode. Application note AND9064
details the behavior of a NCP1611-driven PFC stage under
safety tests [2].
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NCP1611GEVB
the inductor current and an unsafe heating of the inductor,
the MOSFET and the boost diode.
Current within the “short” (5 A/div)
Current within the “short” (5 A/div)
VBULK
VBULK
DRV
DRV
Voltage across the current sense resistor
Voltage across the current sense resistor
a) General view
b) Magnified view
Figure 17. Shorting the Bypass Diode and the NTC
MOSFET turns on while the boost diode is still conducting
a large current (see Figure 17b)). Hence, the MOSFET
closing causes the second over-current comparator to trip
and an “Overstress” situation is detected. As the
consequence, no DRV pulse can take until an 800 ms delay
has elapsed. The very low duty-ratio prevents the
application from heating up.
The NCP1611 incorporates a second over-current
comparator that trips whenever the MOSFET current
happens to exceed 150% of its maximum level. Such an
event can happen when the current slope is so sharp that the
main over-current comparator cannot prevent the current
from exceeding this second level as the result of the inductor
saturation for instance. In this case, the circuit detects an
“Overstress” situation and disables the driver for an 800 ms
delay. This long delay leads to a very low duty-ratio
operation to dramatically limit the risk of overheating.
Figure 17 illustrates the operation while the bypass diode
and the NTC are both shorted @ 115 V with a 0.1 A load
current, the NCP1611 being supplied by a 15 V external
power source. Two drive pulses occur every 800 ms. The
first pulse is limited by the over-current protection. Since the
input and output voltages are equal, the inductor has not
demagnetized when the next pulse is generated and the
Please note that we do not guarantee that the a
NCP1611-driven PFC stage necessarily passes all the
safety tests and in particular the boost diode short one
since the performance can vary with respect to the
application or conditions. The reported tests are
intended to illustrate the typical behavior of the part in
one particular application, highlighting the protections
helping pass the safety tests. The reported tests were
made at 255C ambient temperature.
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NCP1611GEVB
BILL OF MATERIALS
Reference
Qty
Description
HS1
1
Heatsink
F1
1
4-A fuse
4A
250 V
C1, C2
2
Y capacitors
1 nF
C3
1
X2 capacitor
C4
1
X2 capacitor
C5
1
C6a, C6b
C7
Tolerance /
Constraints
Manufacturer
Part number
COLUMBIA-STAVER
TP207ST,120,12.5,N
A,SP,03
through-hole
Multicomp
MCPEP 4A 250V
275 V
through-hole
EPCOS
B32021A3102
680 nF
277 V
through-hole
EPCOS
B32922C3684K
220 nF
277 V
through-hole
EPCOS
B32922C3224K
Filtering
capacitor
470 nF
450 V
through-hole
EPCOS
B32592C6474K
2
Bulk
capacitor
68 mF
450 V
through-hole
Rubycon
450QXW68M12.5X40
1
Electrolytic
capacitor
22 mF
50 V
through-hole
various
various
Diodes
Bridge
GBU406
4 A, 600 V
through-hole
LITE-ON
GBU406
U1
Value
Footprint
L1
1
DM Choke
117 mH
75 mΩ
through-hole
Pulse Engineering
PH9081NL
CM1
1
Common
Mode Filter
8.5 mH
85 mΩ
through-hole
Pulse Engineering
PH9080NL
L2
1
Boost
inductor
200 mH
6 Apk
through-hole
Wurth Elektronik
750370081 (EFD30)
Q1
1
Power
MOSFET
IPA50R250
550 V
TO220
Infineon
IPA50R250CP
D1
1
Boost diode
MUR550
5 A, 520 V
Axial
ON Semiconductor
MUR550APFG
D2
1
Bypass
diode
1N5406
3 A, 600 V
Axial
ON Semiconductor
1N5406G
DZ2
1
33-V
ZENER
diode
MMSZ33T2
33 V, 0.5 W
SOD-123
ON Semiconductor
MMSZ33T2
Rth1
1
Inrush
Current
Limiter
15 Ω
1.8 Amax
through-hole
EPCOS
B57153S0150M000
D3, D4
2
Switching
diode
D1N4148
100 V
SOD123
Vishay
1N4148W-V
R1, R2
2
X2
Capacitors
discharge
resistor
1 MΩ
1%, 500V
SMD, 1206
various
various
R3
1
Current
sense
resistor
80 mΩ
1%, 3W
through-hole
Vishay
LVR03R0800FE12
R4
1
resistor
10 kΩ
10%, 1/4W
SMD, 1206
various
various
R5
1
resistor
2.2 Ω
10%, 1/4W
SMD, 1206
various
various
R6
1
resistor
22 Ω
10%, 1/4W
SMD, 1206
various
various
R7, R13
2
resistor
0Ω
1%, 1/4W
SMD, 1206
various
various
R9, R10,
R23, R24,
R25
5
resistor
1.8 MΩ
1%, 1/4W
SMD, 1206
various
various
R8, R22
2
SMD
resistor,
1206, 1/4W
560 kΩ
1%, 1/4W
SMD, 1206
various
various
http://onsemi.com
15
NCP1611GEVB
Reference
Qty
Description
Value
Tolerance /
Constraints
Footprint
Manufacturer
Part number
R11
1
resistor
27 kΩ
1%, 1/4W
SMD, 1206
various
various
R12
1
resistor
22 kΩ
1%, 1/4W
SMD, 1206
various
various
R14
1
resistor
270 kΩ
1%, 1/4W
SMD, 1206
various
various
R15, R16,
R17
3
resistor
120 kΩ
10%, 1/4W
SMD, 1206
various
various
R18
1
resistor
27 Ω
10%, 1/4W
SMD, 1206
various
various
R20, R21
2
resistor
4.7 kΩ
5%, 1/4W
SMD, 1206
various
various
R26
1
resistor
120 kΩ
1%, 1/4W
SMD, 1206
various
various
C8
1
Capacitor
1 nF
25 V, 10%
SMD, 1206
various
various
C9
1
Capacitor
2.2 F
25 V, 10%
SMD, 1206
various
various
C10, C15
2
Capacitor
220 nF
25 V, 10%
SMD, 1206
various
various
C11, C16
2
Capacitor
470 pF
25 V, 10%
SMD, 1206
various
various
C13
1
Capacitor
10 nF
100 V, 10%
SMD, 1206
various
various
D5, D6
2
Switching
diode
D1N4148
100 V
SOD123
Vishay
1N4148W-V
DZ1
1
22-V zener
diode
MMSZ22T1
22 V, 0.5 W
SOD-123
ON Semiconductor
MMSZ22T1
U2
1
PFC
Controller
NCP1611
SOIC-8
ON Semiconductor
NCP1611B
NOTE: Applications require the use of Y1 capacitors. In this case, CD12-E2GA102MYNSA from TDK or DE1E3KX102MA5B01 from
muRata may be a good option for C1 and C2.
REFERENCES
[1] Joel Turchi, “5 key steps to design a compact, high-efficiency PFC Stage Using The NCP1611”, Application note
AND9062/D, http://www.onsemi.com/pub_link/Collateral/AND9062-D.PDF.
[2] Joel Turchi, “Safety tests on a NCP1611-driven PFC stage”, Application note AND9064/D,
http://www.onsemi.com/pub_link/Collateral/AND9064-D.PDF.
[3] NCP1611 Data Sheet, http://www.onsemi.com/pub_link/Collateral/NCP1611-D.PDF
[4] NCP1611 design worksheet, http://www.onsemi.com/PowerSolutions/supportDoc.do?type=tools&rpn=NCP1611
[5] NCP1611 evaluation board documents,
http://www.onsemi.com/PowerSolutions/supportDoc.do?type=boards&rpn=NCP1611
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