ETC NCP1612

NCP1612
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Enhanced, High-Efficiency
Power Factor Controller
The NCP1612 is designed to drive PFC boost stages based on an
innovative Current Controlled Frequency Fold−back (CCFF)
method. In this mode, the circuit classically operates in Critical
conduction Mode (CrM) when the inductor current exceeds a
programmable value. When the current is below this preset level, the
NCP1612 linearly decays the frequency down to about 20 kHz when
the current is null. CCFF maximizes the efficiency at both nominal
and light load. In particular, the stand−by losses are reduced to a
minimum.
Like in FCCrM controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is reduced. Housed
in a SO−10 package, the circuit also incorporates the features
necessary for robust and compact PFC stages, with few external
components.
General Features
• Near−Unity Power Factor
• Critical Conduction Mode (CrM)
• Current Controlled Frequency Fold−back (CCFF): Low Frequency
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MARKING
DIAGRAM
10
SOIC−10
CASE 751BQ
10
1
1
TBD
A
L
Y
W
G
XXXXX
ALYWX
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
FOVP/BUV
Feedback
1
pfcOK
VCC
Operation is Forced at Low Current Levels
Vcontrol
DRV
• On−time Modulation to Maintain a Proper Current Shaping in CCFF
Vsense
GND
Mode
CS/ZCD
FFcontrol
• Skip Mode Near the Line Zero Crossing
(Top View)
• Fast Line / Load Transient Compensation (Dynamic Response
Enhancer)
ORDERING INFORMATION
• Valley Turn On
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
• High Drive Capability: −500 mA/+800 mA
• VCC Range: from 9.5 V to 35 V
• Low Start−up Consumption
• Over Current Limitation
• A Version: Low VCC Start−up Level (10.5 V),
• Disable Protection if the Feedback and FOVP/BUV
B Version: High VCC Start−up Level (17.0 V)
pins are not connected
• Line Range Detection
• Thermal Shutdown
• pfcOK Signal
• Latched Off Capability
• This is a Pb−Free Device
• Low Duty−Cycle Operation if the Bypass Diode is
shorted
Safety Features
• Open Ground Pin Fault Monitoring
• Separate Pin for Fast Over−Voltage Protection (FOVP)
and Bulk Under−Voltage Detection (BUV)
Typical Applications
• Soft Over−Voltage Protection
• PC Power Supplies
• Brown−Out Detection
• All Off Line Appliances Requiring Power Factor
Correction
• Soft−Start for Smooth Start−up Operation (A version)
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2011
July, 2011 − Rev. P0
1
Publication Order Number:
NCP1612/D
NCP1612
Figure 1. Typical Application Schematic
MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
Value
Unit
VCC
9
Power Supply Input
−0.3, + 35
V
VCC
9
Maximum (dV/dt) that can be applied to pin9
TBD upon test engineer
measurements
V/s
Vi
1, 2, 4,
5, 10
Input Voltage (Note 1)
−0.3, +9
V
Vi(pin6)
6
Input Voltage
−0.3, VCL(pos)*
V
VCONTROL
3
VCONTROL pin
−0.3, VCONTROLMAX*
V
DRV
8
Driver Voltage
Driver Current
−0.3, VDRV*
−500, +800
V
mA
PD
RqJA
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
550
145
mW
°C/W
TJ
Operating Junction Temperature Range
−40 to +125
°C
TJmax
Maximum Junction Temperature
150
°C
TSmax
Storage Temperature Range
−65 to 150
°C
TLmax
Lead Temperature (Soldering, 10s)
300
°C
MSL
Moisture Sensitivity Level
1
−
ESD Capability, Human Body Model (Note 2)
> 2000
V
ESD Capability, Machine Model (Note 2)
> 200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*“VCL(pos)“ is the pin 6 positive clamp voltage. “VCONTROLMAX” is the pin 3 clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if this
clamp voltage is below VCC. “VDRV” is VCC otherwise.
1. When the applied voltage exceeds 5 V, these pins sink about
V1 * 5 V
4 kW
that is about 1 mA if VI = 9 V
2. This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Machine Model Method 200 V per JEDEC Standard JESD22−A115−A
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise
specified) (Note NO TAG)
Rating
Min
Typ
Max
VCC(on)
Start−Up Threshold, VCC increasing:
A version
B version
9.75
15.80
10.50
17.00
11.25
18.20
VCC(off)
Minimum Operating Voltage, VCC falling
8.5
9.0
9.5
VCC(HYST)
Hysteresis (VCC (on ) − VCC (off ))
A version
B version
0.75
6.00
1.50
8.00
−
−
VCC(reset)
VCC level below which the circuit resets
3
5
7
ICC(start)
Start−Up Current, VCC = 9.4 V
A version
B version
−
−
100
30
250
75
ICC(op)1
Operating Consumption, no switching (pin 4 grounded)
−
0.25
1.00
mA
ICC(op)2
Operating Consumption, 50 kHz switching, no load on pin 8
−
2.00
3.00
mA
Symbol
Unit
START−UP AND SUPPLY CIRCUIT
V
V
V
V
mA
CURRENT CONTROLLED FREQUENCY FOLD−BACK
TDT1
Dead−Time, VFFcontrol = 2.60 V
−
−
0
ms
TDT2
Dead−Time, VFFcontrol = 1.75 V
17
20
23
ms
TDT3
Dead−Time, VFFcontrol = 1.00 V
34
40
46
ms
IDT1
Pin6 current, Vsense = 1.4 V and Vcontrol maximum
170
200
230
mA
IDT2
Pin6 current, Vsense = 2.8 V and Vcontrol maximum
110
135
160
mA
VSKIP−H
FFcontrol pin Skip Level, VFFcontrol rising
−
0.75
0.85
V
VSKIP−L
FFcontrol pin Skip Level, VFFcontrol falling
0.55
0.65
−
V
VSKIP−L
FFcontrol pin Skip Hysteresis
50
−
−
mV
TR
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
−
40
−
ns
GATE DRIVE
TF
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
−
20
−
ns
ROH
Source resistance
−
13
−
W
ROL
Sink resistance
−
6
−
W
ISOURCE
Peak source current, VDRV = 0 V (guaranteed by design)
−
500
−
mA
ISINK
Peak sink current, VDRV = 12 V (guaranteed by design)
−
800
−
mA
VDRVlow
DRV pin level at VCC close to VCC (off ) with a 10 kW resistor to GND
8.0
−
−
V
VDRVhigh
DRV pin level at VCC = 35 V (RL = 33 kW, CL = 220 pF)
10
12
14
V
VREF
Feedback Voltage Reference:
@ 25°C
Over the temperature range
TBD
2.44
2.50
2.50
TBD
2.56
REGULATION BLOCK
V
IEA
Error Amplifier Current Capability
−
±20
−
mA
GEA
Error Amplifier Gain
110
200
290
mS
VCONTROL
−VCONTROLMAX
−VCONTROLMIN
Pin 2 Voltage:
− @ VFB = 2 V
− @ VFB = 3 V
−
−
4.5
0.5
−
−
VOUTL / VREF
Ratio (VOUT Low Detect Threshold / VREF ) (guaranteed by design)
95.0
95.5
96.0
%
HOUTL / VREF
Ratio (VOUT Low Detect Hysteresis / VREF ) (guaranteed by design)
−
−
0.5
%
NOTE:
V
The above specification gives the targeted values of the parameters. The final specification will be available once the complete
circuit characterization has been performed.
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise
specified) (Note NO TAG)
Symbol
Rating
Min
Typ
Max
Unit
Pin 3 Source Current when (VOUT Low Detect) is activated
190
240
270
mA
REGULATION BLOCK
IBOOST
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
VCS(th)
Current Sense Voltage Reference
450
500
550
mV
TLEB,OCP
Over−Current Protection Leading Edge Blanking Time (guaranteed by design)
100
200
350
ns
TLEB,OVS
“OverStress” Leading Edge Blanking Time (guaranteed by design)
50
100
170
ns
TOCP
Over−Current Protection Delay from VCS/ZCD > VCS(th) to DRV low
(dVpin 6 / dt = 10 V/ms)
−
100
200
ns
VZCD(th)H
Zero Current Detection, VCS/ZCD rising
675
750
825
mV
VZCD(th)L
Zero Current Detection, VCS/ZCD falling
200
250
300
mV
VZCD(hyst)
Hysteresis of the Zero Current Detection Comparator
375
500
−
mV
RZCD/CS
VZCD(th)H over VCS(th) Ratio
1.4
1.5
1.6
−
VCL(pos)
CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA
9
10
12
V
IZCD(bias)
Pin4 Bias Current, VCS/ZCD = VZCD (th )H
0.5
−
2.0
mA
IZCD(bias)
Pin4 Bias Current, VCS/ZCD = VZCD (th )L
0.5
−
2.0
mA
TZCD
(VCS/ZCD < VZCD (th )L ) to (DRV high)
−
100
200
ns
TSYNC
Minimum ZCD Pulse Width
−
100
200
ns
TWDG
Watch Dog Timer
80
200
320
ms
TWDG(OS)
Watch Dog Timer in “OverStress” Situation
400
800
1200
ms
TTMO
Time−Out Timer
20
30
50
ms
IZCD(gnd)
Source Current for CS/ZCD pin impedance Testing
−
250
−
mA
Duty Cycle, VFB = 3 V, pin 3 open
−
−
0
%
STATIC OVP
DMIN
ON−TIME CONTROL
TON(LL)
Maximum On Time, Vsense = 1.4 V and Vcontrol maximum (CrM)
22.0
25.0
28.0
ms
TON(LL)2
On Time, Vsense = 1.4 V and Vcontrol = 2.5 V (CrM)
11.0
12.5
14.0
ms
TON(HL)
Maximum On Time, Vsense = 2.8 V and Vcontrol maximum (CrM)
7.3
8.3
9.3
ms
TON(LL)(MIN)
Minimum On Time, Vsense = 1.4 V (not tested, guaranteed by characterization)
−
−
200
ns
TON(HL)(MIN)
Minimum On Time, Vsense = 2.8 V (not tested, guaranteed by characterization)
−
−
100
ns
FEED−BACK OVER AND UNDER−VOLTAGE PROTECTION (SOFT OVP AND UVP)
RsoftOVP
Ratio (soft OVP Threshold, VFB rising) over VREF (VsoftOVP /VREF ) (guaranteed
by design)
104
105
106
%
RsoftOVP(HYST)
Ratio (Soft OVP Hysteresis) over VREF (guaranteed by design)
1.5
2.0
2.5
%
RUVP
Ratio (UVP Threshold, VFB rising) over VREF (VUVP /VREF ) (guaranteed by
design)
8
12
16
%
RUVP(HYST)
Ratio (UVP Hysteresis) over VREF (guaranteed by design)
−
−
1
%
(IB)pin2
Pin2 Bias Current @ VFB = VsoftOV P and VFB = VUVP
50
200
450
nA
FAST OVER VOLTAGE PROTECTION AND BULK UNDER−VOLTAGE PROTECTION (FAST OVP AND BUV)
VfastOVP
Latching Fast OVP Threshold, Vpin 1 rising
−
2.7
−
V
RfastOVP1
Ratio (Fast OVP Threshold, Vpin 1 rising) over (soft OVP Threshold, VFB rising)
(VfastOVP /VOVP ) (guaranteed by design)
101.5
102.0
102.5
%
NOTE:
The above specification gives the targeted values of the parameters. The final specification will be available once the complete
circuit characterization has been performed.
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NCP1612
TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, TJ from −40°C to +125°C, unless otherwise
specified) (Note NO TAG)
Symbol
Rating
Min
Typ
Max
Unit
108.5
%
FAST OVER VOLTAGE PROTECTION AND BULK UNDER−VOLTAGE PROTECTION (FAST OVP AND BUV)
RfastOVP2
Ratio (Fast OVP Threshold, Vpin 1 rising) over VREF (VFOVP /VREF )
(guaranteed by design)
105.5
107.0
VBUV
BUV Threshold, Vpin 1 falling
−
1.9
−
V
RBUV
Ratio (BUV Threshold, Vpin 1 falling) over VREF (VBUV /VREF )
(guaranteed by design)
74
76
78
%
(IB)pin1
Pin1 Bias Current @ Vpin 1 = VfastOVP and Vpin 1 = VBUV
50
200
450
nA
VUVP2
Threshold for Floating Pin Detection
0.2
0.3
0.4
V
BROWN−OUT PROTECTION AND FEED−FORWARD
VBOH
Brown−Out Threshold, Vsense rising
0.96
1.00
1.04
V
VBOL
Brown−Out Threshold, Vsense falling
0.86
0.90
0.94
V
VBO(HYST)
Brown−Out Comparator Hysteresis
75
100
−
mV
TBO(blank)
Brown−Out Blanking Time
35
50
65
ms
ICONTROL(BO)
Pin3 Sink Current, Vsense < VBOL
20
30
40
mA
VHL
High−Line Detection Comparator Threshold, Vsense rising
2.1
2.2
2.3
V
VLL
High−Line Detection Comparator Threshold, Vsense falling
1.6
1.7
1.8
V
VHL(hyst)
High−Line Detection Comparator Hysteresis
75
100
−
mV
THL(blank)
Blanking Time for Line Range Detection
15
25
35
ms
IBO(bias)
Brown−Out Pin Bias Current, Vsense = VBO
−250
−
250
nA
(VpfcOK)L
pfcOK low state voltage @ Ipin 10 = 5 mA
−
−
250
mV
(IpfcOK)cap
pfcOK pin Sink Current Capability
5
−
−
mA
VSTDWN
Shutdown Threshold Voltage
7.0
7.5
8.0
V
RpfcOK
Impedance of the pfcOK pin
150
300
−
kW
TLIMIT
Thermal Shutdown Threshold
−
150
−
°C
HTEMP
Thermal Shutdown Hysteresis
−
50
−
°C
pfcOK SIGNAL
THERMAL SHUTDOWN
NOTE:
The above specification gives the targeted values of the parameters. The final specification will be available once the complete
circuit characterization has been performed.
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NCP1612
DETAILED PIN DESCRIPTION
Pin Number
1
2
3
4
5
Name
Function
FOVP / BUV
Vpin1 is the input signal for the Fast Over−Voltage (FOVP) and Bulk Under−Voltage (BUV)
comparators. The circuit disables the driver if Vpin1 exceeds the FOVP threshold which is set
2% higher than the reference for the soft OVP comparator (that monitors the feedback pin) so
that pins 1 and 2 can receive the same portion of the output voltage.
The BUV comparator trips when Vpin 1 drops below 76% of the 2.5 V reference voltage to
disable the driver and ground the pfcOK pin. The BUV function has no action whenever the
pfcOK pin is in low state. As a matter of fact, pin1 monitors the output voltage and checks if it
is high enough for proper operation of the downstream converter.
A 250 nA sink current is built−in to ground the pin and disable the driver if the pin is
accidentally open.
Feedback
This pin receives a portion of the PFC output voltage for the regulation and the Dynamic
Response Enhancer (DRE) that drastically speeds−up the loop response when the output
voltage drops below 95.5% of the desired output level.
Vpin2 is also the input signal for the Over−Voltage (OVP) and Under−Voltage (UVP)
comparators. The UVP comparator prevents operation as long as Vpin2 is lower than 12% of
the reference voltage (VREF). A soft OVP comparator gradually reduces the duty−ratio to zero
when Vpin2 exceeds 105% of VREF (soft OVP).
A 250 A sink current is built−in to trigger the UVP protection and disable the part if the
feedback pin is accidentally open.
VCONTROL
The error amplifier output is available on this pin. The network connected between this pin and
ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high
Power Factor ratios.
Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases
slowly to provide a soft−start function.
VSENSE
A portion of the instantaneous input voltage is to be applied to pin4 in order to detect
brown−out conditions. If Vpin 4 is lower than 1 V for more than 50 ms, the circuit stops pulsing
until the pin voltage rises again and exceeds 1 V.
This pin also detects the line range. By default, the circuit operates the “low−line gain” mode. If
Vpin 4 exceeds 1.8 V, the circuit detects a high−line condition and reduces the loop gain by 3.
Conversely, if the pin voltage remains lower than 1.8 V for more than 25 ms, the low−line gain
is set.
Connecting the pin 4 to ground disables the part.
FFCONTROL
This pin sources a current representative to the line current. Connect a resistor between pin5
and ground to generate a voltage representative of the line current. When this voltage exceeds
the internal 2.5 V reference (VREF ), the circuit operates in critical conduction mode. If the pin
voltage is below 2.5 V, a dead−time is generated that approximately equates [83 ms • (1 −
(Vpin5/VREF))]. By this means, the circuit forces a longer dead−time when the current is small
and a shorter one as the current increases.
The circuit skips cycles whenever Vpin 5 is below 0.65 V to prevent the PFC stage from
operating near the line zero crossing where the power transfer is particularly inefficient. This
does result in a slightly increased distortion of the current. If superior power factor is required,
offset pin 5 by more than 0.75 V offset to inhibit the skip function.
This pin monitors the MOSFET current to limit its maximum current.
This pin is also connected to an internal comparator for Zero Current Detection (ZCD). This
comparator is designed to monitor a signal from an auxiliary winding and to detect the core
reset when this voltage drops to zero. The auxiliary winding voltage is to be applied through a
diode to avoid altering the current sense information for the on−time (see application
schematic).
6
CS / ZCD
7
Ground
8
Drive
The high−current capability of the totem pole gate drive (−0.5/+0.8 A) makes it suitable to
effectively drive high gate charge power MOSFETs.
9
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 10.5 V
(A version, 17.0 V for the B version) and turns off when VCC goes below 9.0 V (typical values).
After start−up, the operating range is 9.5 V up to 35 V.
10
pfcOK
Connect this pin to the PFC stage ground.
This pin is grounded until the PFC output has reached its nominal level. It is also grounded if
the NCP1612 detects a fault. For the rest of the time, i.e., when the PFC stage outputs the
nominal bulk voltage, pin10 is in high−impedance state.
This circuit latches off if pin10 exceeds 7.5 V.
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NCP1612
Figure 2. Block Diagram
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NCP1612
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1612 is designed to optimize the efficiency of
your PFC stage throughout the load range. In addition, it
incorporates protection features for rugged operation. More
generally, the NCP1612 is ideal in systems where
cost−effectiveness, reliability, low stand−by power and high
efficiency are the key requirements:
• Current Controlled Frequency Fold−back: the
NCP1612 is designed to drive PFC boost stages in
so−called Current Controlled Frequency Fold−back
(CCFF). In this mode, the circuit classically operates in
Critical conduction Mode (CrM) when the inductor
current exceeds a programmable value. When the
current is below this preset level, the NCP1612 linearly
reduces the frequency down to about 20 kHz when the
current is zero. CCFF maximizes the efficiency at both
nominal and light load. In particular, stand−by losses
are reduced to a minimum. Similarly to FCCrM
controllers, an internal circuitry allows near−unity
power factor even when the switching frequency is
reduced.
• Skip Mode: to further optimize the efficiency, the
circuit skips cycles near the line zero crossing when the
current is very low. This is to avoid circuit operation
when the power transfer is particularly inefficient at the
cost of current distortion. When superior power factor
is required, this function can be inhibited by offsetting
the “FFcontrol” pin by 0.75 V.
• Low Start−up Current and large VCC range (B version):
The consumption of the circuit is minimized to allow
the use of high−impedance start−up resistors to
pre−charge the VCC capacitor. Also, the minimum
value of the UVLO hysteresis is 6 V to avoid the need
for large VCC capacitors and help shorten the start−up
time without the need for too dissipative start−up
elements. The A version is preferred in applications
where the circuit is fed by an external power source
(from an auxiliary power supply or from a downstream
converter). Its maximum start−up level (11.25 V) is set
low enough so that the circuit can be powered from a
12 V rail. After start−up, the high VCC maximum rating
allows a large operating range from 9.5 V up to 35 V.
• pfcOK signal: the pfcOK pin is to disable/enable the
downstream converter. Grounded until the PFC output
has reached its nominal level and whenever the
NCP1612 detects a fault, it is in high−impedance when
the PFC stage outputs the nominal bulk voltage. In
addition, the circuit latches off if a voltage exceeding
7.5 V is applied to pin 10.
• Fast Line / Load Transient Compensation (Dynamic
Response Enhancer): since PFC stages exhibit low loop
bandwidth, abrupt changes in the load or input voltage
(e.g. at start−up) may cause excessive over or
•
•
under−shoot. This circuit limits possible deviations
from the regulation level as follows:
− The soft and fast Over Voltage Protections firmly
contains the output voltage when it tends to become
excessive.
− The NCP1612 dramatically speeds−up the regulation
loop when the output voltage goes below 95.5 % of
its regulation level. This function is enabled only
after the PFC stage has started−up not to eliminate
the soft−start effect.
Safety Protections: the NCP1612 permanently monitors
the input and output voltages, the MOSFET current and
the die temperature to protect the system from possible
over−stress making the PFC stage extremely robust and
reliable. In addition to the OVP protection, these
methods of protection are provided:
− Maximum Current Limit: the circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low duty−cycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
− Under−Voltage Protection: this circuit turns off when
it detects that the output voltage is below 12% of the
voltage reference (typically). This feature protects
the PFC stage if the ac line is too low or if there is a
failure in the feedback network (e.g., bad
connection).
− Detection of the output voltage improper level: the
“FOVP/BUV” monitors the output voltage.
Typically, the same portion of the output voltage is
applied as to the feedback pin. The circuit disables
the driver if the pin 1 voltage exceeds 102% of the
soft OVP threshold. The circuit also monitors the
output voltage to detect when the PFC stage cannot
maintain the bulk voltage at a high enough level
(BUV situation). When the BUV function trips, the
“pfcOK” pin is grounded, to disable the downstream
converter.
− Brown−Out Detection: the circuit detects low ac line
conditions and stops operation thus protecting the
PFC stage from excessive stress.
− Thermal Shutdown: an internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150°C (typically). The circuit
resumes operation once the temperature drops below
approximately 100°C (50°C hysteresis).
Output Stage Totem Pole: the NCP1612 incorporates a
−0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
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NCP1612
NCP1612 Operation Modes
− When the current is below this preset level, the
NCP1612 linearly reduces the operating frequency
down to about 20 kHz when the current is zero.
As mentioned, the NCP1612 PFC controller implements
a Current Controlled Frequency Fold−back (CCFF) where:
− The circuit operates in classical Critical conduction
Mode (CrM) when the inductor current exceeds a
programmable value.
High Current
No delay è CrM
Low Current
The next cycle is
delayed
Timer delay
Lower Current
Longer dead−time
Timer delay
Figure 3. CCFF Operation
As illustrated in Figure 3, under high load conditions, the
boost stage is operating in CrM but as the load is reduced,
the controller enters controlled frequency discontinuous
operation.
Figure 4 details the operation. A voltage representative of
the input current (“current information”) is generated. If this
signal is higher than a 2.5 V internal reference (named
“Dead−Time Ramp Threshold” in Figure 4), there is no
dead−time and the circuit operates in CrM. If the current
information is lower than the 2.5 V threshold, a dead−time
is inserted that lasts for the time necessary for the internal
ramp to reach 2.5 V from the current information floor.
Hence, the lower the current information is, the longer the
dead−time. When the current information is 0.75 V, the
dead−time is 50 ms.
To further reduce the losses, the MOSFET turns on is
stretched until its drain−source voltage is at its valley. As
illustrated in Figure 4, the ramp is synchronized to the
drain−source ringing. If the ramp exceeds the 2.5 V
threshold while the drain−source voltage is below Vin , the
ramp is extended until it oscillates above Vin so that the drive
will turn on at the next valley.
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NCP1612
Top: CrM operation when the current information exceeds the preset level during the demagnetization phase
Middle: the circuit re−starts at the next valley if the sum (ramp + current information) exceeds the preset level during the dead−time, while
the drain−source voltage is high
Bottom: the sum (ramp + current information) exceeds the preset level while during the dead−time, the drain−source voltage is low. The
circuit skips the current valley and re−starts at the following one.
Figure 4. Dead−Time generation
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NCP1612
Current Information Generation
multiplier gain (Km of Figure 5) is three times less in
high−line conditions (that is when the “”LLine” signal from
the brown−out block is in low state) so that Ipin5 provides a
voltage representative of the input current across resistor
RFF placed between pin 5 and ground. Pin 5 voltage is the
current information.
The “FFcontrol” pin sources a current that is
representative of the input current. In practice, Ipin5 is built
by multiplying the internal control signal (VREGUL , i.e., the
internal signal that controls the on−time) by the sense
voltage (pin 4) that is proportional to the input voltage. The
BO pinpin
VSENSE
IREGUL
IBO
V to I
converter
IBO
Vcontrol pin
VCONTROL
pin
LLine
Multiplier
IREGUL
V to I
converter
Km . IREGUL . IBO
IREGUL= K .VREGUL
+
FFcontrol pin
FFcontrol
pin
SUM
SUM
RAMP
RAMP
RFF
skip2
SKIP
0.75 V / 0.651V
V
pfcOK
pfcOK
Figure 5. Generation of the current information
Skip Mode
by 0.75 V. The skip mode capability is disabled whenever
the PFC stage is not in nominal operation (as dictated by the
“pfcOK” signal − see block diagram and “pfcOK Internal
Signal” Section).
The circuit does not abruptly interrupt the switching when
Vpin5 goes below 0.65 V. Instead, the signal VTON that
controls the on−time is gradually decreased by grounding
the VREGUL signal applied to the VTON processing block (see
Figure 10). Doing so, the on−time smoothly decays to zero
in 3 to 4 switching periods typically. Figure 6 shows the
practical implementation.
As illustrated in Figure 5, the circuit also skips cycles near
the line zero crossing where the current is very low. A
comparator monitors the pin 5 voltage (“FFcontrol”
voltage) and inhibits the switching operation when Vpin5 is
lower than a 0.65 V internal reference. Switching resumes
when Vpin5 exceeds 0.75 V (0.1 V hysteresis). This function
prevents circuit operation when the power transfer is
particularly inefficient at the expense of slightly increased
current distortion. When superior power factor is needed,
this function can be inhibited offsetting the “FFcontrol” pin
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NCP1612
Figure 6. CCFF Practical Implementation
CCFF maximizes the efficiency at both nominal and light
load. In particular, the stand−by losses are reduced to a
minimum. Also, this method avoids that the system stalls
between valleys. Instead, the circuit acts so that the PFC
stage transitions from the n valley to (n + 1) valley or vice
versa from the n valley to (n − 1) cleanly as illustrated by
Figure 7.
Figure 7. Clean Transition Without Hesitation Between Valleys
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NCP1612
NCP1612 On−time Modulation
One can show that the ac line current is given by:
ƪ
Let’s analyze the ac line current absorbed by the PFC
boost stage. The initial inductor current at the beginning of
each switching cycle is always zero. The coil current ramps
up when the MOSFET is on. The slope is (VIN /L) where L
is the coil inductance. At the end of the on−time (t1), the
inductor starts to demagnetize. The inductor current ramps
down until it reaches zero. The duration of this phase is (t2).
In some cases, the system enters then the dead−time (t3) that
lasts until the next clock is generated.
t 1ǒt 1 ) t 2Ǔ
I in + V in
2TL
ƫ
(eq. 1)
Where T = (t1 + t2 + t3) is the switching period and Vin is the
ac line rectified voltage.
In light of this equation, we immediately note that Iin is
proportional to Vin if [t1 (t1 + t2) / T] is a constant.
Figure 8. PFC Boost Converter (left) and Inductor Current in DCM (right)
The NCP1612 operates in voltage mode. As portrayed by
Figure 9, the MOSFET on−time t1 is controlled by the signal
Vton generated by the regulation block and an internal ramp
as follows:
t1 +
C ramp @ V ton
I ch
I in + k @ V in
where : k + constant +
T @ V REGUL
t1 ) t2
I in +
V in @ T ON(LL)
V ton @
T
@
2@L
ƫ
@ t on,max
REGUL max
V REGUL
ǒVREGULǓ max
at low line.
I in +
V in @ T ON(HL)
2@L
@
V REGUL
ǒVREGULǓ max
at high line.
From these equations, we can deduce the expression of the
average input power:
(eq. 3)
or
t1 ) t2
V REGUL
1
@
2L ǒV
Ǔ
Where ton ,max is the maximum on−time obtained when
VREGUL is at its (VREGUL )max maximum level. The
parametric table shows that ton ,max is equal to 20 ms
(TON(LL)) at low line and to 6.5 ms (TON(HL)) at high line
(when pin4 happens to exceeds 1.8 V with a pace higher than
40 Hz − see BO 25 ms blanking time).
Hence, we can re−write the above equation as follows:
(eq. 2)
The charge current is constant at a given input voltage (as
mentioned, it is three times higher at high line compared to
its value at low line). Cramp is an internal capacitor.
The output of the regulation block (VCONTROL) is linearly
transformed into a signal (VREGUL) varying between 0 and
1 V. (VREGUL) is the voltage that is injected into the PWM
section to modulate the MOSFET duty−cycle. The
NCP1612 includes some circuitry that processes (VREGUL )
to form the signal (Vton) that is used in the PWM section (see
Figure 10). (Vton) is modulated in response to the dead−time
sensed during the precedent current cycles, that is, for a
proper shaping of the ac line current. This modulation leads
to:
V ton +
ƪ
P in,avg +
+ V REGUL
Given the low regulation bandwidth of the PFC systems,
(VCONTROL ) and then (VREGUL ) are slow varying signals.
Hence, the (Vton • (t1 + t2)/T) term is substantially constant.
Provided that in addition, (t1) is proportional to (Vton ),
Equation 1 leads to: , where k is a constant. More exactly:
at low line
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ǒVin,rmsǓ
2
@ V REGUL @ T ON(LL)
2 @ L @ ǒV REGULǓ
max
NCP1612
P in,avg +
ǒVin,rmsǓ
2
functioning where (t3 = 0), which leads to (t1 + t2 = T) and
(VTON = VREGUL). That is why the NCP1612 automatically
adapts to the conditions and transitions from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
@ V REGUL @ T ON(HL)
2 @ L @ ǒV REGULǓ
max
at high line
Where (VREGUL)max is the VREGUL maximum value.
Hence, the maximum power that can be delivered by the
PFC stage is:
ǒPin,avgǓ
max
+
ǒVin,rmsǓ
2
@ T ON(LL)
2@L
at low line
ǒPin,avgǓ
max
+
ǒVin,rmsǓ
2
@ T ON(HL)
2@L
at high line
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
Figure 9. PWM circuit and timing diagram.
Figure 10. VTON Processing Circuit. The integrator OA1 amplifies the error between VREGUL and IN1 so that on
average, (VTON * (t1+t2)/T) equates VREGUL.
Remark:
phase and Vton would inappropriately over−dimension Vton
to compensate it. Instead, as illustrated in Figure 10, the Vton
signal is grounded leading to a short soft−start when the
circuit recovers.
The “Vton processing circuit” is “informed” when a
condition possibly leading to a long interruption of the drive
activity (functions generating the STOP signal that disables
the drive − see block diagram − except OCP, i.e., BUV_fault,
OVP, OverStress, SKIP, staticOVP and OFF). Otherwise,
such situations would be viewed as a normal dead−time
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NCP1612
Regulation Block and Low Output Voltage Detection
The swing of the error amplifier output is limited within
an accurate range:
− It is forced above a voltage drop (VF ) by some
circuitry.
− It is clamped not to exceed 4.0 V + the same VF
voltage drop.
Hence, Vpin3 features a 4 V voltage swing. Vpin3 is then
offset down by (VF ) and scaled down by a resistors divider
before it connects to the “VTON processing block” and the
PWM section. Finally, the output of the regulation block is
a signal (“VREGUL ” of the block diagram) that varies
between 0 and a top value corresponding to the maximum
on−time.
The VF value is 0.5 V typically.
A trans−conductance error amplifier (OTA) with access to
the inverting input and output is provided. It features a
typical trans−conductance gain of 200 mS and a maximum
capability of ±20 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and monitored
by the inverting input (pin 2). Bias current is minimized
(less than 500 nA) to allow the use of a high impedance
feed−back network. However, it is high enough so that the
pin remains in low state if the pin is not connected.
The output of the error amplifier is brought to pin 3 for
external loop compensation. Typically a type−2 network is
applied between pin 3 and ground, to set the regulation
bandwidth below about 20 Hz and to provide a decent phase
boost.
VREGUL
(VREGUL)max
VCONTROL
Figure 11. a) Regulation Block Figure (left), b) Correspondence between VCONTROL and VREGUL (right)
Given the low bandwidth of the regulation loop, abrupt
variations of the load, may result in excessive over or
under−shoots. Over−shoot is limited by the soft
Over−Voltage Protection (OVP) connected to the feedback
pin or the fast OVP of pin1.
The NCP1612 embeds a “dynamic response enhancer”
circuitry (DRE) that contains under−shoots. An internal
comparator monitors the feed−back (Vpin1) and when Vpin2
is lower than 95.5% of its nominal value, it connects a
200 mA current source to speed−up the charge of the
compensation network. Effectively this appears as a 10x
increase in the loop gain.
In A version, DRE is disabled during the start−up
sequence until the PFC stage has stabilized (that is when the
“pfcOK” signal of the block diagram, is high). The resulting
slow and gradual charge of the pin 3 voltage (VCONTROL )
softens the soft start−up sequence. In B version, DRE is
enabled during start−up to speed−up this phase and allow for
the use of smaller VCC capacitors.
The circuit also detects overshoot and immediately
reduces the power delivery when the output voltage exceeds
105% of its desired level. The NCP1612 does not abruptly
interrupt the switching. Instead, the signal VTON that
controls the on−time is gradually decreased by grounding
the VREGUL signal applied to the VTON processing block (see
Figure 10). Doing so, the on−time smoothly decays to zero
in 4 to 5 switching periods typically. If the output voltage
still increases, the fast OVP comparator immediately
disables the driver if the output voltage exceeds 108.5% of
its desired level.
The error amplifier OTA and the soft OVP, UVP and DRE
comparators share the same input information. Based on the
typical value of their parameters and if (Vout,nom) is the
output voltage nominal value (e.g., 390 V), we can deduce:
• Output Regulation Level: Vout,nom
• Output soft OVP Level: Vout,sovp = 105% x Vout,nom
• Output UVP Level: Vout,uvp = 12% x Vout,nom
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NCP1612
• Output DRE Level: Vout,dre = 95.5% x Vout,nom
− The BUV comparator trips when Vpin1 drops below
76% of the 2.5 V reference voltage (VBUV = 76% x
VREF). In the case, the circuit grounds the pfcOK
pin (to disable the downstream converter) and
gradually discharges the VCONTROL signal until the
SKIP level is obtained (see block diagram) so that
the next start−up sequence will be performed with a
soft−start. The drive output is disabled for the
VCONTROL discharge time. When the VCONTROL
discharge is complete, the circuit can attempt to
recover operation.
However, the BUV function has no action whenever the
pfcOK pin is in low state, not to inappropriately interrupt
start−up phases.
Fast OVP and Bulk Under−Voltage (BUV)
These functions check that the output voltage is within the
proper window:
− The fast Over−Voltage Protection trips if the bulk
voltage reaches abnormal levels. When the feedback
network is properly designed and correctly
connected, the bulk voltage cannot exceed the level
set by the soft OVP function (Vout,sovp = 105% x
Vout,nom, see precedent section). This second
protection offers some redundancy for a higher
safety level. The FOVP threshold is set 2% higher
than the soft OVP comparator reference so that the
same portion of the output voltage can be applied to
both the FOVP/BUV and feedback input pins (pins 1
and 2).
Figure 12. Bulk Under−Voltage Detection
As a matter of fact, pin1 monitors the output voltage and
checks if it is within the window for proper operation.
Assuming that the same portion of the output voltage is
applied to FOVP/BUV and feedback pins:
− Output fast OVP Level: Vout,fovp = 107% x Vout,nom
− Output BUV Level: Vout,BUV = 76% x Vout,nom
Hence, if the output regulation voltage is 390 V, the FOVP
and BUV output voltage levels are 417 and 296 V
respectively.
A 250 nA sink current is built−in to ground the pin if the
FOVP / BUV pin is accidently open. The circuit disables the
drive as long as the pin voltage is below 300 mV (typically).
generate a positive voltage proportional to the MOSFET
current (VCS). The VCS voltage is compared to a 500 mV
internally reference. When VCS exceeds this threshold, the
OCP signal turns high to reset the PWM latch and forces the
driver low. A 200 ns blanking time prevents the OCP
comparator from tripping because of the switching spikes
that occur when the MOSFET turns on.
The CS pin is also designed to receive a signal from an
auxiliary winding for Zero Current Detection. As illustrated
in Figure 13, an internal ZCD comparator monitors the pin6
voltage and if this voltage exceeds 750 mV, a
demagnetization phase is detected (signal ZCD is high). The
auxiliary winding voltage is applied thought a diode to
prevent this signal from distorting the current sense
information during the on−time. Thus, the OCP protection
is not impacted by the ZCD sensing circuitry. This
Current Sense and Zero Current Detection
The NCP1612 is designed to monitor the current flowing
through the power switch. A current sense resistor (Rsense)
is inserted between the MOSFET source and ground to
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NCP1612
comparator incorporates a 500 mV hysteresis and is able to
detect ZCD pulses longer than 200 ns. When pin 6 voltage
drops below the lower ZCD threshold, the driver can turn
high within 200 ns.
It may happen that the MOSFET turns on while a huge
current flows through the inductor. As an example such a
situation can occur at start−up when large in−rush currents
charge the bulk capacitor to the line peak voltage.
Traditionally, a bypass diode is generally placed between the
input and output high−voltage rails to divert this inrush
current. If this diode is accidentally shorted, the MOSFET
will also see a high current when it turns on. In both cases,
the current can be large enough to trigger the ZCD
comparator. An AND gate detects that this event occurs
while the drive signal is high. In this case, a latch is set and
the “OverStress” signal goes high and disables the driver for
a 800 ms delay. This long delay leads to a very low
duty−cycle operation in case of “OverStress” fault in order
to limit the risk of overheating.
Figure 13. Current Sense and Zero Current Detection Blocks
− Incorrect feeding of the circuit (“UVLO” high when
VCC < VCC(off), VCC(off) equating 9 V typically).
− Excessive die temperature detected by the thermal
shutdown.
− Under−Voltage Protection
− Latched−off of the part
− Regulation loop failure (UVP)
− Brown−out Situation (BO_fault high − see Figure 2)
The pfcOK signal is controlled as illustrated by Figure 14.
The circuit monitors the current sourced by the OTA. If there
is no current, we can deduce that the output voltage has
reached its nominal level. The start−up phase is then
complete and pfcOK remains high−impedance until a fault
is detected. Upon startup, the internal signals and the
internal supply rails need some time to stabilize. The
pfcOK latch cannot be set during this time and until a
sufficient blanking time has elapsed. For the sake of
simplicity, this blanking delay is not represented in
Figure 14.
Another mandatory condition to set pfcOK high is the low
state of the “BUVcomp” signal. This second necessary
condition ensures that the voltage applied to pin 1 is high
enough not to immediately trigger the BUV protection.
The pfcOK pin is to be used to enable the downstream
converter.
When no signal is received that triggers the ZCD
comparator during the off−time, an internal 200 ms
watchdog timer initiates the next drive pulse. At the end of
this delay, the circuit senses the CS/ZCD pin impedance to
detect a possible grounding of this pin and prevent
operation. The CS/ZCD external components must be
selected to avoid false fault detection. 3.9 kW is the
recommended minimum impedance to be applied to the
CS/ZCD pin when considering the NCP1612 parameters
tolerance over the −40°C to 125°C temperature range.
Practically, Rcs must be higher than 3.9 kW in the
application of Figure 13.
pfcOK Signal
The pfcOK pin is in high−impedance state when the PFC
stage operates nominally and is grounded in the following
cases:
• During the PFC stage start−up, that is, until the output
voltage has stabilized at the right level.
• If the output voltage is too low for proper operation of
the downstream converter, more specifically, when the
“BUV_fault” signal (see Figure 2) is in high state.
• In the case of a condition preventing the circuit from
operating properly like in a Brown−out situation or
when one of the following faults turns off the circuit:
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NCP1612
Figure 14. pfcOK Detection
The circuit also incorporates a comparator to a 7.5 V
threshold so that the part latches off if the pfcOK pin voltage
exceeds 7.5 V. This pin is to protect the part in case of major
fault like an over heating. To recover operation, VCC must
drop below VCC(reset).
moment, the circuit turns off (see Figure 2). This method
limits any risk of false triggering. The input of the PFC stage
has some impedance that leads to some sag of the input
voltage when the drawn current is large. If the PFC stage
stops while a high current is absorbed from the mains, the
abrupt decay of the current may make the input voltage rise
and the circuit detect a correct line level. Instead, the gradual
decrease of VCONTROL avoids a line current discontinuity
and limits risk of false triggering.
Pin4 is also used to sense the line for feed−forward. A similar
method is used:
− The VSENSE pin voltage is compared to a 2.2 V
reference.
− If Vpin4 exceeds 2.2 V, the circuit detects a high−line
condition and the loop gain is divided by three (the
internal PWM ramp slope is three times steeper)
− Once this occurs, if Vpin4 remains below 1.7 V for
25 ms, the circuit detects a low−line situation
(500 mV hysteresis).
At startup, the circuit is in low−line state (“LLine” high”)
until Vpin4 exceeds 2.2 V.
The line range detection circuit allows more optimal loop
gain control for universal (wide input mains) applications.
As portrayed in Figure 15, the pin 4 voltage is also utilized
to generate the current information required for the
frequency fold−back function.
Brown−Out Detection
The VSENSE pin (pin4) receives a portion of the
instantaneous input voltage (Vin ). As Vin is a rectified
sinusoid, the monitored signal varies between zero or a small
voltage and a peak value.
For the brown−out block, we need to ensure that the line
magnitude is high enough for operation. This is done as
follows:
− The VSENSE pin voltage is compared to a 1 V
reference.
− If Vpin4 exceeds 1 V, the input voltage is considered
sufficient
− If Vpin4 remains below 0.9 V for 50 ms, the circuit
detects a brown−out situation (100 mV hysteresis).
By default, when the circuit starts operation, the circuit is
in a fault state (“BO_NOK” high) until Vpin4 exceeds 1 V.
When “BO_NOK” is high, the drive is not disabled.
Instead, a 50 mA current source is applied to pin3 to
gradually reduce VCONTROL . As a result, the circuit only
stops pulsing when the SKIP function is activated
(VCONTROL reaches the skip detection threshold). At that
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NCP1612
Figure 15. Input Line Sense Monitoring
Thermal Shutdown (TSD)
Reference Section
An internal thermal circuitry disables the circuit gate drive
and keeps the power switch off when the junction
temperature exceeds 150°C. The output stage is then
enabled once the temperature drops below about 100°C
(50°C hysteresis).
The temperature shutdown remains active as long as the
circuit is not reset, that is, as long as VCC is higher than
VCC(RESET). The reset action forces the TSD threshold to be
the upper one (150°C), thus ensuring that any cold start−up
will be done with the proper TSD level.
The circuit features an accurate internal 2.5 V reference
voltage (VREF ) optimized to be ±2.4% accurate over the
temperature range.
OFF Mode
As previously mentioned, the circuit turns off when one
of the following faults is detected:
• Incorrect feeding of the circuit (“UVLO” high when
VCC < VCC(off), VCC(off) equating 9 V typically).
• Excessive die temperature detected by the thermal
shutdown.
• Brown−Out Fault and SKIP (see block diagram)
• Output Under−Voltage situation (Vpin1 and/or Vpin2
lower than 12% of VREF )
• Latched off produced by pulling the pfcOK pin above
7.5 V.
Generally speaking, the circuit turns off when the
conditions are not proper for desired operation. In this mode,
the controller stops operating. The major part of the circuit
sleeps and its consumption is minimized.
Output Drive Section
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. The gate drive is kept in a sinking
mode whenever the Under−Voltage Lockout is active or
more generally whenever the circuit is off (i.e., when the
“Fault Latch” of the block diagram is high). Its high current
capability (−500 mA/+800 mA) allows it to effectively
drive high gate charge power MOSFET. As the circuit
exhibits a large VCC range (up to 35 V), the drive pin voltage
is clamped not to provide the MOSFET gate with more than
14 V.
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NCP1612
• Fault of the GND connection
More Specifically, When the Circuit is in OFF State:
• The drive output is kept low
• All the blocks are off except:
•
•
•
− The UVLO circuitry that keeps monitoring the VCC
voltage and controlling the start−up current source
accordingly.
− The TSD (thermal shutdown)
− The Under−Voltage Protection (“UVP”).
− The latch off circuit
− The brown−out circuitry
VCONTROL is grounded. This ensures that when the
fault is removed, the device starts−up under the
soft−start mode.
The “pfcOK” signal is grounded.
The output of the “VTON processing block” is grounded
•
Failure Detection
When manufacturing a power supply, elements can be
accidentally shorted or improperly soldered. Such failures
can also happen to occur later on because of the components
fatigue or excessive stress, soldering defaults or external
interactions. In particular, adjacent pins of controllers can be
shorted, a pin can be grounded or badly connected. Such
open/short situations are generally required not to cause fire,
smoke nor big noise. The NCP1612 integrates functions that
ease meeting this requirement. Among them, we can list:
• Floating feedback pins
A 250 nA sink current source pulls down the voltage on
the feedback and FOVP/BUV pin so that the UVP
protection trips and prevents the circuit from operating
if one of this pin is floating. This current source is
small (450 nA maximum) so that its impact on the
output regulation and OVP levels remain negligible
with the resistor dividers typically used to sense the
bulk voltage.
•
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the VCC
capacitor, flows out of the GND pin to return to the
negative terminal of the VCC capacitor. If the GND pin
is not connected, the circuit ESD diodes offer another
return path. The accidental non connection of the GND
pin can hence be detected by detecting that one of this
ESD diode is conducting. Practically, the CS/ZCD ESD
diode is monitored. If such a fault is detected for
200 ms, the circuit stops operating.
Detection the CS/ZCD pin improper connection
The CS/ZCD pin sources a 1 mA current to pull up the
pin voltage and hence disable the part if the pin is
floating. If the CS/ZCD pin is grounded, the circuit
cannot monitor the ZCD signal and the 200 ms
watchdog timer is activated. When the watchdog time
has elapsed, the circuit sources a 250 mA current source
to pull−up the CS/ZCD pin voltage. No drive pulse is
initiated until the CS/ZCD pin voltage exceeds the ZCD
0.75 V threshold. Hence, if the pin is grounded, the
circuit stops operating. Circuit operation requires the
pin impedance to be 3.9 kW or more, the tolerance of
the NCP1612 impedance testing function being
considered over the −40°C to 125°C temperature range.
Boost or bypass diode short
The NCP1612 addresses the short situations of the
boost and bypass diodes (a bypass diode is generally
placed between the input and output high−voltage rails
to divert this inrush current). Practically, the overstress
protection is implemented to detect such conditions and
forces a low duty−cycle operation until the fault is
gone.
Refer to application note ANDxxxx for more details.
ORDERING INFORMATION
Device
NCP1612
Package
Shipping†
SOIC−10
(Pb−Free)
TBD / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP1612
PACKAGE DIMENSIONS
SOIC−10 NB
CASE 751BQ−01
ISSUE A
2X
0.10 C A-B
D
D
A
2X
F
0.10 C A-B
10
6
H
E
1
5
0.20 C
10X
B
2X 5 TIPS
L2
b
0.25
A3
L
C
DETAIL A
M
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
C A-B D
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
TOP VIEW
10X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
SIDE VIEW
DETAIL A
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
1.00
PITCH
10X 0.58
6.50
10X 1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NCP1612/D
NCP1612GEVB
160-W, Wide Mains, PFC
Stage Driven by the
NCP1612 Evaluation Board
User's Manual
http://onsemi.com
EVAL BOARD USER’S MANUAL
Introduction
stage is intended to deliver 160 W under a 390 V output
voltage from a wide mains input. This is a PFC boost
converter as used in Flat TVs, High Power LED Street Light
power supplies, and all-in-one computer supplies. The demo
board embeds the NCP1612 B-version which is best
appropriate for the self-biased configuration. The board is
also configurable to have the NCP1612 powered from an
external power source. In this case, apply a VCC voltage that
exceeds the NCP1612B start-up level (18.2 V max) to
ensure the circuit start of operation or solder the NCP1612A
instead. The low VCC start-up level of the A-version
(11.25 V max.) allows the circuit powering from a 12-V rail.
Both versions feature a large VCC operating range (from
9.5 V up to 35 V).
Housed in a SO-10 package, The NCP1612 is designed to
drive PFC boost stages in so-called Current Controlled
Frequency Fold-back (CCFF). In this mode, the circuit
classically operates in Critical conduction Mode (CrM)
when the inductor current exceeds a programmable value.
When the current is below this preset level, the NCP1612
linearly decays the frequency down to about 20 kHz when
the current is nearly zero. CCFF maximizes the efficiency
throughout the load range. Incorporating protection features
for rugged operation, it is furthermore ideal in systems
where cost-effectiveness, reliability, low stand-by power
and high-efficiency are the key requirements.
Extremely slim, the NCP1612 evaluation board is
designed to be less than 13-mm high. This low-profile PFC
Table 1. ELECTRICAL SPECIFICATIONS
Value
Units
Input Voltage Range
Description
90-265
Vrms
Line Frequency Range
45 to 66
Hz
160
W
Minimum Output Load Current(s)
0
Adc
Number of Outputs
1
Output Power
Nominal Output Voltage
390
Vdc
Maximum Startup Time
<3
s
Target Efficiency at Full Load (115 Vrms)
95
%
10-100
%
Minimum Efficiency At 20% Load, 115 Vrms
93
%
Minimum PF Over The Line Range At Full Load
95
%
Hold-Up Time (the output voltage remaining above 300 V)
> 10
ms
Peak To Peak Low Frequency Output Ripple
<8
%
Load Conditions For Efficiency Measurements (10%, 20%,..)
© Semiconductor Components Industries, LLC, 2011
January, 2012 − Rev. 0
1
Publication Order Number:
EVBUM2051/D
NCP1612GEVB
THE BOARD
Figure 1. A Slim Board (Height < 13 mm)
APPLICATION SCHEMATIC
Vin
U1
GBU606
C4
220nF
Type = X2
D2
1N5406
L2
200 μH (np/ns=10)
.
.
+
C5
470 nF / 400 V
IN
D1
MUR550
Rth1
B57153S150M
Vaux
−
R2
1000k
V line
R1
1000k
R6
22
C1
1 nF
Type = Y2
C2
1 nF
Type = Y2
CM1
DRV
D3
1N4148
R5
2.2
Q1
IPA50R250
Q2
MMBT589LT1G
R4
10k
I sense
R3
80m 3W
L1
150mH
C6a
68μF/450V
C6b
68μF/450V
GND
C3
680nF
Type = X2
D4
1N4148
F1
C7
22μF/50V
DZ2
33V
V CC
Earth
+
N
90−265 Vrms
−
L
Vbulk
Socket for
External VCC
Power Source
Figure 2. Application Schematic − Power Section
case, unplug the PFC stage to recover operation. In all
events, do not apply more than 33 V to the VCC socket not
to exceed the DZ2 reverse ZENER voltage (see Figure 2).
If an external VCC voltage is applied to the board (as
allowed by the socket for external VCC power sourcing),
it should be noted that the NCP1612 latches off if this
voltage exceeds about 30 V (see pfcOK section). In this
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NCP1612GEVB
V line
Vbulk
R8
560k
R29
1800k
R22
560k
R9
1800k
R30
27k
R11
27k
R32
120k
D6
1N4148
pfcOK
C8
1nF
R12
27k
C16
470pF
R17
120k
C10
220nF
1
10
2
9
3
8
4
7
5
6
C11
220nF
R14
270k
C9
2.2μF
R16
120k
R15
120k
V in
V CC
BUV
R10
1800k
R25
1800k
R26
120k
R27
560k
C17
1nF
R23
1800k
R24
1800k
R28
1800k
R13
120k
C13
10nF
D5
1N4148
R18
27
V aux
R20
4.7k
R7
0
R21
4.7k
C18
10nF
R33
39k
DRV
I sense
DZ1
22V
C15
220nF
GND
Figure 3. Application Schematic − Control Section
GENERAL BEHAVIOR − TYPICAL WAVEFORMS
VBULK
VBULK
Line current (2 A/div)
VIN
Line current (2 A/div)
VIN
Voltage on FF CONTROL pin
Voltage on FF CONTROL pin
a.) 115 V
b.) 230 V
Figure 4. General Waveforms at Full Load
CCFF OPERATION
minimum 0.75 V voltage on the “FFcontrol” inhibits this
function.
Practically, the FFcontrol pin of the NCP1612 generates
a voltage representative of the instantaneous line current.
When this voltage exceeds 2.5 V, the circuit operates in CrM.
If the FFcontrol voltage is below 2.5 V, the circuit forces a
delay (or dead-time) before re-starting a DRV cycle which
is proportional to the difference between 2.5 V reference and
the FFcontrol voltage. This delay is maximum when the
FFcontrol voltage is 0.75 V (about 45 ms) so that a nearly
20 kHz operation is obtained. Below this 0.75 V level, the
circuit skips cycles.
The NCP1612 operates in so called Current Controlled
Frequency Fold-back (CCFF) where the circuit operates in
Critical conduction Mode (CrM) when the instantaneous
line current is medium or high. When this current is lower
than a preset level, the frequency linearly decays to about
20 kHz. CCFF maximizes the efficiency at both nominal
and light loads (*). In particular, stand-by losses are
minimized.
To further optimize the efficiency, the circuit skips cycles
near the line zero crossing where the power transfer is
particularly inefficient. This is at the cost of some current
distortion. If superior power factor is needed, forcing a
*Like in FCCrM controllers, internal circuitry allows near-unity power factor even when the switching frequency is reduced.
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NCP1612GEVB
Voltage on FF CONTROL pin
Line current
Line current
DRV
DRV
Voltage on FF CONTROL pin
VDS
VDS
a) CrM operation at the top of the sinusoid
b) Reduced frequency at a lower level of the sinusoid
Line current
DRV
Voltage on FF CONTROL pin
VDS
c) Low frequency near the line zero crossing
Figure 5. CCFF Operation (230 V, 0.2 A Load Current)
Figure 5 illustrates the CCFF operation at 230 V, 200 mA
loading the PFC stage:
1. At the top of the sinusoid, the FFcontrol pin
voltage (that is representative of the line current)
exceeds 2.5 V and the circuit operates in critical
conduction mode (see Figure 5a).
2. As the input voltage decays, so do the line current
and the FFcontrol pin voltage. The FFcontrol
being lower than 2.5 V, the circuit starts to reduce
the frequency. (see Figure 5b).
3. Near the zero crossing the frequency is further
decreased (see Figure 5c).
In all cases, the circuit turns on at a valley:
• At the first valley as classically done in CrM operation
• Or at the first valley following the completion of the
dead-time generated by the CCFF function to reduce
the frequency.
• The circuit nicely stays “locked” on to valley n until it
needs to jump to either valley (n-1) or valley (n+1). In
other words, there is no inappropriate transition
between two valleys
One can also note that the switching frequency being less
when the line current is low, the frequency is particularly
low at light load, high line, CrM operation being more likely
to occur at heavy load, low line. Experience shows that this
behavior helps optimize the efficiency in all conditions.
Similarly, the skipping period of time (near the line zero
crossing) visible in Figure 9 (for the particular case of the
operation at 265 V and 20% of the load):
• Is nonexistent or very short at low line, heavy load
• Is longer when the load diminishes and the line
magnitude
Let us remind that the skip function optimizes the
efficiency but this is at the cost of a limited current
distortion. If superior power factor is needed, forcing a
minimum 0.75 V voltage on the “FFcontrol” pin inhibits this
function.
Refer to the data sheet for a detailed explanation of the
CCFF operation and of its implementation in the NCP1612
[3].
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NCP1612GEVB
Line current
Line current
VIN
VIN
DRV
Voltage on FF CONTROL pin
DRV
Voltage on FF CONTROL pin
a) Soft Skip Beginning
b) Soft Operation Recovery
Figure 6. The NCP1612 Enters and Leaves Skip Mode in a Soft Manner
As illustrated by Figure 6, the circuit does not abruptly
interrupt the switching when it enters skip mode. Instead, the
on-time is gradually decreased to zero in 3 to 4 switching
periods typically. Similarly, the circuit recovers operation in
a soft manner.
NO LOAD LOSSES
ǒ
The input power is measured no load being connected. An external 15-V VCC is applied.
Resistors R15, R16 and R17 of Figure 3 that are implemented to charge the VCC capacitor at start-up, draw a large bias current
V in*V cc
from the input voltage. They are disconnected for this test.
R 15)R 16)R 17
In these conditions, we measured:
Ǔ
115 V (60 Hz)
230 V (50 Hz)
Input power
92 mW
118 mW
ICC
2.0 mA
1.9 mA
The VCC consumption is almost constant over the VCC range (e.g., 2.2 mA at 30 V, low line).
It must be noted that the input power mainly results from static losses:
• Discharge resistors for X2 capacitors (R1 and R2 of Figure 2) consume
•
ǒ
2
V line,rms
R 1)R 2
Ǔ
that is about 7 mW at 115 V and
26 mW at 230 V.
Two resistors sensing networks are implemented to sense the bulk voltage (redundant bulk voltage monitoring). At both
line voltages, they consume
ǒ
2
2
V bulk
V bulk
)
R 8)R 9)R 10)R 11
R 22)R 23)R 24)R 25
Ǔ
that is about 72 mW. These losses can be
easily reduced if needed by using one single resistors divider for pins 1 and 2 and/or by increasing the impedance of the
sensing networks.
used in accumulation mode (W.h measurement over
6 minutes, the result being multiplied by 10 to obtain the
averaged power).
These static losses cost 79 mW at low line and 98 mW at
high line. As a matter of fact, the losses linked to the PFC
stage operation are very small.
The measurements were made at 25°C ambient
temperature by means of a power meter CHROMA 66202
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NCP1612GEVB
POWER FACTOR AND EFFICIENCY
current is less compared to the input side. However, this
component still consumes some power. That is why the
efficiency is given with the NTC and with the NTC being
shorted.
The NCP1612 evaluation board embeds a NTC to limit
the in-rush current that takes place when the PFC stage is
plugged in. The NTC placed in series with the boost diode.
This location is rather optimum in term of efficiency since
it is in the in-rush current path at a place where the rms
Efficiency at 90 V
Efficiency at 115 V
Efficiency at 230 V
Efficiency at 265 V
Figure 7. Efficiency versus Load of the Evaluation Board (blue dotted line), of the Evaluation Board where
the NTC is shorted (red solid line)
Figure 7 displays the efficiency versus load at different
line levels. When considering efficiency versus load, we
generally think of the traditional bell-shaped curves:
• At low line, the efficiency peaks somewhere at a
medium load and declines at full load as a result of the
conduction losses and at light load due to the switching
losses.
• At high line, the conduction losses being less critical,
efficiency is maximal at or near the maximum load
point and decays when the power demand diminishes
due to the increasing impact of the switching losses.
Curves of Figure 7 meet this behavior in the right-hand
side where our demo-board resembles a traditional CrM
PFC stage. In the left-hand side, the efficiency normally
drops because of the switching losses until an inflection
point where it rises up again as a result of the CCFF
operation. As previously detailed, CCFF makes the
switching frequency decay linearly as a function of the
instantaneous line current when it goes below a preset level.
As detailed in [1], the CCFF threshold is set to 17% of the
line maximum current. Hence, the PFC circuit switching
frequency is permanently reduced when the power is below
17% of its maximum level at 90 V and below about 50% at
265 V. That is why the aforementioned inflection point is
around 20% of the load at low line and 50% of the load at
high line, as confirmed by the curves of Figure 8.
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NCP1612GEVB
Efficiency comparison to a traditional CrM operation.
Let’s remind that CCFF works as a function of the
instantaneous line current: when the signal representative of
the line current (generated by the FFcontrol pin) is lower
than 2.5 V, the circuit reduces the switching frequency. This
is the case near the line zero crossing whatever the load is.
Hence, the switching frequency reduces at the lowest values
of the line sinusoid even in heavy load conditions. That is
why the efficiency is also improved when the load is high.
This is particularly true at high line where CCFF has more
effect than at low line since the line current is less.
3 V have been forced on the FFcontrol pin of the NCP1612
so that the circuit CCFF function is disabled. Hence, the PFC
stage operates in a traditional critical conduction mode
(CrM) in all conditions. Figure 8 compares the efficiency
with CCFF (evaluation board) to that without CCFF.
Otherwise said, CCFF operation is compared to the
traditional critical mode solution.
As expected, as long as the switching frequency is not
significantly reduced by CCFF, that is above 20% load at
low line and above 50% at high line (see previous section),
the CCFF and CrM curves matches. At lighter loads, the
efficiency is much improved with CCFF.
Efficiency at 115 V
Efficiency at 230 V
Figure 8. Efficiency versus Load of the Evaluation Board (red solid line), of the Evaluation Board Operated in
Full CrM (purple dotted line). In both Cases, the NTC is Shorted.
Skip Mode
mode is inhibited by forcing a 0.75 V minimum voltage on
the FFcontrol pin. The efficiency is improved below 20 %
of the load at low line while some benefit is visible starting
from 50% of the load at 230 V.
When the instantaneous line current tends to be very low
(below about 5% of its maximum level in our application –
refer to [1]), the circuit enters a skip cycle mode. In another
words, the circuit stops operating at a moment when the
power transfer is particularly inefficient.
This improves the efficiency in light load as shown by
Figure 10. The dotted line portrays the efficiency when skip
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NCP1612GEVB
Line Current (2 A/div)
DRV
VDS
FFCONTROL
Figure 9. The Circuit Skips Cycle Near the Line Zero Crossing (265 V, 20% Load)
Efficiency at 115 V
Efficiency at 230 V
Figure 10. Efficiency versus Load of the Evaluation Board (red solid line) and of the Evaluation Board where Skip
Mode is Disabled (green dotted line). In both Cases, the NTC is Shorted.
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NCP1612GEVB
POWER FACTOR (PF) AND TOTAL HARMONIC DISTORTION (THD)
115 V / 60 Hz and 230 V / 50 Hz being applied to the board
and at two power levels: full load and 20% of max. load (that
could be considered as a worst case of this type of
application).
Figure 11 (Figure 12) reports the NCP1612 board
performance with respect to the IEC61000-3-2 class C (class
D) standards requirements. These results were obtained by
means of a CHROMA 66202 Digital Power Meter. They
were measured at low and high line, i.e., with respectively,
115 V / 60 Hz, full load
115 V / 60 Hz, 20% load
230 V / 50 Hz, full load
230 V / 50 Hz, 20% load
Figure 11. Performance with respect to IEC61000−3−2 Class C Requirements
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NCP1612GEVB
115 V / 60 Hz, full load
115 V / 60 Hz, 20% load
230 V / 50 Hz, full load
230 V / 50 Hz, 20% load
Figure 12. Performance with respect to IEC61000−3−2 Class D Requirements
closed to the limit. We could check that inhibiting the skip
mode (forcing a 0.75 V minimum voltage on the FFcontrol)
significantly increases the headroom.
In the light of Figure 11 and Figure 12, we can see that the
NCP1612 board easily passes the standard requirements in
the considered conditions. The least margin is observed at
230 V, 20% of the load for class C for which harmonic 11 is
PROTECTION OF THE PFC STAGE
The NCP1612 protection features allow for the design of very rugged PFC stages
Brown-out
• (Vin,rms)BOH = 78.6 V (rms line voltage above which
An external 15-V VCC power source is applied to the
board. The load is 100 mA. The rms input voltage is
decreased with 0.1 V steps.
• (Vin,rms)BOL = 71.3 V (rms line voltage below which
the circuit stops operating)
the circuit starts to operate)
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NCP1612GEVB
Line Current (2 A/div)
V BULK
V CC
V CONTROL
a) Start of operation when Vin,rms exceeds (Vin,rms)BOH
(NCP1612B)
Line Current (2 A/div)
V BULK
Line Current (2 A/div)
V CONTROL gradual
decrease
V CC
50-ms blanking time
V BULK
V CONTROL
V aux
V CONTROL
b) Start of operation when Vin,rms exceeds (Vin,rms)BOH
(NCP1612A)
c) Abrupt line drop (90 V to 70 V)
Figure 13. Brown−Out Operation
the circuit increases the control signal (VCONTROL). This
lasts for the 50 ms blanking time of the brown-out function.
At the end of the 50 ms delay, a brown-out situation is
detected. VCONTROL is gradually reduced down to its
bottom clamp value (0.5 V) leading the line current to
steadily decay as well. When VCONTROL has reached 0.5 V,
the circuit stops pulsing and grounds the VCONTROL pin to
ensure a clean resumption (including soft-start with the
NCP1612 A version) when the line is brought back to a level
allowing operation.
Figure 13a shows the re-start when the input voltage
exceeds the 78.6 V BOH level with the NCP1612B. The
circuit sharply restarts for a minimized recovery time
Figure 13b shows the same when the NCP1612A is used
instead of the NCP1612B. In this case, the circuit smoothly
recovers operation (soft start).
Figure 13c shows the NCP1612 behavior when the line
voltage becomes too low (NCP1612A or NCP1612B). The
line is abruptly changed from 90 V to 70 V at full load. As
a line drop result, the bulk voltage decreases and in response,
Over−Current Protection (OPC)
In our application, the theoretical maximal line current is
1 500mV that is about 3.1 A.
2
80mW
Figure 14 shows the line current when clamped. The
over-current situation was obtained at 85 V with a 500 mA
load. A 15-V VCC power source was applied to the board.
The NCP1612 is designed to monitor the current flowing
through the power switch. A current sense resistor (R3 of
Figure 2) is inserted between the MOSFET source and
ground to generate a positive voltage proportional to the
MOSFET current (VCS). When VCS exceeds a 500 mV
internal reference, the circuit forces the driver low. A 200 ns
blanking time prevents the OCP comparator from tripping
because of the switching spikes that occur when the
MOSFET turns on.
ǒ
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11
Ǔ
NCP1612GEVB
VBULK
Line Current (5 A/div)
DRV
Figure 14. Over−Current Situation (85 V, 0.5 A Load Current)
DYNAMIC PERFORMANCE
The NCP1605 features the dynamic response enhancer
(DRE) that increases the loop gain by an order of magnitude
when the output voltage goes below 95.5% of its nominal
level. This function dramatically reduces undershoots in
case of an abrupt increase of the load demand.
As an example, Figure 15a illustrates a load step from 100
to 400 mA (2-A/ms slope) at 115 V. One can note that as a
result of the DRE function, the control signal (VCONTROL)
steeply rises when the bulk voltage goes below 370 V,
leading to a sudden increase of the line current (in our case,
this is so sharp that the over-current protection trips to limit
the line current to about 3 A). This sharp reaction
dramatically limits the bulk voltage decay. VBULK stays
above 365 V and recovers within about 15 ms.
One can further note that the VCONTROL rapidly decreases
back to its new steady state level. This is allowed by the use
of a type-2 compensation: DRE leads to the charge of the C10
capacitor to the high VCONTROL level but C9 is partly
charged only. Our compensation reduces to nearly zero the
overshoot that can follow the fast response to an
under-voltage.
Line Current (5 A/div)
Line Current (5 A/div)
VBULK
VBULK
VCC
VCC
VCONTROL
VCONTROL
a) Load abrupt rise
b) Load abrupt decay
Figure 15. Bulk Voltage Variations when the Load Changes from 100 to 400 mA (2 A/ms slope)
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NCP1612GEVB
about 50 ms that is 2 to 10 switching periods according to the
conditions of a typical application. If the output voltage rise
is so fast that VBULK still significantly increases during this
braking phase, the fast OVP protection (FOVP)
immediately disables the driver when the pin1 voltage
exceeds 107% of the 2.5 V voltage reference. In other words,
if as generally done, pin1 and the feedback pin receive the
same portion of the bulk voltage, the FOVP comparator
triggers when the bulk voltage is 107% above the regulation
level.
Figure 15b shows the other transition from 400 mA to
100 mA. Again the bulk voltage deviation is very small:
VBULK remains below 410 V. This is because the soft Over
Voltage Protection (softOVP) triggers when VBULK exceeds
105% of its nominal voltage and prevents the DRV from
pulsing until VBULK has dropped down to a safe level (103%
of its nominal voltage).
Figure 16 shows a magnified view of Figure 15b. It
illustrates the gradual interruption of the drive pulses flow
for a reduced acoustic noise. The circuit reduces the power
delivery by smoothly decaying the on-time to zero within
Load current (0.5 A/div)
VBULK
VCONTROL
DRV
Figure 16. Soft Over−Voltage Protection
pfcOK FUNCTION
pfcOK pin of the NCP1612 has been designed with the goal
of controlling the downstream converter operation:
• The pfcOK pin is grounded when the downstream
converter should be disabled
• The pfcOK pin is in high-impedance state otherwise.
That is why a portion of VCC is generally applied to
this pin to fix the high-state level. In our application,
the portion of VCC is controlled by resistors R32 and R33
of Figure 3.
The NCP1612 is particularly interesting in applications
where the downstream converter is of the forward or
half-bridge type, i.e., a converter that takes advantage of a
narrow input voltage range. As aforementioned, both the
dynamic response enhancer and the soft OVP are of great
help in this case by drastically minimizing the bulk voltage
deviation under line/load changes. In addition, an optimum
sequencing for this application type consists of having the
PFC stage started first, the downstream converter entering
operation afterwards when the bulk voltage is nominal. The
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NCP1612GEVB
If the pfcOK pin is pulled up above 7.5 V, the NCP1612
latches off until a brown-out situation is detected or VCC is
dropped below its reset level (5 V typically).
Typically, the pfcOK pin drives the feedback pin of the
downstream converter controller or its brown-out pin when
available.
It is recommended to protect the pfcOK pin from
surrounding noise. This is the goal of C18 of Figure 3.
In our application, the VCC latched-off level is:
R 33)R 32
R 33
7.5V ^ 30.6V
level (5 V typically). Figure 17b shows operation recovery.
A 80 ms mains interruption was produced to trigger the
brown-out protection (VCC having been previously
decreased below 30 V, that is, below the level leading the
part to latch off). The pfcOK signal turns high back when
the bulk voltage has reached its regulation level.
Figure 17a shows the circuit latching off. An external VCC
power source was applied and VCC was externally raised
until the pfcOK signal exceeds 7.5 V. As a consequence, the
NCP1612 stops operating (no drive pulse) and pfcOK pin
voltage is grounded.
No operation recovery is possible until either a brown-out
condition is detected or VCC is decreased below the reset
V CC
Line current (5 A/div)
V BULK
7.5V + 39k)120k
39k
Line current (5 A/div)
V CC
V BULK
pfcOK
pfcOK
a) pfcOK being pulled−up above 7.5 V, the part latches off
b) the part recovers operation as a result of a mains
interruption
Figure 17. NCP1612 Latch−Off Function
BEHAVIOR UNDER FAILURE SITUATIONS
is plugged in, a large in-rush current takes place that charges
the bulk capacitor to the line peak voltage. Traditionally, a
bypass diode (D2 in the application schematic of Figure 2)
is placed between the input and output high-voltage rails to
divert this inrush current from the inductor and boost diode.
When it is shorted, the bulk voltage being equal to the input
voltage, the inductor cannot demagnetize but only by virtue
of the inductor and boost diode conduction losses. This is
generally far insufficient to prevent a cycle-by-cycle
cumulative rise of the inductor current and an unsafe heating
of the inductor, of the MOSFET and of the boost diode.
Elements of the PFC stage can be accidently shorted,
badly soldered or damaged as a result of manufacturing
incidents, of an excessive operating stress or of other
troubles. In particular, adjacent pins of controllers can be
shorted, a pin, grounded or badly connected. It is often
required that such open/short situations do not cause fire,
smoke nor loud noise. The NCP1612 integrates functions
that help meet this requirement, for instance, in case of an
improper pin connection (including GND) or of a short of
the boost or bypass diode. Application note AND9064
details the behavior of a NCP1612-driven PFC stage under
safety tests [2].
As an example, we will illustrate here the circuit operation
when the PFC bypass diode is shorted. When the PFC stage
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14
NCP1612GEVB
Current within the “short” (5 A/div)
Current within the “short” (5 A/div)
VBULK
VBULK
DRV
DRV
Voltage across the current sense resistor
Voltage across the current sense resistor
a) General view
b) Magnified view
Figure 18. Shorting the Bypass Diode and the NTC
MOSFET turns on while the boost diode is still conducting
a large current (see Figure 18b). Hence, the MOSFET
closing causes the second over-current comparator to trip
and an “overstress” situation is detected. As the
consequence, no DRV pulse can occur until an 800 ms delay
has elapsed. The very low duty-ratio operation prevents the
application from heating up.
The NCP1612 incorporates a second over-current
comparator that trips whenever the MOSFET current
happens to exceed 150% of its maximum level. Such an
event can happen when the current slope is so sharp that the
main over-current comparator cannot prevent the current
from exceeding this second level as the result of the inductor
saturation for instance. In this case, the circuit detects an
“overstress” situation and disables the driver for an 800 ms
delay. This long delay leads to a very low duty-ratio
operation to dramatically limit the risk of overheating.
Figure 18 illustrates the operation while the bypass diode
and the NTC are both shorted at 115 V with a 0.1 A load
current, the NCP1612 being supplied by a 15 V external
power source. Two drive pulses occur every 800 ms. The
first pulse is limited by the over-current protection. Since the
input and output voltages are equal, the inductor has not
demagnetized when the next pulse is generated and the
Please note that we do not guarantee that a
NCP1612-driven PFC stage necessarily passes all the
safety tests and in particular the bypass diode short one
since the performance can vary with respect to the
application or the test conditions. The reported results
are intended to illustrate the typical behavior of the part
in one particular application, highlighting the
protections helping pass the safety tests. The reported
tests were made at 255C ambient temperature.
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15
NCP1612GEVB
BILL OF MATERIALS
Reference
Qty
Description
Manufacturer
Part number
HS1
1
Heatsink
COLUMBIASTAVER
TP207ST,120,12.5,
NA,SP,03
F1
1
4-A fuse
4A
250 V
through-hole
Multicomp
MCPEP 4A 250V
C1, C2
2
Y capacitors
1 nF
275 V
through-hole
EPCOS
B32021A3102
C3
1
X2 capacitor
C4
1
X2 capacitor
680 nF
277 V
through-hole
EPCOS
B32922C3684K
220 nF
277 V
through-hole
EPCOS
B32922C3224K
C5
1
Filtering
capacitor
470 nF
450 V
through-hole
EPCOS
B32592C6474K
C6a, C6b
2
Bulk
capacitor
68 mF
450 V
through-hole
Rubycon
450QXW68M12.5X40
C7
1
Electrolytic
capacitor
22 mF
50 V
through-hole
various
various
Diodes
Bridge
GBU406
4 A, 600 V
through-hole
LITE-ON
GBU406
U1
Value
Tolerance /
Constraints
Footprint
L1
1
DM Choke
117 mH
75 mΩ
through-hole
Pulse Engineering
PH9081NL
CM1
1
Common
Mode Filter
8.5 mH
85 mΩ
through-hole
Pulse Engineering
PH9080NL
L2
1
Boost
inductor
200 mH
6 Apk
through-hole
Wurth Elektronik
750370081 (EFD30)
Q1
1
Power
MOSFET
IPA50R250
550 V
TO220
Infineon
IPA50R250CP
D1
1
Boost diode
MUR550
5 A, 520 V
Axial
ON Semiconductor
MUR550APFG
D2
1
Bypass
diode
1N5406
3 A, 600 V
Axial
ON Semiconductor
1N5406G
DZ2
1
33 V
ZENER
diode
MMSZ33T2
33 V, 0.5 W
SOD-123
ON Semiconductor
MMSZ33T2
Rth1
1
Inrush
Current
Limiter
15 Ω
1.8 Amax
through-hole
EPCOS
B57153S0150M000
D3, D4
2
Switching
diode
D1N4148
100 V
SOD123
Vishay
1N4148W-V
R1, R2
2
X2
Capacitors
discharge
resistor
1 MΩ
1%, 500V
SMD, 1206
various
various
R3
1
Current
sense
resistor
80 mΩ
1%, 3 W
through-hole
Vishay
LVR03R0800FE12
R4
1
resistor
10 kΩ
10%, 1/4 W
SMD, 1206
various
various
R5
1
resistor
2.2 Ω
10%, 1/4 W
SMD, 1206
various
various
R6
1
resistor
22 Ω
10%, 1/4 W
SMD, 1206
various
various
R7
1
resistor
0Ω
1%, 1/4 W
SMD, 1206
various
various
R9, R10,
R23, R24,
R25
5
resistor
1.8 MΩ
1%, 1/4 W
SMD, 1206
various
various
R8, R22
2
SMD
resistor,
1206, 1/4 W
560 kΩ
1%, 1/4 W
SMD, 1206
various
various
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16
NCP1612GEVB
Reference
Qty
Description
Value
Tolerance /
Constraints
Footprint
Manufacturer
Part number
R11
1
resistor
27 kΩ
1%, 1/4 W
SMD, 1206
various
various
R12
1
resistor
22 kΩ
1%, 1/4 W
SMD, 1206
various
various
R14
1
resistor
270 kΩ
1%, 1/4 W
SMD, 1206
various
various
R13, R15,
R16, R17,
R26
5
resistor
120 kΩ
10%, 1/4 W
SMD, 1206
various
various
R18
1
resistor
27 Ω
10%, 1/4 W
SMD, 1206
various
various
R20, R21
2
resistor
4.7 kΩ
5%, 1/4 W
SMD, 1206
various
various
C8
1
Capacitor
1 nF
25 V, 10%
SMD, 1206
various
various
C9
1
Capacitor
2.2 mF
25 V, 10%
SMD, 1206
various
various
C10, C11,
C15
3
Capacitor
220 nF
25 V, 10%
SMD, 1206
various
various
C16
1
Capacitor
470 pF
25 V, 10%
SMD, 1206
various
various
C13
1
Capacitor
10 nF
100 V, 10%
SMD, 1206
various
various
D5, D6
2
Switching
diode
D1N4148
100 V
SOD123
Vishay
1N4148W-V
DZ1
1
22 V zener
diode
MMSZ22T1
22 V, 0.5 W
SOD-123
ON Semiconductor
MMSZ22T1
U2
1
PFC
Controller
NCP1612
SOIC-8
ON Semiconductor
NCP1612B
NOTE: Applications require the use of Y1 capacitors. In this case, CD12-E2GA102MYNSA from TDK or DE1E3KX102MA5B01 from
muRata may be a good option for C1 and C2.
REFERENCES
[1] Joel Turchi, “5 key steps to design a compact, high-efficiency PFC Stage Using The NCP1612”, Application note
AND9065/D, http://www.onsemi.com/pub_link/Collateral/AND9065-D.PDF.
[2] Joel Turchi, “Safety tests on a NCP1612-driven PFC stage”, Application note AND9046/D,
http://www.onsemi.com/pub_link/Collateral/AND9064-D.PDF.
[3] NCP1612 Data Sheet, http://www.onsemi.com/pub_link/Collateral/NCP1612-D.PDF
[4] NCP1612 design worksheet, http://www.onsemi.com/pub/Collateral/NCP1612%20DWS.XLS
[5] NCP1612 evaluation board documents,
http://www.onsemi.com/PowerSolutions/supportDoc.do?type=boards&rpn=NCP1612
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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