IRLIZ34N Data Sheet (259 KB, EN)

PD - 95455
IRLIZ34NPbF
Logic-Level Gate Drive
Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS …
l Sink to Lead Creepage Dist. = 4.8mm
l Fully Avalanche Rated
l Lead-Free
Description
HEXFET® Power MOSFET
l
l
D
VDSS = 55V
RDS(on) = 0.035Ω
G
ID = 22A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current †
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy ‚†
Avalanche Current†
Repetitive Avalanche Energy†
Peak Diode Recovery dv/dt Ġ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw.
22
15
110
37
0.24
±16
110
16
3.7
5.0
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case)
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient
Min.
Typ.
Max.
Units
––––
––––
––––
––––
4.1
65
°C/W
6/23/04
IRLIZ34NPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
55
–––
–––
–––
–––
1.0
11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
–––
–––
–––
–––
V(BR)DSS
IGSS
Typ.
–––
0.065
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
8.9
100
29
21
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA†
0.035
VGS = 10V, ID = 12A „
0.046
Ω
VGS = 5.0V, ID = 12A „
0.060
VGS = 4.0V, ID = 10A „
2.0
V
VDS = V GS, ID = 250µA
–––
S
VDS = 25V, ID = 16A†
25
VDS = 55V, V GS = 0V
µA
250
VDS = 44V, V GS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
25
ID = 16A
5.2
nC VDS = 44V
14
VGS = 5.0V, See Fig. 6 and 13 „†
–––
VDD = 28V
–––
ID = 16A
ns
–––
RG = 6.5Ω, VGS = 5.0V
–––
RD = 1.8Ω, See Fig. 10 „†
Between lead,
4.5 –––
6mm (0.25in.)
nH
from package
7.5 –––
and center of die contact
880 –––
VGS = 0V
220 –––
pF
VDS = 25V
94 –––
ƒ = 1.0MHz, See Fig. 5†
12 –––
ƒ = 1.0MHz
D
G
S
Source-Drain Ratings and Characteristics
IS
I SM
VSD
t rr
Q rr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) †
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ VDD = 25V, starting TJ = 25°C, L = 610µH
RG = 25Ω, IAS = 16A. (See Figure 12)
ƒ ISD ≤ 16A, di/dt ≤ 270A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Min. Typ. Max. Units
–––
–––
22
–––
–––
110
–––
–––
–––
–––
76
190
1.3
110
290
A
V
ns
nC
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V „
TJ = 25°C, IF = 16A
di/dt = 100A/µs „†
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… t=60s, ƒ=60Hz
† Uses IRLZ34N data and test conditions
D
G
S
IRLIZ34NPbF
10000
10000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.0V
100
1000
ID , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
1000
10
1
0.1
2.0V
0.01
20µs PULSE WIDTH
TJ = 25°C
A
0.001
0.1
1
10
100
100
10
1
0.01
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
100
TJ = 175°C
10
1
0.1
V DS = 25V
20µs PULSE WIDTH
5
6
7
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
10
A
100
Fig 2. Typical Output Characteristics
3.0
4
1
VDS , Drain-to-Source Voltage (V)
1000
3
20µs PULSE WIDTH
TJ = 175°C
0.001
0.1
Fig 1. Typical Output Characteristics
0.01
2.0V
0.1
VDS , Drain-to-Source Voltage (V)
2
VGS
7.50V
5.00V
4.00V
3.50V
3.00V
2.75V
2.50V
BOTTOM 2.25V
TOP
TOP
10
A
I D = 27A
2.5
2.0
1.5
1.0
0.5
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRLIZ34NPbF
1400
V GS , Gate-to-Source Voltage (V)
1200
C, Capacitance (pF)
15
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = Cds + C gd
1000
800
C oss
600
400
Crss
200
0
1
10
100
A
I D = 16A
V DS = 44V
V DS = 28V
12
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
4
V DS , Drain-to-Source Voltage (V)
12
16
20
24
28
A
32
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
8
100
TJ = 175°C
TJ = 25°C
10
100
10µs
100µs
10
1ms
VGS = 0V
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
2.0
TC = 25°C
TJ = 175°C
Single Pulse
1
1
10ms
10
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
A
100
IRLIZ34NPbF
25
RD
VDS
V GS
ID , Drain Current (A)
20
D.U.T.
RG
+
-V DD
15
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10
Fig 10a. Switching Time Test Circuit
5
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
10%
VGS
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.01
0.00001
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1
L
VDS
D.U.T.
RG
+
V
- DD
IAS
5.0 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
IRLIZ34NPbF
250
TOP
BOTTOM
200
150
100
50
VDD = 25V
0
25
tp
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
VDD
VDS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
5.0 V
QGS
ID
6.6A
11A
16A
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
A
175
IRLIZ34NPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
ISD
*
IRLIZ34NPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
E X AM P L E :
T H IS IS AN IR F I8 4 0 G
W IT H AS S E M B L Y
L OT CODE 3 432
AS S E M B L E D O N W W 2 4 1 9 9 9
IN T H E AS S E M B L Y L IN E "K "
Note: "P" in assembly line
position indicates "Lead-Free"
IN T E R N AT IO N AL
R E CT IF IE R
L OGO
AS S E M B L Y
L OT CODE
P AR T N U M B E R
IR F I8 40 G
924 K
34
32
D AT E C O D E
Y E AR 9 = 1 9 9 9
WE E K 24
L IN E K
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/