AND8269/D Layout Guidelines to Reduce Switch−Node Jitter in the CS51411/NCV51411 Prepared by: Jim Hill ON Semiconductor http://onsemi.com APPLICATION NOTE Introduction The CS5141x product family has shown some sensitivity to noise which shows up as jitter on the Switch Node pin (VSW). The CS51411 family uses V2 control to achieve superior line and load. This control method enhances the load transient response, but under certain conditions can lead to jitter if proper care is not taken. V2 performs similarly to current mode control, but that the gain is much higher. The gain is set up by the output ripple voltage plus the internal ramp. As you decrease the output voltage, you also decrease ripple voltage which, in turn, increases gain. With a high gain, the PCB layout becomes very critical. This report shows how minor changes in layout can greatly improve VSW jitter on the CS51411 family of buck converters. Problem Figures 1 and 2 show examples of this jitter phenomenon. The upper waveform (CH1) is the output voltage and the lower waveform (CH2) is the voltage at VSW. Figure 2. 18 VAC (24 VDC) to 3.3 V/1.3 A Figure 1. 18 VAC (24 VDC) to 1.8 V/1.4 A Notice that the jitter at the lower output voltage of 1.8 V is much worse than that at 3.3 V which supports the claim in the introduction. The customer was using the © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 0 ON Semiconductor evaluation board with their own components when they noted this behavior. 1 Publication Order Number: AND8269/D AND8269/D Figure 4. CS51411 Bottom Metal Figure 3. CS51411 Top Metal SOIC−16W Layout Evaluation One can see that the grounding layout is a high impedance connection that could pick up noise. Also one can see that the actual connection of the ground trace to the ground plane is at the VIN ground point. Since the input of the buck converter has discontinuous current, this connection could be injecting unwanted noise. Connecting to the output ground should be a better layout due to the continuous current at the output. Connecting directly to the ground plane could also be a better layout. As an experiment in layout optimization the NCV51411 evaluation board was utilized. NCV51411 is the same IC in a different package which uses a layout that connects the ground pin to the output ground and the bottom metal ground plane. Figures 5 and 6 show the layout for this board. Figure 6. NCV51411 SOIC−16W Bottom Metal Figure 5. NCV51411 SOIC−16W Top Metal http://onsemi.com 2 AND8269/D The following waveforms and corresponding schematics show the jitter behavior with this new layout. The input and output capacitor and the inductor are the same as the customer used. The plots are taken with Analog Persistence enabled to plot any changes in the waveform. Figure 7 shows the schematic for the 1.8 V converter which exhibited the worst jitter behavior when using the original layout. Changing the layout and the decoupling capacitor C10 to 3.3 nF eliminated the jitter problem for this converter. The decoupling capacitor was required to provide a low impedance path to ground for unwanted noise. Figures 8 and 9 show the behavior for the 1.8 V converter. D1 C 18 − 24V C1 0.1uF U1 5 SYNC 4 8 BOOST 1 VSW 3 SHDNB VFB 7 VC GND 6 C5 0.1uF L1 22uH C + C2 100uF/50V VIN 1N4148 R1 205 D2 MBRS230L CS51411 3.3V/1.5A R2 127 C4 N/C + C3 470uF A ON/#OFF 2 A Figure 7. Schematic for a 1.8 V output converter using the NCV51411 SOIC−16W Figure 8. Vin = 18 V, Vout = 1.8 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 3 AND8269/D Figure 9. Vin = 24 V, Vout = 1.8 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 4 AND8269/D Figure 10 shows the schematic for the 3.3 V converter. This converter did not show as much of jitter due to the higher duty cycle/output voltage. Changing the layout was all that was necessary to eliminate the jitter problem for this converter. Figures 11 and 12 show the behavior for the 3.3 V converter. 3.3V D3 C A 1N4148 18 − 24V C6 0.1uF U2 5 ON/#OFF + C7 100uF/50V VIN BOOST 1 VSW 3 SYNC 4 SHDNB VFB 7 8 VC GND 6 L2 22uH C 2 R3 52.6 D4 MBRS230L CS51411 A C12 0.1uF 1.8V/1.5A R4 127 C10 N/C + C8 470uF Figure 10. Schematic for a 3.3 V output converter using the NCV51411 SOIC−16W Figure 11. Vin = 18 V, Vout = 3.3 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 5 AND8269/D Figure 12. Vin = 24 V, Vout = 3.3 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 6 AND8269/D DFN−18 Layout Evaluation The same experiment was run on the DFN−18 version of the NCV51411. Figures 13 and 14 show the layout for this package. Again, the ground connection was made as close as possible to the VOUT ground connection and the ground plane to reduce noise pickup. Figure 13. NCV51411 DFN Top Metal Figure 14. NCV51411 DFN Bottom Metal 3.3V D3 C A MMSD4148 18 − 24V C6 0.1uF U2 5 BOOST 1 VSW 3 SYNC 4 SHDNB VFB 7 8 VC GND 6 C12 0.1uF L2 22uH CS51411 1.8V/1.5A R3 52.6 D4 MBRS230L A ON/#OFF + C7 100uF/50V VIN C 2 R4 127 C10 N/C + C8 470uF Figure 15. Schematic for a 1.8 V output converter using the NCV51411 DFN−18 http://onsemi.com 7 AND8269/D Figure 16. Vin = 18 V, Vout = 1.8 V, Iout = 1.5 A, C1 = Vout, C2 = VSW Figure 17. Vin = 24 V, Vout = 1.8 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 8 AND8269/D D1 C 18 − 24V C1 0.1uF U1 + C2 100uF/50V 1 VSW 3 SHDNB VFB 7 VC GND 6 SYNC 4 8 C5 0.1uF L1 22uH C ON/#OFF BOOST VIN 5 MMSD4148 R1 205 D2 MBRS230L CS51411 3.3V/1.5A R2 127 C4 N/C + C3 470uF A 2 A Figure 18. Schematic for a 3.3 V output converter using the NCV51411 DFN−18 Figure 19. Vin = 18 V, Vout = 3.3 V, Iout = 1.5 A, C1 = Vout, C2 = VSW http://onsemi.com 9 AND8269/D Figure 20. Vin = 24 V, Vout = 3.3 V, Iout = 1.5 A, C1 = Vout, C2 = VSW Summary pickup. Also, as pointed out earlier, when you decrease the output voltage, you also decrease ripple voltage which, in turn, increases gain. For lower output voltages noise immunity improves even further by decoupling the feedback pin (VFB), but the key to eliminating jitter is the layout. The above data shows that with proper layout and decoupling, the jitter in the CS51411 family can be eliminated. Proper layout involves connecting the IC ground close the Vout ground point, rather than Vin, and providing a via to a low impedance ground plane to prevent noise ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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