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The CS5141X products are 1.5 A buck regulator ICs. These devices
are fixed–frequency operating at 260 kHz and 520 kHz. The regulators
use the V2 control architecture to provide unmatched transient
response, the best overall regulation and the simplest loop
compensation for today’s high–speed logic. These products
accommodate input voltages from 4.5 V to 40 V.
The CS51411 and CS51413 contain synchronization circuitry. The
CS51412 and CS51414 have the option of powering the controller
from an external 3.3 V to 6.0 V supply in order to improve efficiency,
especially in high input voltage, light load conditions.
The on–chip NPN transistor is capable of providing a minimum of
1.5 A of output current, and is biased by an external “boost” capacitor
to ensure saturation, thus minimizing on–chip power dissipation.
Protection circuitry includes thermal shutdown, cycle–by–cycle
current limiting and frequency foldback. The CS51411 and CS51413
are functionally pin–compatible with the LT1375. The CS51412 and
CS51414 are functionally pin–compatible with the LT1376.
Features
• V2 Architecture Provides Ultra–Fast Transient Response, Improved
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MARKING DIAGRAM
8
5141X
ALYWT
1
X
A
WL, L
YY, Y
WW, W
T
•
•
•
•
•
•
•
Reduces Short Circuit Power Dissipation
BOOST Lead Allows “Bootstrapped” Operation to Maximize
Efficiency
Sync Function for Parallel Supply Operation or Noise Minimization
Shutdown Lead Provides Power–Down Option
85 µA Quiescent Current During Power–Down
Thermal Shutdown
Soft Start
Pin–Compatible with LT1375 and LT1376
= 1, 2, 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Temperature Range, E or G
PIN CONNECTIONS
Regulation and Simplified Design
• 2.0% Error Amp Reference Voltage Tolerance
• Switch Frequency Decrease of 4:1 in Short Circuit Conditions
SO–8
D SUFFIX
CASE 751
8
CS51411/3
BOOST
1
8
VIN
VSW
VC
VFB
GND
SHDNB
SYNC
CS51412/4
BOOST
1
8
VC
VIN
VSW
VFB
GND
BIAS
SHDNB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 11
1
Publication Order Number:
CS51411/D
CS51411, CS51412, CS51413, CS51414
PRODUCT SELECTION GUIDE
Part Number
Frequency
Temperature Range
Bias/Sync
CS51411E
260 kHz
–40°C to 85°C
Sync
CS51411G
260 kHz
0°C to 70°C
Sync
CS51412E
260 kHz
–40°C to 85°C
Bias
CS51412G
260 kHz
0°C to 70°C
Bias
CS51413E
520 kHz
–40°C to 85°C
Sync
CS51413G
520 kHz
0°C to 70°C
Sync
CS51414E
520 kHz
–40°C to 85°C
Bias
CS51414G
520 kHz
0°C to 70°C
Bias
1N4148
D1
C1
0.1 µF
4.5 V – 16 V
C2
100 µF
Shutdown
VIN
4
SHDNB
5
SYNC
1
U1 2
SYNC
VC
8
BOOST
VSW
3
CS51411/3
GND
VFB
6
7
3.3 V
L1
15 µH
D3
1N5821
R1
205
C3
100 µF
R2
127
C4
0.1 µF
Figure 1. Application Diagram, 4.5 V – 16 V to 3.3 V @ 1.0 A Converter
MAXIMUM RATINGS*
Rating
Operating Junction Temperature Range, TJ
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Storage Temperature Range, TS
ESD Damage Threshold (Human Body Model)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
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Value
Unit
–40 to 150
°C
230 peak
°C
–65 to +150
°C
2.0
kV
CS51411, CS51412, CS51413, CS51414
MAXIMUM RATINGS
Pin Name
VMax
VMIN
ISOURCE
ISINK
VIN
40 V
–0.3 V
N/A
4.0 A
BOOST
40 V
–0.3 V
N/A
100 mA
VSW
40 V
–0.6 V/–1.0 V, t < 50 ns
4.0 A
10 mA
VC
7.0 V
–0.3 V
1.0 mA
1.0 mA
SHDNB
7.0 V
–0.3 V
1.0 mA
1.0 mA
SYNC
7.0 V
–0.3 V
1.0 mA
1.0 mA
BIAS
7.0 V
–0.3 V
1.0 mA
50 mA
VFB
7.0 V
–0.3 V
1.0 mA
1.0 mA
GND
7.0 V
–0.3 V
50 mA
1.0 mA
ELECTRICAL CHARACTERISTICS (–40°C < TJ < 125°C (CS51411E/2E/3E/4E); –40°C < TA < 85°C (CS51411E/2E/3E/4E);
0°C < TA < 70°C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
Oscillator
Operating Frequency
CS51411/CS51412
224
260
296
kHz
Operating Frequency
CS51413/CS51414
446
520
594
kHz
Frequency Line Regulation
–
–
0.05
0.15
%/V
Maximum Duty Cycle
–
85
90
95
%
VFB Frequency Foldback Threshold
–
0.29
0.32
0.36
V
8.0
25
17
50
26
75
mV/µs
mV/µs
–
–
150
–
300
230
ns
ns
PWM Comparator
Slope Compensation Voltage
CS51411/CS51412, Fix VFB, ∆VC/∆TON
CS51413/CS51414
Minimum Output Pulse Width
CS51411/CS51412, VFB to VSW
CS51413/CS51414, VFB to VSW
Power Switch
Current Limit
VFB > 0.36 V
1.6
2.3
3.0
A
Foldback Current
VFB < 0.29 V
0.9
1.5
2.1
A
Saturation Voltage
IOUT = 1.5 A, VBOOST = VIN + 2.5 V
0.4
0.7
1.0
V
Current Limit Delay
Note 2
–
120
160
ns
1.244
1.270
1.296
V
–
40
–
dB
–
0.02
0.1
µA
Error Amplifier
–
Internal Reference Voltage
Reference PSRR
Note 2
FB Input Bias Current
–
Output Source Current
VC = 1.270 V, VFB = 1.0 V
15
25
35
µA
Output Sink Current
VC = 1.270 V, VFB = 2.0 V
15
25
35
µA
Output High Voltage
VFB = 1.0 V
1.39
1.46
1.53
V
Output Low Voltage
VFB = 2.0 V
5.0
20
60
mV
Unity Gain Bandwidth
Note 2
–
500
–
kHz
Open Loop Amplifier Gain
Note 2
–
70
–
dB
Amplifier Transconductance
Note 2
–
6.4
–
mA/V
2. Guaranteed by design, not 100% tested in production.
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CS51411, CS51412, CS51413, CS51414
ELECTRICAL CHARACTERISTICS (continued) (–40°C < TJ < 125°C (CS51411E/2E/3E/4E); –40°C < TA < 85°C (CS51411E/2E/3E/4E);
0°C < TA < 70°C (CS51411G/2G/3G/4G), 4.5 V< VIN < 40 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Sync
Sync Frequency Range
CS51411/CS51412
305
–
470
kHz
Sync Frequency Range
CS51413/CS51414
575
–
880
kHz
Sync Pin Bias Current
VSYNC = 0 V
VSYNC = 5.0 V
–
250
0.1
360
0.2
460
µA
µA
1.0
1.5
1.9
V
Sync Threshold Voltage
–
Shutdown
–
1.0
1.3
1.6
V
VSHDNB = 0 V
0.14
5.00
35
µA
Overtemperature Trip Point
Note 3
175
185
195
°C
Thermal Shutdown Hysteresis
Note 3
–
42
–
°C
Shutdown Threshold Voltage
Shutdown Pin Bias Current
Thermal Shutdown
General
Quiescent Current
ISW = 0 A
3.0
4.0
6.25
mA
Shutdown Quiescent Current
VSHDNB = 0 V
8.0
20
85
µA
Boost Operating Current
VBOOST – VSW = 2.5 V
6.0
15
40
mA/A
Minimum Boost Voltage
Note 3
–
–
2.5
V
Start up Voltage
–
2.2
3.3
4.4
V
Minimum Output Current
–
–
7.0
12
mA
3. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1
BOOST
The BOOST pin provides additional drive voltage to the on–chip NPN power transistor.
The resulting decrease in switch on voltage increases efficiency.
2
VIN
This pin is the main power input to the IC.
3
VSW
This is the connection to the emitter of the on–chip NPN power transistor and serves
as the switch output to the inductor. This pin may be subjected to negative voltages
during switch off–time. A catch diode is required to clamp the pin voltage in normal
operation. This node can stand –1.0 V for less than 50 ns during switch node flyback.
4 (CS51412/CS51414)
BIAS
The BIAS pin connects to the on–chip power rail and allows the IC to run most of its
internal circuitry from the regulated output or another low voltage supply to improve
efficiency. The BIAS pin is left floating if this feature is not used.
5 (CS51411/CS51413)
SYNC
This pin provides the synchronization input.
5 (CS51412/CS51414)
4 (CS51411/CS51413)
SHDNB
6
GND
Power return connection for the IC.
7
VFB
The FB pin provides input to the inverting input of the error amplifier. If VFB is lower
than 0.29 V, the oscillator frequency is divided by four, and current limit folds back to
about 1 ampere. These features protect the IC under severe overcurrent or short
circuit conditions.
8
VC
The VC pin provides a connection point to the output of the error amplifier and input to
the PWM comparator. Driving of this pin should be avoided because on–chip test
circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC.
The shutdown pin is active low and TTL compatible. The IC goes into sleep mode,
drawing less than 85 µA when the pin voltage is pulled below 1.0 V. This pin should be
left floating in normal position.
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CS51411, CS51412, CS51413, CS51414
SHDNB
SYNC
VIN
5.0 µA
BIAS
2.9 V LDO
Voltage
Regulator
Shutdown
Comparator
+
Artificial
Ramp
–
Thermal
Shutdown
Oscillator
BOOST
+
1.3 V –
S
Q
Output
Driver
R
VSW
∑
+
Current
Limit
Comparator
–
PWM
Comparator
+
1.46 V
IREF
–
–
–
VFB
+
+
0.32 V –
+
1.270 V
+
–
Frequency
and Current
Limit Foldback
Error
Amplifier
VC
Figure 2. Block Diagram
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IFOLDBACK
GND
CS51411, CS51412, CS51413, CS51414
APPLICATIONS INFORMATION
THEORY OF OPERATION
The slope compensation signal is a fixed voltage ramp
provided by the oscillator. Adding this signal eliminates
subharmonic oscillation associated with the operation at
duty cycle greater than 50%. The artificial ramp also ensures
the proper PWM function when the output ripple voltage is
inadequate. The slope compensation signal is properly sized
to serve it purposes without sacrificing the transient
response speed.
Under load and line transient, not only the ramp signal
changes, but more significantly the DC component of the
feedback voltage varies proportionally to the output voltage.
FFB path connects both signals directly to the PWM
comparator. This allows instant modulation of the duty cycle
to counteract any output voltage deviations. The transient
response time is independent of the error amplifier
bandwidth. This eliminates the delay associated with error
amplifier and greatly improves the transient response time.
The error amplifier is used here to ensure excellent DC
accuracy.
V2 Control
The CS5141X family of buck regulators provides leading
edge technology, a high level of integration and high
operating frequencies allowing the layout of a switch–mode
power supply in a very small board area. These devices are
based on the proprietary V2 control architecture. V2 control
uses the output voltage and its ripple as the ramp signal,
providing an ease of use not generally associated with
voltage or current mode control. Improved line regulation,
load regulation and very fast transient response are also
major advantages.
S1
VIN
L1
VO
R1
Duty Cycle
C1
D1
Buck
Controller
Error Amplifier
Oscillator
The CS5141X has a transconductance error amplifier,
whose non–inverting input is connected to an Internal
Reference Voltage generated from the on–chip regulator.
The inverting input connects to the VFB pin. The output of
the error amplifier is made available at the VC pin. A typical
frequency compensation requires only a 0.1 µF capacitor
connected between the VC pin and ground, as shown in
Figure 1. This capacitor and error amplifier’s output
resistance (approximately 8.0 MΩ) create a low frequency
pole to limit the bandwidth. Since V2 control does not
require a high bandwidth error amplifier, the frequency
compensation is greatly simplified.
The VC pin is clamped below Output High Voltage. This
allows the regulator to recover quickly from over current or
short circuit conditions.
Slope
Comp
FFB
+
Latch S
R
V2 Control
VC
+
−
−
+
PWM
Comparator
R2
SFB
Error
Amplifier
VREF
+
–
Figure 3. Buck Converter with V2 Control.
As shown in Figure 3, there are two voltage feedback
paths in V2 control, namely FFB(Fast Feedback) and
SFB(Slow Feedback). In FFB path, the feedback voltage
connects directly to the PWM comparator. This feedback
path carries the ramp signal as well as the output DC voltage.
Artificial ramp derived from oscillator is added to the
feedback signal to improve stability. The other feedback
path SFB connects the feedback voltage to the error
amplifier whose output VC feeds to the other input of the
PWM comparator. In a constant frequency mode, the
oscillator signal sets the output latch and turns on the switch
S1. This starts a new switch cycle. The ramp signal,
composed of both artificial ramp and output ripple,
eventually comes across the VC voltage, and consequently
resets the latch to turn off the switch. The switch S1 will turn
on again at the beginning of the next switch cycle. In a buck
converter, the output ripple is determined by the ripple
current of the inductor L1 and the ESR (equivalent series
resistor) of the output capacitor C1.
Oscillator and Sync Feature (CS51411 and CS51413 only)
The on–chip oscillator is trimmed at the factory and
requires no external components for frequency control. The
high switching frequency allows smaller external
components to be used, resulting in a board area and cost
savings. The tight frequency tolerance simplifies magnetic
components selection. The switching frequency is reduced
to 25% of the nominal value when the VFB pin voltage is
below Frequency Foldback Threshold. In short circuit or
over–load conditions, this reduces the power dissipation of
the IC and external components.
An external clock signal can sync CS51411/CS51414 to
a higher frequency. The rising edge of the sync pulse turns
on the power switch to start a new switching cycle, as shown
in Figure 4. There is approximately 0.5 µs delay between the
rising edge of the sync pulse and rising edge of the VSW pin
voltage. The sync threshold is TTL logic compatible, and
duty cycle of the sync pulses can vary from 10% to 90%. The
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CS51411, CS51412, CS51413, CS51414
components. When the peak of the switching current reaches
the Current Limit, the power switch turns off after the
Current Limit Delay. The switch will not turn on until the
next switching cycle. The current limit threshold is
independent of switching duty cycle. The maximum load
current, given by the following formula under continuous
conduction mode, is less than the Current Limit due to the
ripple current.
frequency foldback feature is disabled during the sync
mode.
V (V * VO)
IO(MAX) + ILIM * O IN
2(L)(VIN)(fs)
where:
fS = switching frequency,
ILIM = current limit threshold,
VO = output voltage,
VIN = input voltage,
L = inductor value.
When the regulator runs under current limit, the
subharmonic oscillation may cause low frequency
oscillation, as shown in Figure 6. Similar to current mode
control, this oscillation occurs at the duty cycle greater than
50% and can be alleviated by using a larger inductor value.
The current limit threshold is reduced to Foldback Current
when the FB pin falls below Foldback Threshold. This
feature protects the IC and external components under the
power up or over–load conditions.
Figure 4. A CS51411 Buck Regulator is Synced by an
External 350 kHz Pulse Signal
Power Switch and Current Limit
The collector of the built–in NPN power switch is
connected to the VIN pin, and the emitter to the VSW pin.
When the switch turns on, the VSW voltage is equal to the
VIN minus switch Saturation Voltage. In the buck regulator,
the VSW voltage swings to one diode drop below ground
when the power switch turns off, and the inductor current is
commutated to the catch diode. Due to the presence of high
pulsed current, the traces connecting the VSW pin, inductor
and diode should be kept as short as possible to minimize the
noise and radiation. For the same reason, the input capacitor
should be placed close to the VIN pin and the anode of the
diode.
The saturation voltage of the power switch is dependent
on the switching current, as shown in Figure 5.
0.7
0.6
VIN – VSW (V)
0.5
Figure 6. The Regulator in Current Limit
0.4
BOOST Pin
0.3
The BOOST pin provides base driving current for the
power switch. A voltage higher than VIN provides required
headroom to turn on the power switch. This in turn reduces
IC power dissipation and improves overall system
efficiency. The BOOST pin can be connected to an external
boost–strapping circuit which typically uses a 0.1 µF capacitor
and a 1N914 or 1N4148 diode, as shown in Figure 1. When the
power switch is turned on, the voltage on the BOOST pin is
equal to
0.2
0.1
0
0
0.5
1.0
Switching Current (A)
1.5
Figure 5. The Saturation Voltage of the Power Switch
Increases with the Conducting Current
VBOOST + VIN ) VO * VF
Members of the CS5141X family contain pulse–by–pulse
current limiting to protect the power switch and external
where:
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CS51411, CS51412, CS51413, CS51414
to the inductor, IC and catch diode. In V2 control , the
compensation capacitor provides Soft Start with no need for
extra pin or circuitry. During the power up, the Output
Source Current of the error amplifier charges the
compensation capacitor which forces VC pin and thus output
voltage ramp up gradually. The Soft Start duration can be
calculated by
VF = diode forward voltage.
The anode of the diode can be connected to any DC voltage
other than the regulated output voltage. However, the
maximum voltage on the BOOST pin shall not exceed 40 V.
As shown in Figure 7, the BOOST pin current includes a
constant 7.0 mA pre–driver current and base current
proportional to switch conducting current. A detailed
discussion of this current is conducted in Thermal
Consideration section. A 0.1 µF capacitor is usually
adequate for maintaining the Boost pin voltage during the on
time.
V
CCOMP
TSS + C
ISOURCE
where:
VC = VC pin steady–state voltage, which is approximately
equal to error amplifier’s reference voltage.
CCOMP = Compensation capacitor connected to the VC pin
ISOURCE = Output Source Current of the error amplifier.
Boost Pin Current (mA)
30
25
Using a 0.1 µF CCOMP, the calculation shows a TSS over
5.0 ms which is adequate to avoid any current stresses.
Figure 8 shows the gradual rise of the VC, VO and envelope
of the VSW during power up. There is no voltage over–shoot
after the output voltage reaches the regulation. If the supply
voltage rises slower than the VC pin, output voltage may
over–shoot.
20
15
10
5
0
0
0.5
1.0
Switching Current (A)
1.5
Figure 7. The Boost Pin Current Includes 7.0 mA
Pre–Driver Current and Base Current when the
Switch is Turned On. The Beta Decline of the
Power Switch Further Increases the Base
Current at High Switching Current
BIAS Pin (CS51412 and CS51414 Only)
The BIAS pin allows a secondary power supply to bias the
control circuitry of the IC. The BIAS pin voltage should be
between 3.3 V and 6.0 V. If the BIAS pin voltage falls below
that range, use a diode to prevent current drain from the
BIAS pin. Powering the IC with a voltage lower than the
regulator’s input voltage reduces the IC power dissipation
and improves energy transfer efficiency.
Figure 8. The Power Up Transition of CS5141X
Regulator
Short Circuit
Shutdown
When the VFB pin voltage drops below Foldback
Threshold, the regulator reduces the peak current limit by
40% and switching frequency to 1/4 of the nominal
frequency. These features are designed to protect the IC and
external components during over load or short circuit
conditions. In those conditions, peak switching current is
clamped to the current limit threshold. The reduced
switching frequency significantly increases the ripple
current, and thus lowers the DC current. The short circuit can
cause the minimum duty cycle to be limited by Minimum
Output Pulse Width. The foldback frequency reduces the
minimum duty cycle by extending the switching cycle. This
protects the IC from overheating, and also limits the power
that can be transferred to the output. The current limit
foldback effectively reduces the current stress on the
The internal power switch will not turn on until the VIN
pin rises above the Start Up Voltage. This ensures no
switching until adequate supply voltage is provided to the
IC.
The IC enters a sleep mode when the SHDNB pin is pulled
below Shutdown Threshold Voltage. In the sleep mode, the
power switch keeps open and the supply current reduces to
Shutdown Quiescent Current. This pin has internal pull–up
current. So when this pin is not used, leave the SHDNB pin
open.
Start–Up
During power up, the regulator tends to quickly charge up
the output capacitors to reach voltage regulation. This gives
rise to an excessive in–rush current which can be detrimental
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CS51411, CS51412, CS51413, CS51414
current when the transistor needs to be on. The power
dissipated by the IC due to this current is
inductor and diode. When the output is shorted, the DC
current of the inductor and diode can approach the current
limit threshold. Therefore, reducing the current limit by 40%
can result in an equal percentage drop of the inductor and
diode current. The short circuit waveforms are captured in
Figure 9, and the benefit of the foldback frequency and
current limit is self–evident.
V 2
WBASE + O
VIN
IS
60
where:
IS = DC switching current.
When the power switch turns on, the saturation voltage
and conduction current contribute to the power loss of a
non–ideal switch. The power loss can be quantified as
WSAT +
VO
VIN
IS
VSAT
where:
VSAT = saturation voltage of the power switch which is
shown in Figure 5.
The switching loss occurs when the switch experiences
both high current and voltage during each switch transition.
This regulator has a 30 ns turn–off time and associated
power loss is equal to
I
WS + S
20 ns
fS
The turn–on time is much shorter and thus turn–on loss is
not considered here.
The total power dissipated by the IC is sum of all the above
Figure 9. In Short Circuit, the Foldback Current and
Foldback Frequency Limit the Switching Current to
Protect the IC, Inductor and Catch Diode
WIC + WQ ) WDRV ) WBASE ) WSAT ) WS
Thermal Considerations
A calculation of the power dissipation of the IC is always
necessary prior to the adoption of the regulator. The current
drawn by the IC includes quiescent current, pre–driver
current, and power switch base current. The quiescent
current drives the low power circuits in the IC, which
include comparators, error amplifier and other logic blocks.
Therefore, this current is independent of the switching
current and generates power equal to
WQ + VIN
The IC junction temperature can be calculated from the
ambient temperature, IC power dissipation and thermal
resistance of the package. The equation is shown as follows,
TJ + WIC
RqJA ) TA
The maximum IC junction temperature shall not exceed
125°C to guarantee proper operation and avoid any damages
to the IC.
IQ
Minimum Load Requirement
As pointed out in the previous section, a minimum load is
required for this regulator due to the pre–driver current
feeding the output. Placing a resistor equal to VO divided by
12 mA should prevent any voltage overshoot at light load
conditions. Alternatively, the feedback resistors can be
valued properly to consume 12 mA current.
where:
IQ = quiescent current.
The pre–driver current is used to turn on/off the power
switch and is approximately equal to 12 mA in worst case.
During steady state operation, the IC draws this current from
the Boost pin when the power switch is on and then receives
it from the VIN pin when the switch is off. The pre–driver
current always returns to the VSW pin. Since the pre–driver
current goes out to the regulator’s output even when the
power switch is turned off, a minimum load is required to
prevent overvoltage in light load conditions. If the Boost pin
voltage is equal to VIN + VO when the switch is on, the power
dissipation due to pre–driver current can be calculated by
WDRV + 12 mA
VIN
2
COMPONENT SELECTION
Input Capacitor
In a buck converter, the input capacitor witnesses pulsed
current with an amplitude equal to the load current. This
pulsed current and the ESR of the input capacitors determine
the VIN ripple voltage, which is shown in Figure 10. For VIN
ripple, low ESR is a critical requirement for the input
capacitor selection. The pulsed input current possesses a
significant AC component, which is absorbed by the input
capacitors. The RMS current of the input capacitor can be
calculated using:
V 2
(VIN * VO ) O )
VIN
The base current of a bipolar transistor is equal to collector
current divided by beta of the device. Beta of 60 is used here
to estimate the base current. The Boost pin provides the base
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CS51411, CS51412, CS51413, CS51414
IRMS + IO ǸD(1 * D)
Selecting the capacitor type is determined by each
design’s constraint and emphasis. The aluminum
electrolytic capacitors are widely available at lowest cost.
Their ESR and ESL (equivalent series inductor) are
relatively high. Multiple capacitors are usually paralleled to
achieve lower ESR. In addition, electrolytic capacitors
usually need to be paralleled with a ceramic capacitor for
filtering high frequency noises. The OS–CON are solid
aluminum electrolytic capacitors, and therefore has a much
lower ESR. Recently, the price of the OS–CON capacitors
has dropped significantly so that it is now feasible to use
them for some low cost designs. Electrolytic capacitors are
physically large, and not used in applications where the size,
and especially height is the major concern.
Ceramic capacitors are now available in values over 10 µF.
Since the ceramic capacitor has low ESR and ESL, a single
ceramic capacitor can be adequate for both low frequency
and high frequency noises. The disadvantage of ceramic
capacitors are their high cost. Solid tantalum capacitors can
have low ESR and small size. However, the reliability of the
tantalum capacitor is always a concern in the application
where the capacitor may experience surge current.
where:
D = switching duty cycle which is equal to VO/VIN.
IO = load current.
Figure 10. Input Voltage Ripple in a Buck Converter
Output Capacitor
To calculate the RMS current, multiply the load current
with the constant given by Figure 11 at each duty cycle. It is
a common practice to select the input capacitor with an RMS
current rating more than half the maximum load current. If
multiple capacitors are paralleled, the RMS current for each
capacitor should be the total current divided by the number
of capacitors.
In a buck converter, the requirements on the output
capacitor are not as critical as those on the input capacitor.
The current to the output capacitor comes from the inductor
and thus is triangular. In most applications, this makes the
RMS ripple current not an issue in selecting output
capacitors.
The output ripple voltage is the sum of a triangular wave
caused by ripple current flowing through ESR, and a square
wave due to ESL. Capacitive reactance is assumed to be
small compared to ESR and ESL. The peak to peak ripple
current of the inductor is:
0.6
0.5
IRMS (XIO)
0.4
V (V * VO)
IP * P + O IN
(VIN)(L)(fS)
0.3
VRIPPLE(ESR), the output ripple due to the ESR, is equal
to the product of IP–P and ESR. The voltage developed
across the ESL is proportional to the di/dt of the output
capacitor. It is realized that the di/dt of the output capacitor
is the same as the di/dt of the inductor current. Therefore,
when the switch turns on, the di/dt is equal to (VIN – VO)/L,
and it becomes VO/L when the switch turns off. The total
ripple voltage induced by ESL can then be derived from
0.2
0.1
0
0
0.2
0.4
0.6
Duty Cycle
0.8
1.0
Figure 11. Input Capacitor RMS Current can be
Calculated by Multiplying Y Value with Maximum Load
Current at any Duty Cycle
V * VO
V
V
VRIPPLE(ESL) + ESL( IN) ) ESL( IN
) + ESL( IN)
L
L
L
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10
CS51411, CS51412, CS51413, CS51414
The total output ripple is the sum of the VRIPPLE(ESR) and
VRIPPLE(ESR).
Figure 15. The Output Voltage Ripple Using
One 100 mF Tantalum Capacitor
Figure 12. The Output Voltage Ripple Using Two 10 mF
Ceramic Capacitors in Parallel
Figure 12 to Figure 15 show the output ripple of a 5.0 V
to 3.3 V/500 mA regulator using 22 µH inductor and various
capacitor types. At the switching frequency, the low ESR
and ESL make the ceramic capacitors behave capacitively
as shown in Figure 12. Additional paralleled ceramic
capacitors will further reduce the ripple voltage, but
inevitably increase the cost. “POSCAP”, manufactured by
SANYO, is a solid electrolytic capacitor. The anode is
sintered tantalum and the cathode is a highly conductive
polymerized organic semiconductor. TPC series, featuring
low ESR and low profile, is used in the measurement of
Figure 13. It is shown that POSCAP presents a good balance
of capacitance and ESR, compared with a ceramic capacitor.
In this application, the low ESR generates less than 5.0 mV
of ripple and the ESL is almost unnoticeable. The ESL of the
through–hole OS–CON capacitor give rise to the inductive
impedance. It is evident from Figure 14 which shows the
step rise of the output ripple on the switch turn–on and large
spike on the switch turn–off. The ESL prevents the output
capacitor from quickly charging up the parasitic capacitor of
the inductor when the switch node is pulled below ground
through the catch diode conduction. This results in the spike
associated with the falling edge of the switch node. The D
package tantalum capacitor used in Figure 15 has the same
footprint as the POSCAP, but doubles the height. The ESR
of the tantalum capacitor is apparently higher than the
POSCAP. The electrolytic and tantalum capacitors provide
a low–cost solution with compromised performance. The
reliability of the tantalum capacitor is not a serious concern
for output filtering because the output capacitor is usually
free of surge current and voltage.
Figure 13. The Output Voltage Ripple Using One 100 mF
POSCAP Capacitor
Diode Selection
The diode in the buck converter provides the inductor
current path when the power switch turns off. The peak
reverse voltage is equal to the maximum input voltage. The
peak conducting current is clamped by the current limit of
the IC. The average current can be calculated from:
Figure 14. The Output Voltage Ripple Using
One 100 mF OS–CON
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11
CS51411, CS51412, CS51413, CS51414
I (V * VO)
ID(AVG) + O IN
VIN
The DC current through the inductor is equal to the load
current. The worse case occurs during maximum load
current. Check the vendor’s spec to adjust the inductor value
under current loading. Inductors can lose over 50% of
inductance when it nears saturation.
The core materials have a significant effect on inductor
performance. The ferrite core has benefits of small physical
size, and very low power dissipation. But be careful not to
operate these inductors too far beyond their maximum
ratings for peak current, as this will saturate the core.
Powered Iron cores are low cost and have a more gradual
saturation curve. The cores with an open magnetic path, such
as rod or barrel, tend to generate high magnetic field
radiation. However, they are usually cheap and small. The
cores providing a close magnetic loop, such as pot–core and
toroid, generate low electro–magnetic interference (EMI).
There are many magnetic component vendors providing
standard product lines suitable for CS5141X. Table 2 lists
three vendors, their products and contact information.
The worse case of the diode average current occurs during
maximum load current and maximum input voltage. For the
diode to survive the short circuit condition, the current rating
of the diode should be equal to the Foldback Current Limit.
See Table 1 for schottky diodes from ON Semiconductor
which are suggested for CS5141X regulator.
Inductor Selection
When choosing inductors, one might have to consider
maximum load current, core and copper losses, component
height, output ripple, EMI, saturation and cost. Lower
inductor values are chosen to reduce the physical size of the
inductor. Higher value cuts down the ripple current, core
losses and allows more output current. For most
applications, the inductor value falls in the range between
2.2 µH and 22 µH. The saturation current ratings of the
inductor shall not exceed the IL(PK), calculated according to
V (V * VO)
IL(PK) + IO ) O IN
2(fS)(L)(VIN)
Table 1.
Part Number
VBREAKDOWN (V)
IAVERAGE (A)
V(F) (V) @ IAVERAGE
Package
1N5817
20
1.0
0.45
Axial Lead
1N5818
30
1.0
0.55
Axial Lead
1N5819
40
1.0
0.6
Axial Lead
MBR0520
20
0.5
0.385
SOD–123
MBR0530
30
0.5
0.43
SOD–123
MBR0540
40
0.5
0.53
SOD–123
MBRS120
20
1.0
0.55
SMB
MBRS130
30
1.0
0.395
SMB
MBRS140
40
1.0
0.6
SMB
Table 2.
Vendor
Product Family
Web Site
Telephone
Coiltronics
UNI–Pac1/2: SMT, barrel
THIN–PAC: SMT, toroid, low profile
CTX: Leaded, toroid
www.coiltronics.com
(516) 241–7876
Coilcraft
DO1608: SMT, barrel
DS/DT 1608: SMT, barrel, magnetically shielded
DO3316: SMT, barrel
DS/DT 3316: SMT, barrel, magnetically shielded
DO3308: SMT, barrel, low profile
www.coilcraft.com
(800) 322–2645
Pulse
–
www.pulseeng.com
(619) 674–8100
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12
CS51411, CS51412, CS51413, CS51414
U1
5.0 V – 12 V input
2
C1
22 µF
4
5
7
VFB
VIN
C5
0.1 µF
BOOST 1
SHDNB CS51411/3
SYNC
VSW 3
15 µH L1
VC
GND
6
R2
373
D2
1N4148
D1
MBR0520
8
R3
127
C6
22 µ
C2
0.1 µF
–5.0 V output
C3
C4
0.01 µF
R1 50 k
0.1 µF
Figure 16. Additional Application Diagram, 5.0 V – 12 V to –5.0 V/400 mA Inverting Converter
D2 1N4148
1N4148
D1
12 V
C1
100 µF
Shutdown
U1 2
VIN
5 SHDNB
VC
8
1
BOOST
4
BIAS
C1
0.1 µF
VSW
3
CS51412/4
GND
VFB
6
7
5.0 V
L1
15 µH
D3
1N5821
R1
373
C3
100 µF
R2
127
C4
0.1 µF
Figure 17. Additional Application Diagram, 12 V to 5.0 V/1.0 A Buck Converter using the BIAS Pin
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13
CS51411, CS51412, CS51413, CS51414
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
CS51411ED8
95 Units/Rail
CS51411EDR8
2500 Tape & Reel
CS51412ED8
95 Units/Rail
CS51412EDR8
CS51413ED8
2500 Tape & Reel
–40°C
40°C < TA < 85°C
95 Units/Rail
CS51413EDR8
2500 Tape & Reel
CS51414ED8
95 Units/Rail
CS51414EDR8
2500 Tape & Reel
SO 8
SO–8
CS51411GD8
CS51411GDR8
95 Units/Rail
2500 Tape & Reel
CS51412GD8
95 Units/Rail
CS51412GDR8
CS51413GD8
Shipping
2500 Tape & Reel
0°C < TA < 70°C
95 Units/Rail
CS51413GDR8
2500 Tape & Reel
CS51414GD8
95 Units/Rail
CS51414GDR8
2500 Tape & Reel
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14
CS51411, CS51412, CS51413, CS51414
PACKAGE DIMENSIONS
SO–8
D SUFFIX
CASE 751–07
ISSUE V
! " # $ ! % # –X–
A
8
5
&!
S
B
1
4
K
–Y–
G
C
N
X 45 _
SEATING
PLANE
–Z–
&!
H
D
&!
' M
J
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
$
$&
$
&&_
&&_
PACKAGE THERMAL DATA
Parameter
SO–8
Unit
RΘJC
Typical
45
°C/W
RΘJA
Typical
165
°C/W
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15
INCHES
MIN
MAX
$
$
&
$
&&_
&&_
CS51411, CS51412, CS51413, CS51414
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
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2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051
Phone: 81–3–5773–3850
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
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16
CS51411/D