AND8284/D Improving Output Voltage Ripple of the NCP3063 Series of Switching Regulators by Applying a Simple Feedforward Technique http://onsemi.com Prepared by: Dennis Solley ON Semiconductor The NCP3063 Switching Regulator is an improved version of the popular MC34063 switching regulators and is based on a very flexible hysteretic architecture that can be used to create step−down (buck), step−up (boost) and buck−boost voltage regulators. This device can support input and output voltages up to 40 VDC which makes it attractive for a wide array of switching regulator applications, be it boosting a 5 V rail up to 24 V or stepping down a 12 V supply to 5 V or dealing with a wide input voltage from a Lead−Acid battery. The techniques discussed in this application note will assist the designer in optimizing their design to the specific VIN and VOUT requirements of their application and allowing them to improve output ripple performance when they do not require operating the DC−DC converter near the maximum duty cycle of the NCP3063. The block diagram of the NCP3063 controller is shown in Figure 1. NCP3063 NC 8 TSD 1 Switch Collector SET Dominant S R 7 IPK Sense +VCC 6 Comparator − + − + Q 2 S R Q 0.2 V Oscillator CT Comparator Inverting Input 5 1.25 V Reference Regulator + − Switch Emitter SET Dominant 3 Timing Capacitor 4 GND Figure 1. Block Diagram of NCP3063 © Semiconductor Components Industries, LLC, 2007 March, 2007 − Rev. 1 1 Publication Order Number: AND8284/D AND8284/D The oscillator section consists of two current sources; one charging, the other discharging the timing capacitor CT, between two fixed voltage levels. The levels are approximately 500 mV apart. The ratio between the charge current and the discharge current is set within the controller to be 1:6. This ratio creates a fixed duty cycle DMAX of 6/7 or 0.86. Typical operating waveforms, including the timing ramp CT, are illustrated in Figure 2. 1 Feedback Comparator Output 0 1 IPK Comparator Output 0 Timing Capacitor, CT Output Switch 1 0 Nominal Output Voltage Level Output Voltage Startup Operation Figure 2. Typical Operating Waveform 0.42 and a corresponding D = 0.42, a 12 V to 19 V boost application requires a gain of 1.58 resulting in a nominal D = 0.37, while a 12 V to 12 V buck−boost application requires unity gain and D = 0.5. Hence dependent on the application, the ratio of “on pulses” to “off pulses” can be very large or very small, to maintain output regulation against a given set point. In turn, this may result increased output ripple, requiring a large output capacitor. In extreme cases, audible noise generation is possible, if the pulse repetition rate is in the audio band. The addition of a feedforward resistor can help to alleviate these issues. The ramp circuit is modified as illustrated in Figure 3 by the addition of an external current source IFF at the CT pin. This current source, in the simplest case, is created by adding a resistor between VIN and CT. This versatile controller can be configured for buck, boost, buck−boost and also inverting applications. For detailed information regarding controller operation refer to the NCP3063 data sheet. The essentials of the control method can be observed in the waveforms of Figure 2. The output voltage is fed back to the inverting input (Pin 5) of the comparator (Figure 1) via a resistor divider. If the output is above or below the setpoint, the comparator “gates” a series of clock cycles through the power switch. Control of the output voltage is achieved by varying the average number of “on cycles” to the number of “off cycles” in a given time interval. The transfer functions (or gain) VOUT/VIN for buck, boost and buck−boost operation, neglecting circuit losses, are given by the following equations: (eq. 1) Buck Transfer Function + D Boost Transfer Function + 1 (eq. 2) (1 * D ) Buck−Boost Transfer Function + VCC D (1 * D ) ICHARGE (eq. 3) IFF If the value DMAX equal to 0.86 is inserted into the above equations, the maximum gain available for each topology is determined. Maximum buck gain = 0.86 Maximum boost gain = 7.14 Maximum buck−boost gain = 6.14 The maximum gain values indicated above may be considerably more than a particular application requires. For example a 12 V to 5 V buck application requires a gain of VIN IDISCHARGE CT Figure 3. http://onsemi.com 2 AND8284/D Adding an external current will reduce the time it takes to charge the CT capacitor between the ramp’s minimum and maximum thresholds. The design equations relating to the oscillator section are given below. ȍ ICHARGE T OFF + C T * V RAMP ń ȍ I DISCHARGE T ON + C T * V RAMP ń T S + ǒTON ) T OFFǓ D MOD + FS + (eq. 4) (eq. 5) (eq. 7) T OFF (eq. 8) Table 1 shows the corresponding reduction in duty cycle DMOD as a normalized function of the charging and discharging currents flowing into the timing capacitor CT. The table also shows the change in normalized oscillator frequency. Once an optimum duty cycle has been identified and IFF selected, the value of CT can be ratio metrically adjusted to set the design frequency. Once set, the frequency variation against duty cycle is small over a wide range of external charging currents. (eq. 6) T ON 1 TS Table 1. VARIATION OF DUTY CYCLE DMOD AND FREQUENCY FMOD AS A FUNCTION OF NORMALIZED EXTERNAL CURRENT, CHARGING THE TIMING CAPACITOR CT. External Charging Current Internal Charging Current Internal Discharging Current Duty Cycle DMOD Frequency FMOD 0 1 6 0.86 1.00 1 1 5 0.71 1.43 2 1 4 0.66 1.71 3 1 3 0.50 1.71 4 1 2 0.29 1.43 5 1 1 0.14 0.86 http://onsemi.com 3 AND8284/D Practical Example Q1 NSS40500UW3T2G VIN R1 10.7k D2 MBRA340T3 L1 C2 50m/16V D1 MBRA340T3 R4 49 VOUT 68mH R5 200 U1 NCP3063 8 7 NC SWC ISENS SWE 6 5 C1 50m/ 16V 1 2 Q2 NSS40501UW3T2G 3 VCC CT CMPINV GND R6 49 4 Feedforward Resistor R3 20k R2 1.24k C3 3.9n RTN RTN Figure 4. Schematic of a Noninverting Buck−Boost Topology Figure 4 is a schematic of a noninverting buck−boost topology. The input is a nominal 12 VIN while the output is regulated to 12 VOUT. Assuming no circuit losses, the transfer function or gain of this application is unity and the duty cycle determined from the buck boost transfer function is 0.5. Referring to Table 1, a 3:1 ratio for the external charging current to internal charging current would generate a modified duty DMOD of 0.5. However, to accommodate conduction and switching losses in the power components, we will start by selecting a 2:1 ratio, providing a DMOD of 0.66 and modified gain (Equation 3) of 0.66/0.34 or 1.94. The nominal charge and discharge currents for the NCP3063 are listed below: • Charging Current is 260 mA @ 5 V VCC / 25°C and 280 mA @ 40 V VCC / 25°C. • Discharging Current is 1550 mA @ 5 V VCC / 25°C and 1700 mA @ 40V VCC / 25°C. The data above may be verified from measurements of the CT ramp illustrated in Figure 5 before inserting the feedforward resistor R3 in Figure 4. Figure 5. Ramp Waveform CT = 1800 pF, TS = 4.94 mS Rearranging Equation 4, the charge current ICHARGE is given by the expression I CHARGE + C T * DV RAMP ń T ON http://onsemi.com 4 (eq. 9) AND8284/D Substituting the measured values taken from the ramp waveform in Figure 5 into Equation 9, ICHARGE = 1800 pF * 628 mV / 4.18 mS = 270 mA which corresponds to the data above. For DMOD of 0.66, we require an external current of 520 mA. The average ramp voltage from Figure 5 is 0.9 V and VIN is nominally 12 V, hence the value of the feedforward resistor R3 may be determined from the expression (12 V − 0.9 V) /520 mA or 21.3 kW. A preferred value of 20 kW is selected; IFF is then 555 mA. T ON + 2.68 ms T OFF + 2.28 ms T S + ǒTON ) T OFFǓ + 4.96 ms D MOD + FS + T ON T OFF + 0.54 1 + 202 kHz TS ȍ ICHARGE + 555 mA ) 270 mA + 0.825 mA ȍ IDISCHARGE + 1550 mA * 555 mA + 0.995 mA From Table 1, it is apparent that in order to maintain the same switching frequency FS after an external current source is added in circuit, the value of the timing capacitor CT has to be increased by a design factor 1.72 times. Here CT was increased to 3.9 nF. C T * DV RAMP + 3.9 nF * 560 mV + 2.18 10 −9 Substituting the values above into Equations 4 and 5 gives: T ON + 2.64 mS T OFF + 2.19 ms Figure 7. Buck−Boost Output Ripple with Voltage Feedforward Applied T S + ǒTON ) T OFFǓ + 4.83 ms D MOD + FS + T ON TS The output ripple across a 33 mF electrolytic and 20 mF MLCC capacitors in parallel is shown in Figure 7. The output voltage is regulated at 11.9 V. The ripple is 70 mV peak to peak with a repetition rate around 9 kHz. The collector waveform of the NPN transistor Q2 and modified CT ramp are illustrated in Figure 8. It is observed that energy is flowing from primary to secondary for many switching cycles to support the 100 mA output load. The converter was then operated without feedforward at the same switching frequency. The output capacitor bank and the load were identical. The output ripple is shown in Figure 9. + 0.547 1 + 207kHz TS The modified ramp is captured in Figure 6. Figure 6. Modified Ramp Waveform, CT =3.9 nF, IFF = 555 mA Data measured from the ramp waveform in Figure 6 is given below and shows good correlation with the calculated results above. Figure 8. Collector Waveform Q2 with Modified Ramp DMOD http://onsemi.com 5 AND8284/D The collector waveform of the NPN transistor Q2 and DMAX ramp is shown in Figure 10. Here it is evident that the energy flow to support the same 100 mA output is drawn from the input in five switching cycles, during which time the voltage on the output capacitor C2 is increased by 1.2 V. C2 is discharged by the output load for several hundred microseconds before the gate oscillator in the NCP3063 restarts. Conclusion By summing an external current source into the CT pin of the NCP3063, it is possible to optimize the open loop gain of buck, boost or buck boost topologies for any given application. Reducing the controller’s maximum duty cycle of 0.86 to a lower value DMOD allows the power components to be designed for lower stress. Input capacitors, output capacitors, inductor, switches and diodes can all benefit from the DMAX reduction. The effect of output capacitor ripple was investigated in the particular case of a buck−boost topology. It is evident that a large reduction in output capacitor is possible when a single resistor feedforward function is implemented. This technique can also be applied to the MC33063/MC34063 but be aware that the ramp charge and discharge currents are different. Figure 9. Buck Boost Output Ripple Without Feedforward Applied It is evident that the output ripple has increased to 1.2 V peak−to−peak with a repetition rate around 3 kHz and the higher ripple of the output waveform results in the average output voltage being regulated at 12.3 V. Figure 10. Collector Waveform Q2 with DMAX Ramp ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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