NCP3063, NCP3063B, NCV3063 1.5 A, Step−Up/Down/ Inverting Switching Regulators http://onsemi.com The NCP3063 Series is a higher frequency upgrade to the popular MC34063A and MC33063A monolithic DC−DC converters. These devices consist of an internal temperature compensated reference, comparator, a controlled duty cycle oscillator with an active current limit circuit, a driver and a high current output switch. This series was specifically designed to be incorporated in Step−Down, Step−Up and Voltage−Inverting applications with a minimum number of external components. MARKING DIAGRAMS 8 • Operation to 40 V Input Low Standby Current Output Switch Current to 1.5 A Output Voltage Adjustable Frequency Operation of 150 kHz Precision 1.5% Reference New Features: Internal Thermal Shutdown with Hysteresis New Features: Cycle−by−Cycle Current Limiting Pb−Free Packages are Available NCP3063x AWL YYWWG 1 8 1 PDIP−8 P, P1 SUFFIX CASE 626 • Step−Down, Step−Up and Inverting supply applications • High Power LED Lighting • Battery Chargers 8 TSD SET dominant 1 R DFN−8 SUFFIX CASE 488 Q 7 COMPARATOR − + S S Q Rs Vin 0.15 W 6 R OSCILLATOR 0.2 V 5 + COMPARATOR − R2 R1 2.4 kW 3063y ALYW G 2 SET dominant 3 D CT 12 V + Cin 220 mF NCV3063 AWL YYWWG 1 1 NCP3063 V3063 ALYW G 1 Applications 8 1 1 SOIC−8 D SUFFIX CASE 751 Features • • • • • • • 3063x ALYW G 1.25 V REFERENCE REGULATOR 3.9 kW L 47 mH CT 2.2 nF 4 Vout 3.3 V / 800 mA 470 mF Cout + NCP3063x = Specific Device Code x=B A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. Figure 1. Typical Buck Application Circuit © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 1 1 Publication Order Number: NCP3063/D NCP3063, NCP3063B, NCV3063 PIN CONNECTIONS 1 Switch Collector 8 N.C. Switch Emitter 2 7 Ipk Sense Timing Capacitor 3 6 VCC GND 4 5 Comparator Inverting Input (Top View) NCP3063 8 1 TSD N.C. Switch Collector SET dominant R Q S 7 COMPARATOR − + Ipk Sense 2 S Q Switch Emitter SET dominant R 0.2 V OSCILLATOR 6 3 Timing Capacitor CT +VCC COMPARATOR 5 1.25 V REFERENCE REGULATOR + − 4 GND Comparator Inverting Input Figure 2. Block Diagram http://onsemi.com 2 NCP3063, NCP3063B, NCV3063 PIN DESCRIPTION Pin No. Pin Name Description 1 Switch Collector 2 Switch Emitter 3 Timing Capacitor 4 GND 5 Comparator Inverting Input 6 VCC 7 Ipk Sense 8 N.C. Internal Darlington switch collector Internal Darlington switch emitter Timing Capacitor to control the switching frequency Ground pin for all internal circuits Inverting input pin of internal comparator Voltage supply Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak current through the circuit Pin not connected MAXIMUM RATINGS (measured vs. pin 4, unless otherwise noted) Rating Symbol Value Unit VCC pin 6 VCC 0 to +40 V Comparator Inverting Input pin 5 VCII − 0.2 to + VCC V Darlington Switch Collector pin 1 VSWC 0 to +40 V Darlington Switch Emitter pin 2 (transistor OFF) VSWE − 0.6 to + VCC V Darlington Switch Collector to Emitter pin 1−2 VSWCE 0 to +40 V Darlington Switch Current ISW 1.5 A Ipk Sense pin 7 VIPK − 0.2 to VCC + 0.2 V PDIP−8 Thermal Resistance Junction−to−Air RqJA 100 SOIC−8 Thermal Resistance Junction−to−Air RqJA 180 Storage Temperature Range TSTG −65 to +150 °C TJ MAX +150 °C Power Dissipation and Thermal Characteristics °C/W °C/W Maximum Junction Temperature Operating Junction Temperature Range (Note 3) NCP3063 NCP3063B, NCV3063 °C TJ 0 to +70 −40 to +125 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115 Machine Model Method 200 V 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq • PD 4. The pins which are not defined may not be loaded by external signals http://onsemi.com 3 NCP3063, NCP3063B, NCV3063 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified) Symbol Characteristic Conditions Min Typ Max Unit (VPin 5 = 0 V, CT = 2.2 nF, TJ = 25°C) 110 150 190 kHz (Pin 7 to VCC, TJ = 25°C) 5.5 6.0 6.5 − (TJ = 25°C) (Note 6) 165 200 235 mV (ISW = 1.0 A, Pin 2 to GND, TJ = 25°C) (Note 7) 1.0 1.3 V (VCE = 40 V) 0.01 100 mA TJ = 25°C 1.250 OSCILLATOR fOSC IDISCHG / ICHG VIPK(Sense) Frequency Discharge to Charge Current Ratio Current Limit Sense Voltage OUTPUT SWITCH (Note 7) VSWCE(DROP) Darlington Switch Collector to Emitter Voltage Drop IC(OFF) Collector Off−State Current COMPARATOR VTH Threshold Voltage NCP3063 REGLiNE ICII in Threshold Voltage Line Regulation Input Bias Current −1.5 V +1.5 % NCP3063B, NCV3063 −2 +2 % (VCC = 5.0 V to 40 V) −6.0 2.0 6.0 mV (Vin = Vth) −1000 −100 1000 nA 7.0 mA TOTAL DEVICE ICC Supply Current (VCC = 5.0 V to 40 V, CT = 2.2 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = GND, remaining pins open) Thermal Shutdown Threshold 160 °C Hysteresis 10 °C 5. NCP3063: Tlow = 0°C, Thigh = +70°C; NCP3063B, NCV3063: Tlow = −40°C, Thigh = +125°C 6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends on comparator response time and di/dt current slope. See the Operating Description section for details. 7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. 8. NCV prefix is for automotive and other applications requiring site and change control. http://onsemi.com 4 NCP3063, NCP3063B, NCV3063 200 190 180 CT = 2.2 nF TJ = 25°C 180 FREQUENCY (Hz) FREQUENCY (kHz) 160 140 120 100 80 60 160 150 140 130 40 120 20 0 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 7 12 16 21 25 29 34 38 40 Ct, CAPACITANCE (nF) VCC, SUPPLY VOLTAGE (V) Figure 3. Oscillator Frequency vs. Oscillator Timing Capacitor Figure 4. Oscillator Frequency vs. Supply Voltage 2.4 1.25 VCC = 5.0 V IE = 1 A VCC = 5.0 V IC = 1 A 1.20 VOLTAGE DROP (V) 2.2 VOLTAGE DROP (V) 170 2.0 1.8 1.6 1.4 1.15 1.10 1.05 1.2 1.0 −50 0 50 100 1.0 −50 150 50 100 150 TJ, JUNCTION TEMPERATURE (°C) Figure 5. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Temperature Figure 6. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Temperature 2.0 1.5 1.9 1.4 VCC = 5.0 V TJ = 25°C 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.2 0.7 1.1 1.0 0.6 0.5 0 VCC = 5.0 V TJ = 25°C 1.3 VOLTAGE DROP (V) 1.8 VOLTAGE DROP (V) 0 TJ, JUNCTION TEMPERATURE (°C) 0.5 1.0 1.5 0 0.5 1.0 IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 7. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Emitter Current Figure 8. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Collector Current http://onsemi.com 5 1.5 Vth, COMPARATOR THRESHOLD VOLTAGE (V) NCP3063, NCP3063B, NCV3063 0.30 Vipk(sense), CURRENT LIMIT SENSE VOLTAGE (V) 1.30 1.28 1.26 1.24 1.22 1.20 −40 −25 −10 5 20 35 50 65 80 95 110 125 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 −40 −25 −10 TJ, JUNCTION TEMPERATURE (°C) 5 20 ICC, SUPPLY CURRENT (mA) 65 80 95 110 125 Figure 10. Current Limit Sense Voltage vs. Temperature 6.0 5.5 5.0 4.5 4.0 3.5 CT = 2.2 nF Pin 5, 7 = VCC Pin 2 = GND 3.0 2.5 2.0 8.0 50 TJ, JUNCTION TEMPERATURE (°C) Figure 9. Comparator Threshold Voltage vs. Temperature 3.0 35 13 18 23 28 33 38 43 VCC, SUPPLY VOLTAGE (V) Figure 11. Standby Supply Current vs. Supply Voltage http://onsemi.com 6 NCP3063, NCP3063B, NCV3063 INTRODUCTION The NCP3063 is a monolithic power switching regulator optimized for dc to dc converter applications. The combination of its features enables the system designer to directly implement step−up, step−down, and voltage− inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for industrial markets. A representative block diagram is shown in Figure 2. controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the output switch next cycle turning on is inhibited. The feedback comparator will enable the switching immediately when the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be enabled for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. (See AN920/D for more information). Operating Description The NCP3063 is a hysteric, dc−dc converter that uses a gated oscillator to regulate output voltage. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 12. The output voltage waveform shown is for a step−down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle Oscillator The oscillator frequency and off−time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 1 to 6 ratio internal current source and sink, generating a positive going sawtooth waveform at Pin 3. The oscillator peak and valley voltage difference is 500 mV typically. To calculate the CT capacitor value for required oscillator frequency, use the equations found in Figure 13. An Excel based design tool can be found at www.onsemi.com on the NCP3063 product page. 1 Feedback Comparator Output 0 1 IPK Comparator Output 0 Timing Capacitor, CT On Output Switch Off Nominal Output Voltage Level Output Voltage Startup Operation Figure 12. Typical Operating Waveforms http://onsemi.com 7 NCP3063, NCP3063B, NCV3063 Peak Current Sense Comparator With a voltage ripple gated converter operating under normal conditions, output switch conduction is initiated by the Voltage Feedback comparator and terminated by the oscillator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Ipk Current Sense comparator will protect the Darlington output Switch. The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and the Darlington output switch. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 200 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle−by−cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on−time during a given oscillator cycle. Real Vturn−off on Rs Resistor Vturn_off + Vipk(sense) ) Rs @ (t_delay @ dińdt) Typical Ipk comparator response time t_delay is 350 ns. The di/dt current slope is growing with voltage difference on the inductor pins and with decreasing inductor value. It is recommended to check the real max peak current in the application at worst conditions to be sure that the max peak current will never get over the 1.5 A Darlington Switch Current max rating. Thermal Shutdown Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the Output Switch is disabled. The temperature sensing circuit is designed with 10°C hysteresis. The Switch is enabled again when the chip temperature decreases to at least 150°C threshold. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking. I1 di/dt slope Vipk(sense) Real Vturn−off on Rsc resistor Io I through the Darlington Switch Output Switch t_delay The output switch is designed in a Darlington configuration. This allows the application designer to operate at all conditions at high switching speed and low voltage drop. The Darlington Output Switch is designed to switch a maximum of 40 V collector to emitter voltage and current up to 1.5 A. The VIPK(Sense) Current Limit Sense Voltage threshold is specified at static conditions. In dynamic operation the sensed current turn−off value depends on comparator response time and di/dt current slope. APPLICATIONS Figure 13 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3063 can be found at www.onsemi.com. Figures 14 through 22 show the simplicity and flexibility of the NCP3063. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. http://onsemi.com 8 NCP3063, NCP3063B, NCV3063 Step−Down Step−Up Voltage−Inverting Vout ) VF Vin * VSWCE * Vout Vout ) VF * Vin Vin * VSWCE |Vout| ) VF Vin * VSWCE ton toff ton toff (See Notes 9, 10, 11) ton toff ton ton toff f ǒton ) 1Ǔ f ǒton ) 1Ǔ t CT + 381.6 @ fosc CT Iout Ipk (Switch) Iout IL(avg) ) t off 10 *6 IL(avg) f ǒton ) 1Ǔ t off DIL 2 off * 343 @ 10 *12 ǒtton ) 1Ǔ off IL(avg) ) DIL 2 Iout ǒtton ) 1Ǔ off IL(avg) ) DIL 2 RSC 0.20 Ipk (Switch) 0.20 Ipk (Switch) 0.20 Ipk (Switch) L * Vout ǒVin * VSWCE Ǔ ton DIL ǒVin *DIVLSWCEǓ ton ǒVin *DIVLSWCEǓ ton t I [ on out ) DIL @ ESR CO t I [ on out ) DIL @ ESR CO Vripple(pp) DIL Vout Ǹǒ Ǔ 1 8 f CO ǒ 2 ) (ESR) 2 R VTH 2 ) 1 R1 ǒ Ǔ R VTH 2 ) 1 R1 Ǔ ǒ R VTH 2 ) 1 R1 Ǔ The Following Converter Characteristics Must Be Chosen: Vin − Nominal operating input voltage. Vout − Desired output voltage. Iout − Desired output current. DIL − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce converter output current capability. f − Maximum output switch frequency. Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. 9. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 5, 6, 7 and 8. 10. VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V. 11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio. Figure 13. Design Equations http://onsemi.com 9 NCP3063, NCP3063B, NCV3063 R201 0R15 8 7 6 5 +VIN = +12 V 1 J201 C201 0.1 mF + C202 220 mF / 50 V U201 N.C. SWC SWE IPK TCAP VCC COMP GND 1 2 3 4 +VOUT = +3.3 V / 800 mA 47 mH L201 1 C203 2.2 nF NCP3063 C206 D201 1N5819 0.1 mF J203 + C205 470 mF / 25 V J204 1 GND J202 R203 1 GND 3K9 ±1% R202 2K4 ±1% Figure 14. Typical Buck Application Schematic Value of Components Name Value Name Value L201 47 mH, Isat > 1.5 A R201 150 mW, 0.5 W D201 1 A, 40 V Schottky Rectifier R202 2.40 kW C202 220 mF, 50 V, Low ESR R203 3.90 kW C205 470 mF, 25 V, Low ESR C201 100 nF Ceramic Capacitor C203 2.2 nF Ceramic Capacitor C202 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 9 V to 12 V, Io = 800 mA 8 mV Load Regulation Vin = 12 V, Io = 80 mA to 800 mA 9 mV Output Ripple Vin = 12 V, Io = 40 mA to 800 mA ≤ 85 mVpp Efficiency Vin = 12 V, Io = 400 mA to 800 mA > 73% Short Circuit Current Vin = 12 V, Rload = 0.15 W 1.25 A 76 EFFICIENCY (%) 74 72 70 68 66 64 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (Adc) Figure 16. Efficiency vs. Output Current for the Buck Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C Figure 15. Buck Demoboard Layout http://onsemi.com 10 NCP3063, NCP3063B, NCV3063 100 mH U101 N.C. SWC 1 SWE 2 IPK 3 VCC TCAP COMP GND 4 L101 R101 0R15 8 7 6 5 +VIN = +12 V 1 J101 C101 0.1 mF + C102 470 mF / 25 V D101 +VOUT = +24 V / 350 mA 1N5819 1 J103 C106 C103 0.1 mF 2.2 nF NCP3063 + C105 330 mF / 50 V J104 1 GND J102 R103 1 GND R102 1K0 ±1% 18K0 ±1% Figure 17. Typical Boost Application Schematic Value of Components Name Value Name Value L101 100 mH, Isat > 1.5 A R101 150 mW, 0.5 W D101 1 A, 40 V Schottky Rectifier R102 1.00 kW C102 470 mF, 25 V, Low ESR R103 18.00 kW C105 330 mF, 50 V, Low ESR C101 100 nF Ceramic Capacitor C103 2.2 nF Ceramic Capacitor C106 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 9 V to 15 V, Io = 250 mA 2 mV Load Regulation Vin = 12 V, Io = 30 mA to 350 mA 5 mV Output Ripple Vin = 12 V, Io = 10 mA to 350 mA ≤ 350 mVpp Efficiency Vin = 12 V, Io = 50 mA to 350 mA > 85.5% 90 89 EFFICIENCY (%) 88 87 86 85 84 83 82 81 80 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 OUTPUT LOAD (Adc) Figure 19. Efficiency vs. Output Current for the Boost Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C Figure 18. Boost Demoboard Layout http://onsemi.com 11 NCP3063, NCP3063B, NCV3063 R501 0R15 8 7 6 5 +VIN = +5 V 1 J501 C501 0.1 mF + U501 N.C. SWC SWE IPK TCAP VCC COMP GND 1 2 3 4 NCP3063 C502 330 mF / 25 V J502 C503 L501 2.2 nF 22 mH D501 1N5819 VOUT = −12 V / 100 mA R503 1 J503 1 1K96 ±1% GND C506 R502 16K9 ±1% C505 + 470 mF / 35 V 0.1 mF 1 J504 GND Figure 20. Typical Voltage Inverting Application Schematic Value of Components Name Value Name Value L501 22 mH, Isat > 1.5 A R501 150 mW, 0.5 W D501 1 A, 40 V Schottky Rectifier R502 16.9 kW C502 330 mF, 25 V, Low ESR R503 1.96 kW C505 470 mF, 35 V, Low ESR C501 100 nF Ceramic Capacitor C503 2.2 nF Ceramic Capacitor C506 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 4.5 V to 6 V, Io = 50 mA 1.5 mV Load Regulation Vin = 5 V, Io = 10 mA to 100 mA 1.6 mV Output Ripple Vin = 5 V, Io = 0 mA to 100 mA ≤ 300 mVpp Efficiency Vin = 5 V, Io = 100 mA 49.8% Short Circuit Current Vin = 5 V, Rload = 0.15 W 0.885 A 52 EFFICIENCY (%) 50 48 46 44 42 40 38 36 0 20 40 60 80 100 OUTPUT LOAD (mAdc) Figure 22. Efficiency vs. Output Current for the Voltage Inverting Demo Board at Vin = +5 V, Vout = −12 V, TA = 255C Figure 21. Voltage Inverting Demoboard Layout http://onsemi.com 12 NCP3063, NCP3063B, NCV3063 ORDERING INFORMATION Package Shipping † NCP3063PG PDIP−8 (Pb−Free) 50 Units / Rail NCP3063BPG PDIP−8 (Pb−Free) 50 Units / Rail NCP3063DR2G SOIC−8 (Pb−Free) 2500 Units / Tape & Reel NCP3063BDR2G SOIC−8 (Pb−Free) 2500 Units / Tape & Reel NCP3063 DFN−8 (Pb−Free) TBD NCV3063PG PDIP−8 (Pb−Free) 50 Units / Rail NCV3063DR2G SOIC−8 (Pb−Free) 2500 Units / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NCV prefix is for automotive and other applications requiring site and change control. http://onsemi.com 13 NCP3063, NCP3063B, NCV3063 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCP3063, NCP3063B, NCV3063 PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626−05 ISSUE L 8 5 −B− 1 4 F −A− NOTE 2 L C J −T− N SEATING PLANE D H M K G 0.13 (0.005) M T A M B M http://onsemi.com 15 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. AC IN DC + IN DC − IN AC IN GROUND OUTPUT AUXILIARY VCC INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 NCP3063, NCP3063B, NCV3063 PACKAGE DIMENSIONS 8 PIN DFN, 4x4 CASE 488AF−01 ISSUE B A D 8X B 8X PIN ONE IDENTIFICATION L ÇÇ Ç ÇÇ Ç ÇÇ Ç K 1 8 E 0.15 C 2X 2X 0.15 C 0.10 C 8X 0.08 C SEATING PLANE A1 8X NOTE 3 E2 0.05 C ÇÇÇ Ç DIM A A1 A3 b D D2 E E2 e K L e 0.10 C A B TOP VIEW D2 4 5 b NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. BOTTOM VIEW MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 −−− 0.30 0.50 A (A3) C SIDE VIEW SOLDERING FOOTPRINT* 4.30 8X 2.21 2.39 ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ 1 8X 0.35 0.63 DIMENSIONS: MILLIMETERS 0.40 0.80 PITCH 2.75 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 16 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP3063/D