Freescale Semiconductor, Inc. Data Sheet: Technical Data Document Number: SCMIMX6DQ Rev. 0, 02/2016 SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products 1. Introduction Freescale Single Chip System Modules (SCMs) are a suite of highly integrated products in an ultra-small form factor. The first member of this portfolio, the Freescale SCM-i.MX 6Dual/6Quad, drastically reduces time to market by providing a solution that minimizes design time. We’ve integrated and validated dual- and quad-core performance, the power management system, flash memory, and over a hundred passive system components all in the size of a dime. The SCM-i.MX 6Dual/6Quad is enabled with the standard i.MX 6Dual/6Quad multimedia, connectivity and security features including High Assurance Boot, cryptographic cipher engines, random number generator, and tamper detection. It is a scalable solution intended for use in a wide variety of consumer and industrial applications. The SCM-i.MX 6Dual/6Quad speeds and eases development time by addressing technology challenges such as design of DDR and power management. Our single chip module i.MX 6Dual/6Quad consists of the i.MX 6Dual/6Quad applications processor, PF0100 (PMIC) for power management, 16 MB SPI NOR, over a hundred discrete components, and is enabled for 1 or 2 GB LPDDR2 via PoP assembly. Contents 1. 2. 3. 4. 5. 6. 7. 8. Introduction........................................................................ 1 1.1. Ordering information .............................................. 2 1.2. Features ................................................................... 3 1.3. References............................................................... 8 Architectural Overview ...................................................... 9 2.1. Block Diagram ........................................................ 9 Modules List .................................................................... 10 3.1. Special Signal Considerations ............................... 10 Electrical Characteristics.................................................. 11 4.1. Chip-Level Conditions .......................................... 11 Power Supplies Requirements and Restrictions ............... 12 5.1. Power-Up Sequences ............................................ 12 5.2. Power-Down Sequences ....................................... 12 5.3. Power Supplies Usage........................................... 12 5.4. Boot Configuration ............................................... 12 Boot Mode Configuration ................................................ 14 6.1. Boot Mode Configuration Pins ............................. 14 6.2. Boot Devices Interfaces Allocation ...................... 14 Package Information ........................................................ 15 7.1. Signal List ............................................................. 15 7.2. Critical Signals...................................................... 22 7.3. Ball Map ............................................................... 25 7.4. Package Drawings................................................. 27 Revision History .............................................................. 29 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2016 Freescale Semiconductor, Inc. All rights reserved. 1.1. Ordering information Figure 1. Part Number Nomenclature The table below shows examples of orderable part numbers. Table 1-1 Part Numbers Part Number CPU MSCMMX6DZDK08AB i.MX 6Dual MSCMMX6QZDK08AB i.MX 6Quad Part Differentiator 16MB SPI NOR, PF0100 16MB SPI NOR, PF0100 Speed Grade Temperature Grade Package 800 MHz Commercial: 0 to 85C 800 MHz Commercial: 0 to 85C SCM 14x17mm P0.65mm 2D PoP SCM 14x17mm P0.65mm 2D PoP SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 2 Freescale Semiconductor, Inc. 1.2. Features 1.2.1. i.MX 6Dual/6Quad Features The i.MX 6Dual/6Quad processors are based on ARM® Cortex®-A9 MPCore platform, which has the following features: • ARM Cortex-A9 MPCore 4xCPU processor (with TrustZone®) • The core configuration is symmetric, where each core includes: — 32 Kbyte L1 Instruction Cache — 32 Kbyte L1 Data Cache — Private Timer and Watchdog — Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The ARM Cortex-A9 MPCore complex includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • Snoop Control Unit (SCU) • 1 MB unified I/D L2 cache, shared by two/four cores • Two Master AXI (64-bit) bus interfaces output of L2 cache • Frequency of the core (including Neon and L1 cache) as per Table 4-3 • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: — Boot ROM, including HAB (96 KB) — Internal multimedia / shared, fast access RAM (OCRAM, 256 KB) — Secure/non-secure RAM (16 KB) • External memory interfaces: — 32-bit LPDDR2, supporting DDR interleaving mode, or fixed 2x32. — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bits. SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 3 — 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Hard Disk Drives—SATA II, 3.0 Gbps • Displays—Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps • Camera sensors: — Parallel Camera port (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes. Each i.MX 6Dual/6Quad processor has four lanes. • Expansion cards: — Four MMC/SD/SDIO card ports all supporting: • – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: • – One HS host with integrated High Speed PHY – Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY Expansion PCI Express port (PCIe) v2.0 one lane: — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. • Miscellaneous IPs and interfaces: — SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 4 Freescale Semiconductor, Inc. — ESAI is capable of supporting audio sample frequencies up to 260kHz in I2S mode with 7.1 multi-channel outputs — Five UARTs, up to 4.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while others four supports 4wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature • Support DVFS techniques for low power modes • Use Software State Retention and Power Gating for ARM and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). 1 SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 5 The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H (2 IPUs) • GPU3Dv4—3D Graphics Processing Unit (OpenGL ES 2.0) version 4 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) • GPUVG—OpenVG 1.1 Graphics Processing Unit • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and True and Pseudo Random Number Generator (NIST certified) • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization. 1.2.2. PF0100Z Features • Input voltage range to PMIC: 2.8 - 4.5 V • Buck regulators — Four to six channel configurable – SW1A/B/C, 4.5 A (single); 0.3 to 1.875 V – SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 to 1.875 V – SW2, 2.0 A; 0.4 to 3.3 V – SW3A/B, 2.5 A (single/dual); 0.4 to 3.3 V – SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V – SW4, 1.0 A; 0.4 to 3.3 V – SW4, VTT mode provide DDR termination at 50% of SW3A — Dynamic voltage scaling — Modes: PWM, PFM, APS SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 6 Freescale Semiconductor, Inc. — Programmable output voltage — Programmable current limit — Programmable soft start — Programmable PWM switching frequency — Programmable OCP with fault interrupt • Boost regulator — SWBST, 5.0 to 5.15 V, 0.6 A, OTG support — Modes: PFM and Auto — OCP fault interrupt • LDOs — Six user programmable LDO – VGEN1, 0.80 to 1.55 V, 100 mA – VGEN2, 0.80 to 1.55 V, 250 mA – VGEN3, 1.8 to 3.3 V, 100 mA – VGEN4, 1.8 to 3.3 V, 350 mA – VGEN5, 1.8 to 3.3 V, 100 mA NOTE VGEN5 power characteristics are modified from what is displayed in Table 106 of the MMPF0100 datasheet. SCM-specific tolerances are ±5%, rather than ± 3% as presented in the table. – VGEN6, 1.8 to 3.3 V, 200 mA — Soft start — LDO/Switch supply – • VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400uA DDR memory reference voltage — VREFDDR, 0.6 to 0.9 V, 10 mA • 16 MHz internal master clock • OTP(One time programmable) memory for device configuration — User programmable start-up sequence and timing • Battery backed memory including coin cell charger • I2C interface • User programmable Standby, Sleep, and Off modes SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 7 1.3. References This document is intended to be a companion to the data sheets of the following integrated parts: a) Freescale i.MX 6Dual/6Quad (Document Number: IMX6DQCEC) b) Freescale MMPF0100 (Document Number: MMPF0100Z) c) SPI NOR (N25Q128A13) d) LPDDR2 - PoP Footprint for 12mm x 12mm FBGA216 (up to 2GB) 1.d.1. Part validation was done using Micron 1GB (P/N: MT42L128M64D2LL-25) and 2GB (P/N: MT42L256M64D4LL-25) SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 8 Freescale Semiconductor, Inc. 2. Architectural Overview The following subsection provides an architectural overview of the SCM-i.MX 6Dual/6Quad. 2.1. Block Diagram Figure 2. SCM-i.MX 6Dual/6Quad Block Diagram SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 9 3. Modules List Table 3-1 Modules List Block Name Description/Notes i.MX 6Dual/6Quad Freescale i.MX 6Dual/6Quad Applications Processor. Fully functional as a normal i.MX 6Dual/6Quad except the MLB bus is disabled and not pinned out. MMPF0100 Power management IC requires only a single supply and can provide power and voltage references to entire SCM. Refer to section 4 for electrical details. SPI NOR 16 megabytes of SPI NOR which is fully available for user programming. LPDDR2 PoP Interface Interface to support LPDDR2 (1GB or 2GB) in PoP configuration using a 12mm x 12mm FBGA216 footprint. 109 passives for decoupling capacitors and reference resistors. Discrete Components Table 3-2 Recommended Memory Part Number Description MT42L128M64D2LL-25 Micron LPDDR2, 1GB MT42L256M64D4LL-25 Micron LPDDR2, 2GB Note: Micron is the only recommended memory solution for SCM. 3.1. Special Signal Considerations The figure below shows critical internal connections, pull-ups and pulldowns. Figure 3. SCM-i.MX 6Dual/6Quad Critical Internal Connections Note: DDR_VREF is connected internally to the LPDDR2 memory through one of the PoP landing pads. SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 10 Freescale Semiconductor, Inc. 4. Electrical Characteristics 4.1. Chip-Level Conditions 4.1.1. Absolute Max Ratings Table 4-1 Absolute Max Ratings Parameter Description Symbol Min Max Unit PMIC System Supply Voltage Range PMIC_VIN -0.3 4.8 V Temperature range (storage) T_storage -40 150 C 4.1.2. Thermal Resistance Table 4-2 provides the FO-WLP thermal resistance data. Table 4-2 FO-WLP Thermal Resistance Data Parameter Description Junction to Ambient 1,6 Test Condition Symbol Value Unit RθJA 36.5 °C/W RθJA 19.9 °C/W RθJMA 27.7 °C/W RθJMA 16.1 °C/W - RθJB 6.6 °C/W - ΨJT 2.9 °C/W 2 Single-layer board (1s); natural convection 2 Four-layer board (2s2p); natural convection Junction to Ambient 1,6 Single-layer board (1s); air flow 200ft/min Four-layer board (2s2p); air flow 200ft/min 1,4,6 Junction to Board Junction to top characterization 1,5,6 parameter 3 3 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 6 Values reported are modeled and based upon a summation of power dissipation of multiple die within the package. Junction temperatures will vary between die according to power ratios and use case. 4.1.3. Operating Ranges Table 4-3 Operating Ranges Parameter Description PMIC System Supply Voltage Range SPI NOR Flash Supply Voltage Range Junction Temperature (standard commercial) Symbol PMIC_VIN NVCC_EIM0_NOR Tj Min Max Unit 3.6 4.5 V 2.775 3.6 V 0 85 C SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 11 5. Power Supplies Requirements and Restrictions SCM-specific power-up sequence requirements are shown in SCM-IMX6DQHUG. 5.1. Power-Up Sequences Must follow the i.MX 6Dual/6Quad consumer datasheet (Document Number: IMX6DQCEC) recommendations for power up. The internal PMIC simplifies power sequence design. 5.2. Power-Down Sequences Must follow the i.MX 6Dual/6Quad consumer datasheet (Document Number: IMX6DQCEC) recommendations for power down. 5.3. Power Supplies Usage Must follow the i.MX 6Dual/6Quad consumer datasheet (Document Number: IMX6DQCEC) recommendations for power supply usage. 5.4. Power Supplies Restrictions DDR_1V2 and DDR_1V2_SW3AFB (switcher 3 feedback pin) are internally connected for dedicated LPDDR2 usage with SW3. SW3 cannot be used to supply anything else but the LPDDR2. 5.5. Boot Configuration 5.5.1. OTP PMIC Table 5-1 OTP Fuse Map Registers Default Configuration Pre-programmed OTP Configuration Program code (hex) Intended Use SW1AB_VOLT 1.375V 1.375V 2B VDDSOC SW1AB_SEQ 1 2 02 SW1AB CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 05 SW1C_VOLT 1.375 1.375V 00 SW1C_SEQ 1 2 02 SW1C CONFIG Independent, 2.0 MHz Independent, 2.0 MHz 00 SW2_VOLT 3.0V 3.15V 6F SW2_SEQ 2 1 01 SW2 CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 01 SW3A_VOLT 1.5V 1.2V 20 SW3A_SEQ 3 4 04 VDDARM VDDHIGH_IN DDR 1.2V SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 12 Freescale Semiconductor, Inc. Registers Default Configuration Pre-programmed OTP Configuration Program code (hex) SW3A CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 05 SW3B_VOLT 1.5V 1.2V 20 SW3B_SEQ 3 4 04 SW3B CONFIG Single Phase, 2.0 MHz Single Phase, 2.0 MHz 01 SW4_VOLT 1.8V 1.8V 54 SW4_SEQ 3 4 04 SW4_CONFIG No VTT, 2.0MHz No VTT, 2.0 MHz 01 SWBST_VOLT - - 00 SWBST_SEQ - 4 04 VSNVS_VOLT 3.0V 3.0V 06 VREFDDR_SEQ 3 4 04 VGEN1_VOLT - - 00 VGEN1_SEQ - - 00 VGEN2_VOLT 1.5V - 00 VGEN2_SEQ 2 - 00 VGEN3_VOLT - - 00 VGEN3_SEQ - - 00 VGEN4_VOLT 1.8V - 00 VGEN4_SEQ 3 - 00 VGEN5_VOLT 2.5V - 00 VGEN5_SEQ 3 - 00 VGEN6_VOLT 2.8V - 00 VGEN6_SEQ 3 - 00 1.0ms 1.0ms 01 6.25 mV/us 12.5mV/us 00 Level sensitive Level sensitive 00 RESETBMCU in Default Mode 00 PU CONFIG1, SEQ_CLK_SPEED PU CONFIG2, SWDVS_CLK PU CONFIG3, PWRON PG EN Intended Use DDR 1.2V DDR 1.8V Customer VDD_SNVS_IN Customer Customer Customer Customer Customer Customer Note: 1. Refer to application notes AN4714 (Features of Voltage Regulators in the MMPF0100) and AN4536 (MMPF0100 OTP Programming Instructions) for further usage instructions. 2. The OTP registers for regulators which default to (OFF) are free to be programmed according to customer needs. 3. The OTP Lock bit is not programmed from factory. 4. Freescale not responsible for device issues caused by customer fuse programming. SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 13 6. Boot Mode Configuration 6.1. Boot Mode Configuration Pins Refer to the i.MX 6Dual/6Quad consumer datasheet (Document Number: IMX6DQCEC). 6.2. Boot Devices Interfaces Allocation Not limited to booting from internal SPI NOR. Refer to the i.MX 6Dual/6Quad consumer datasheet (Document Number: IMX6DQCEC). SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 14 Freescale Semiconductor, Inc. 7. Package Information 7.1. Signal List Table 7-1 Signal List Ball Name BOOT_MODE0 BOOT_MODE1 CLK1_N CLK1_P CLK2_N CLK2_P CSI_CLK0M CSI_CLK0P CSI_D0M CSI_D0P CSI_D1M CSI_D1P CSI_D2M CSI_D2P CSI_D3M CSI_D3P CSI0_DAT10 CSI0_DAT11 CSI0_DAT12 CSI0_DAT13 CSI0_DAT14 CSI0_DAT15 CSI0_DAT16 CSI0_DAT17 CSI0_DAT18 CSI0_DAT19 CSI0_DAT4 CSI0_DAT5 CSI0_DAT6 CSI0_DAT7 CSI0_DAT8 CSI0_DAT9 CSI0_DATA_EN CSI0_MCLK CSI0_PIXCLK Ball U11 V12 U18 U17 W19 W20 N20 N19 R20 R19 P19 P20 M19 M20 L20 L19 H17 H18 J17 J18 K17 K16 N16 M18 L17 M17 E17 E18 F17 F18 G17 G18 D18 C18 C17 Power Group VDD_SNVS_IN VDD_SNVS_IN VDD_HIGH_CAP VDD_HIGH_CAP VDD_HIGH_CAP VDD_HIGH_CAP NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI NVCC_CSI Comments SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 15 Ball Name CSI0_VSYNC DI0_DISP_CLK DI0_PIN15 DI0_PIN2 DI0_PIN3 DI0_PIN4 DISP0_DAT0 DISP0_DAT1 DISP0_DAT10 DISP0_DAT11 DISP0_DAT12 DISP0_DAT13 DISP0_DAT14 DISP0_DAT15 DISP0_DAT16 DISP0_DAT17 DISP0_DAT18 DISP0_DAT19 DISP0_DAT2 DISP0_DAT20 DISP0_DAT21 DISP0_DAT22 DISP0_DAT23 DISP0_DAT3 DISP0_DAT4 DISP0_DAT5 DISP0_DAT6 DISP0_DAT7 DISP0_DAT8 DISP0_DAT9 DSI_CLK0M DSI_CLK0P DSI_D0M DSI_D0P DSI_D1M DSI_D1P EIM_A16 EIM_A17 EIM_A18 EIM_A19 Ball D17 A4 A2 B4 B3 A3 D5 C5 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9 B5 D10 C10 B10 A10 A5 D6 C6 B6 A6 D7 C7 P18 P17 R17 R18 N17 N18 H1 H4 J2 J3 Power Group NVCC_CSI NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_LCD NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_MIPI NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 Comments SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 16 Freescale Semiconductor, Inc. Ball Name EIM_A20 EIM_A21 EIM_A22 EIM_A23 EIM_A24 EIM_A25 EIM_BCLK EIM_CS0 EIM_CS1 EIM_D16_NOR EIM_D17_NOR EIM_D18_NOR EIM_D19 EIM_D20 EIM_D21 EIM_D22 EIM_D23 EIM_D24 EIM_D25 EIM_D26 EIM_D27 EIM_D28 EIM_D29 EIM_D30 EIM_D31 EIM_DA0 EIM_DA1 EIM_DA10 EIM_DA11 EIM_DA12 EIM_DA13 EIM_DA14 EIM_DA15 EIM_DA2 EIM_DA3 EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 Ball J4 K1 K2 K3 K4 R5 B1 H3 H2 V3 U4 U3 T4 T3 R4 P3 P4 T5 N3 M4 M3 L4 L3 L2 L1 E1 F4 D2 D4 C4 B2 C2 C3 F2 F3 E2 D1 E4 E3 C1 Power Group Comments NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 NVCC_EIM0 NVCC_EIM2 NVCC_EIM1 NVCC_EIM1 NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 17 Ball Name EIM_DA9 EIM_EB0 EIM_EB1 EIM_EB2_NOR EIM_EB3 EIM_LBA EIM_OE EIM_RW EIM_WAIT ENET_CRS_DV ENET_MDC ENET_MDIO ENET_REF_CLK ENET_RX_ER ENET_RXD0 ENET_RXD1 ENET_TX_EN ENET_TXD0 ENET_TXD1 GPIO_0 GPIO_1 GPIO_16 GPIO_17 GPIO_18_PMIC_INTB GPIO_19 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 HDMI_CLKM HDMI_CLKP HDMI_D0M HDMI_D0P HDMI_D1M HDMI_D1P HDMI_D2M Ball D3 G3 G2 V4 N4 F1 G1 G4 F5 D11 D12 C12 C13 C11 A11 B11 D13 A12 B12 E16 E15 M15 R16 AD12 P16 D16 A19 F16 G16 H16 J16 L16 M16 K19 K20 J19 J20 G19 G20 F19 Power Group Comments NVCC_EIM2 NVCC_EIM2 NVCC_EIM2 NVCC_EIM0_NOR NVCC_EIM0_NOR NVCC_EIM1 NVCC_EIM1 NVCC_EIM1 NVCC_EIM2 NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_ENET NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO HDMI_VPH HDMI_VPH HDMI_VPH HDMI_VPH HDMI_VPH HDMI_VPH HDMI_VPH SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 18 Freescale Semiconductor, Inc. Ball Name HDMI_D2P HDMI_HPD JTAG_MOD JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_B KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL3_PMIC_SCL KEY_COL4 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3_PMIC_SDA KEY_ROW4 LVDS0_CLK_N LVDS0_CLK_P LVDS0_TX0_N LVDS0_TX0_P LVDS0_TX1_N LVDS0_TX1_P LVDS0_TX2_N LVDS0_TX2_P LVDS0_TX3_N LVDS0_TX3_P LVDS1_CLK_N LVDS1_CLK_P LVDS1_TX0_N LVDS1_TX0_P LVDS1_TX1_N LVDS1_TX1_P LVDS1_TX2_N LVDS1_TX2_P LVDS1_TX3_N LVDS1_TX3_P NANDF_ALE NANDF_CLE Ball F20 K18 U19 T17 V18 V17 T18 T16 E12 E13 C14 W13 C15 E11 F14 D14 W12 D15 B19 B20 E19 E20 D19 D20 C19 C20 A18 B18 A16 B16 A17 B17 B15 A15 B14 A14 A13 B13 U15 T15 Power Group HDMI_VPH HDMI_VPH NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_JTAG NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_GPIO NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_LVDS_2P5 NVCC_NANDF NVCC_NANDF Comments SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 19 Ball Name NANDF_CS0 NANDF_CS1 NANDF_CS2 NANDF_CS3 NANDF_D0 NANDF_D1 NANDF_D2 NANDF_D3 NANDF_D4 NANDF_D5 NANDF_D6 NANDF_D7 NANDF_RB0 NANDF_WP_B NOR_HOLD_B NOR_W_B ONOFF PCIE_RXM PCIE_RXP PCIE_TXM PCIE_TXP RGMII_RD0 RGMII_RD1 RGMII_RD2 RGMII_RD3 RGMII_RX_CTL RGMII_RXC RGMII_TD0 RGMII_TD1 RGMII_TD2 RGMII_TD3 RGMII_TX_CTL RGMII_TXC RTC_XTALI RTC_XTALO SATA_RXM SATA_RXP SATA_TXM SATA_TXP SD1_CLK Ball T14 Y16 W16 U16 R13 T13 R12 T12 R11 T11 R10 T10 U14 V16 V13 AA13 AD13 Y20 Y19 AA19 AA20 N1 N2 M1 M2 P2 P1 T1 T2 R1 R2 U2 U1 V19 V20 AE17 AD17 AE18 AD18 AE14 Power Group NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_EIM0 NVCC_EIM0 VDD_SNVS_IN PCIE_VPH PCIE_VPH PCIE_VPH PCIE_VPH NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII NVCC_RGMII VDD_SNVS_CAP VDD_SNVS_CAP SATA_VPH SATA_VPH SATA_VPH SATA_VPH NVCC_SD1 Comments SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 20 Freescale Semiconductor, Inc. Ball Name SD1_CMD SD1_DAT0 SD1_DAT1 SD1_DAT2 SD1_DAT3 SD2_CLK SD2_CMD SD2_DAT0 SD2_DAT1 SD2_DAT2 SD2_DAT3 SD3_CLK SD3_CMD SD3_DAT0 SD3_DAT1 SD3_DAT2 SD3_DAT3 SD3_DAT4 SD3_DAT5 SD3_DAT6 SD3_DAT7 SD3_RST SD4_CLK SD4_CMD SD4_DAT0 SD4_DAT1 SD4_DAT2 SD4_DAT3 SD4_DAT4 SD4_DAT5 SD4_DAT6 SD4_DAT7 SYS_POR_B SYS_PWRON SYS_STBY_REQ TAMPER TEST_MODE USB_H1_DN USB_H1_DP USB_OTG_CHD_B Ball AD14 AE16 AD16 AE15 AD15 AB13 AC13 AB14 AB12 AC12 AC14 AC17 AC16 AC18 AB17 AB18 AA17 Y17 Y18 W17 W18 AB16 P9 N9 N8 P8 N7 P7 N6 P6 N5 P5 AE12 AE13 AB15 U13 R9 AD20 AD19 AB19 Power Group NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD1 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD2 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_SD3 NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF NVCC_NANDF VDD_SNVS_IN VDD_SNVS_IN VDD_SNVS_IN VDD_SNVS_IN VDD_SNVS_IN VDD_USB_CAP VDD_USB_CAP VDD_USB_CAP Comments SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 21 Ball Name USB_OTG_DN USB_OTG_DP XTALI XTALO Ball AC19 AC20 T19 T20 Power Group VDD_USB_CAP VDD_USB_CAP NVCC_PLL NVCC_PLL Comments 7.2. Critical Signals The table below shows the differences between the ball map of the i.MX6 Dual and the SCM-i.MX 6Dual/6Quad. Table 7-2 Signal Name differences from i.MX6 Dual SCM-i.MX 6Dual/6Quad Ball Name i.MX6 Dual Ball Remarks Ball Name EIM_D16_NOR V3 EIM_D16 connected to SPI NOR through a 33Ohm resistor EIM_D17_NOR U4 EIM_D17 Connected to SPI NOR EIM_D18_NOR U3 EIM_D18 Connected to SPI NOR EIM_EB2_NOR V4 EIM_EB2 Connected to SPI NOR GPIO_18_PMIC_INTB AD12 GPIO_18 i.MX 6Dual/6QuadQ (GPIO18) connected to PMIC (INTB) KEY_COL3_PMIC_SCL W13 KEY_COL3 i.MX6DQ (KEY_COL3) tied to PMIC (SCL) KEY_ROW3_PMIC_SDA W12 KEY_ROW3 i.MX6DQ (KEY_ROW3) tied to PMIC (SDA) NOR_HOLD_B V13 SPI NOR HOLD_B NOR_W_B AA13 SPI NOR W_B PMIC_ICTEST Y8 PMIC ICTEST PMIC_SDWNB Y13 PMIC SDWNB SYS_POR_B AE12 POR_B i.MX6DQ (POR_B) connected to PMIC (RESETBMCU) SYS_PWRON AE13 PMIC_ON_REQ SYS_STBY_REQ AB15 – PMIC_STBY_REQ i.MX6DQ (PMIC_ON_REQ) connected to PMIC (PWRON) i.MX6DQ (PMIC_STBY_REQ) connected to PMIC (STANDBY) CSI_REXT Grounded internally DSI_REXT Grounded internally FA_ANA Grounded internally HDMI_REF Grounded internally MLB_CN Not pinned out. MLB_CP Not pinned out. MLB_DN Not pinned out. MLB_DP Not pinned out. MLB_SN Not pinned out. MLB_SP Not pinned out. PCIE_REXT Grounded internally SATA_REXT Grounded internally ZQPAD Tied to ground through 240Ohm resistor. – – – – – – – – – – – – – – – – – – – – – – – – – SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 22 Freescale Semiconductor, Inc. The table below shows the device list for ground, power, sense, and reference contact signals Table 7-3 Supply Signal List for i.MX6 Dual Supply Name Balls DDR_1V2 DDR_1V2_SW3AFB DDR_1V8 GPANAIO E5, E9, E14, V15 W8 V5 U12 A1, C16, U9, V6, W4, W9, Y4, Y5, E10, E6, E7, E8, F10, F11, F6, F7, F8, A20, F9, G10, G11, G12, G14, G6, G7, G9, H10, H11, AA12, H12, H14, H20, H9, J1, J10, J11, J12, J13, J14, AA14, J7, J8, J9, K10, K11, K12, K7, K8, K9, L10, AA15, L11, L12, L18, L7, L8, L9, R3, R6, R7, R8, AA16, U20, V10, V11, V14, V2, W11, W14, W15, Y12, Y14, AA18, Y15, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AB11, AB3, AC15, AB4, AB5, AB6, AB7, AB8, AB9, AC4, AC5, AC6, AC7, AE20, AC8, AC9, AE1, T6, T7, T8, T9, U6, U7, U8 H19 L14 K14 Y11 H15 L5 K5 J5 G5 G15 P15 H5 F15 M14 P10 R14 M5 M6 N10 P11 N15 N12 GND HDMI_DDCCEC HDMI_VP HDMI_VPH LICELL NVCC_CSI NVCC_EIM0_NOR NVCC_EIM1 NVCC_EIM2 NVCC_ENET NVCC_GPIO NVCC_JTAG NVCC_LCD NVCC_LVDS2P5 NVCC_MIPI NVCC_NANDF NVCC_PLL_OUT NVCC_RGMII NVCC_SD1 NVCC_SD2 NVCC_SD3 PCIE_VP PCIE_VPH Remark Test signal. Should be unconnected. LICELL output from PMIC EIM0 domain shared with the SPI NOR. SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 23 Supply Name PCIE_VPTX PMIC_VCOREREF PMIC_VDDOTP Balls PMIC_VIN SATA_VP SATA_VPH SW1ABFB SW1ABLX SW1CFB SW1CLX SW2LX SW3ABLX SW4LX SWBSTFB SWBSTIN SWBSTLX SYS_SW2FB_VIN2 SYS_SW4FB_VIN1 N14 AD9 Y9 AC10, AE11, AE2, AE3, V7, V8, AC11, AC2, AC3, AD10, AD11, AD2, AD3, AE10 N13 N11 AE9 AD7, AD8, AE6, AE7, AE8 AE5 AD4, AD5, AD6, AE4 W1, W2, W3, Y1, Y2, Y3 W6, W7, Y6, Y7 AA1, AA2, AB2 Y10 AB10 AA10, AA11 V1 AB1 SYS_VSNVS USB_H1_VBUS USB_OTG_VBUS VDD_SNVS_CAP VDDARM_CAP VDDARM_IN VDDARM23_CAP VDDARM23_IN VDDHIGH_CAP VDDHIGH_IN VDDPU_CAP VDDSOC_CAP VDDSOC_IN VDDUSB_CAP VGEN1 VGEN2 VGEN3 VGEN4 VGEN5 VGEN6 W10 AE19 AB20 P12 M10, M11, M12 M7, M8, M9 K13, L13, M13 J15, K15, L15 P14 R15 J6, K6, L6 F12, F13, G13, H13 G8, H6, H7, H8 P13 AD1 AC1 U5 W5 V9 U10 Remark PMIC V_core_ref PMIC VDD OTP Main system supply. i.MX 6D/6Q (VDD_SNVS_IN) tied to PMIC (VSNVS) SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 24 Freescale Semiconductor, Inc. RGMII_RD3 EIM_D27 EIM_D26 RGMII_RD1 EIM_D25 EIM_EB3 Freescale Semiconductor, Inc. GND GND GND VDDARM_CA P VDDARM_CA P VDDARM_CA P VDDARM23_ VDDARM23_ VDDARM23_ CAP CAP CAP NVCC_MIPI GPIO_16 GPIO_9 NVCC_SD2 SATA_VPH PCIE_VPH SATA_VP PCIE_VPTX PCIE_VP CSI0_DAT16 GND CSI_D2P CSI_D3M HDMI_CLKP HDMI_D0P HDMI_CLKM HDMI_D0M LVDS1_TX2_ LVDS1_TX2_P N SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 25 HDMI_D1P HDMI_D2P LVDS0_TX0_P LVDS0_TX1_P LVDS0_TX2_P LVDS0_CLK_P GND 19 GND HDMI_DDCC LVDS0_TX0_ LVDS0_TX1_ LVDS0_TX2_ LVDS0_CLK_ HDMI_D1M HDMI_D2M EC N N N N CSI0_DAT5 GPIO_3 CSI0_DATA_E LVDS0_TX3_ CSI0_MCLK LVDS0_TX3_P N N LVDS1_CLK_P LVDS1_TX0_ N GND LVDS1_CLK_ N GPIO_2 KEY_COL4 KEY_COL2 18 LVDS1_TX1_ LVDS1_TX1_P N KEY_ROW4 KEY_ROW2 17 CSI0_DAT4 CSI0_VSYNC CSI0_PIXCLK LVDS1_TX0_P GPIO_0 GPIO_1 DDR_1V2 16 CSI_D3P CSI0_DAT7 CSI0_DAT6 GPIO_4 NVCC_LVDS2 P5 KEY_ROW1 ENET_REF_CL LVDS1_TX3_ LVDS1_TX3_P K N ENET_MDC ENET_MDIO ENET_TXD1 ENET_TXD0 ENET_CRS_D ENET_RX_ER ENET_RXD1 ENET_RXD0 V DISP0_DAT20 DISP0_DAT21 DISP0_DAT22 DISP0_DAT23 15 CSI_CLK0M CSI_D2M HDMI_HPD CSI0_DAT13 CSI0_DAT11 CSI0_DAT9 CSI_CLK0P GND CSI0_DAT17 GPIO_5 DSI_D1P GPIO_6 CSI0_DAT19 CSI0_DAT18 CSI0_DAT14 CSI0_DAT12 CSI0_DAT10 CSI0_DAT8 GPIO_7 NVCC_GPIO GND DSI_D1M CSI0_DAT15 KEY_ROW0 GND DDR_1V2 DISP0_DAT16 DISP0_DAT17 DISP0_DAT18 DISP0_DAT19 VDDSOC_CAP KEY_COL0 GND GND GND DISP0_DAT12 DISP0_DAT13 DISP0_DAT14 DISP0_DAT15 DISP0_DAT8 DISP0_DAT9 DISP0_DAT10 DISP0_DAT11 14 GPIO_8 GND GND GND GND DI0_DISP_CL K DISP0_DAT4 DISP0_DAT5 DISP0_DAT6 DISP0_DAT7 VDDSOC_CAP VDDSOC_CAP VDDSOC_CAP KEY_COL1 ENET_TX_EN GND GND GND GND GND GND DI0_PIN2 DI0_PIN4 DI0_PIN15 GND A 13 VDDARM23_I VDDARM23_I VDDARM23_I NVCC_CSI N N N GND GND GND GND GND GND GND GND EIM_DA12 DI0_PIN3 EIM_DA13 EIM_BCLK B DISP0_DAT0 DISP0_DAT1 DISP0_DAT2 DISP0_DAT3 EIM_DA11 EIM_DA15 EIM_DA14 EIM_DA8 C 12 HDMI_VPH GND GND GND GND GND VDDSOC_IN VDDSOC_IN VDDSOC_IN GND DDR_1V2 EIM_DA6 EIM_DA9 EIM_DA10 EIM_DA5 D Table 7-4 Ball Map 8 9 10 11 HDMI_VP GND VDDARM_IN SD4_CMD GND GND GND EIM_WAIT EIM_DA1 EIM_DA7 EIM_DA4 EIM_DA0 E 7 GND GND SD4_DAT0 VDDARM_IN GND GND GND NVCC_ENET EIM_RW EIM_DA3 EIM_DA2 EIM_LBA F 6 SD4_DAT2 VDDARM_IN NVCC_SD1 VDDPU_CAP VDDPU_CAP VDDPU_CAP VDDSOC_IN NVCC_LCD EIM_A17 EIM_EB0 EIM_EB1 EIM_OE G 5 SD4_DAT4 EIM_A20 EIM_CS0 EIM_CS1 EIM_A16 H 4 NVCC_EIM0_ NVCC_EIM1 NVCC_EIM2 NOR EIM_A24 EIM_A19 EIM_A18 GND J 3 EIM_D28 EIM_A23 EIM_A22 EIM_A21 K 2 EIM_D29 EIM_D30 EIM_D31 L 1 SD4_DAT6 NVCC_RGMII RGMII_RD2 M RGMII_RD0 N 7.3. Ball Map 20 26 GND SW1CLX SW1CLX SW1CLX SW1ABLX SW1ABLX PMIC_VCORE REF PMIC_VIN PMIC_VIN SW1CLX SW1CFB SW1ABLX SW1ABLX SW1ABLX SW1ABFB PMIC_VIN PMIC_VIN GND SD3_DAT5 SD3_DAT4 SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. USB_H1_DN USB_OTG_DP CLK2_P CLK2_N SD3_DAT7 SD3_DAT6 RTC_XTALO RTC_XTALI JTAG_TDI JTAG_TDO NVCC_PLL_O VDDHIGH_CA UT P GND JTAG_MOD CLK1_N CLK1_P XTALO XTALI JTAG_TMS JTAG_TCK CSI_D0M CSI_D0P DSI_D0P DSI_D0M GPIO_17 CSI_D1P CSI_D1M DSI_CLK0M DSI_CLK0P GPIO_19 NANDF_ALE NANDF_CLE VDDHIGH_IN NVCC_JTAG NANDF_WP_ NANDF_CS3 JTAG_TRST_B B DDR_1V2 NANDF_RB0 NANDF_CS0 19 GND PCIE_RXM SD3_DAT2 SD3_DAT3 NANDF_CS1 NANDF_CS2 GND GND NANDF_D0 VDDUSB_CAP 18 USB_OTG_VB PCIE_TXP US SD3_DAT0 SD3_DAT1 GND GND GND NANDF_D1 17 PCIE_RXP SATA_TXP SATA_TXM SD3_CLK SD3_RST GND SYS_STBY_RE Q GND TAMPER PMIC_SDWN KEY_COL3_P NOR_HOLD_ B MIC_SCL B 16 USB_H1_VBU USB_OTG_D USB_OTG_CH USB_H1_DP PCIE_TXM S N D_B SATA_RXP SD3_CMD GND GND SD2_DAT0 NOR_W_B VDD_SNVS_C AP 15 SATA_RXM SD1_DAT3 SD1_DAT2 SD2_DAT3 SD2_CLK NANDF_D2 NVCC_NAND F NVCC_SD3 SD4_CLK SD4_DAT1 14 SD1_DAT1 SD1_CMD SD1_CLK SD2_CMD NANDF_D3 NANDF_D4 BOOT_MODE NANDF_D5 0 GPANAIO NANDF_D6 TEST_MODE NANDF_D7 VGEN6 KEY_ROW3_P BOOT_MODE MIC_SDA 1 GND GND GND GND GND SD4_DAT3 SD4_DAT5 13 SD1_DAT0 ONOFF GND GND SYS_VSNVS GND GND GND GND SD4_DAT7 12 SYS_PWRON SD2_DAT1 LICELL SWBSTFB VGEN5 GND GND GND EIM_A25 11 GPIO_18_PM SD2_DAT2 IC_INTB SWBSTLX SWBSTLX GND PMIC_VIN DDR_1V2_S W3AFB GND GND EIM_D24 EIM_D23 10 GND SWBSTIN PMIC_VDDOT P PMIC_VIN SW3ABLX GND VGEN3 EIM_D21 EIM_D22 9 PMIC_VIN PMIC_VIN GND PMIC_ICTEST SW3ABLX SW3ABLX DDR_1V8 EIM_D19 EIM_EB2_NO EIM_D17_NO R R GND RGMII_RX_CT L RGMII_RXC P 8 GND GND GND SW3ABLX VGEN4 EIM_D20 RGMII_TD3 RGMII_TX_CT RGMII_TD1 L EIM_D16_NO EIM_D18_NO R R GND RGMII_TD2 R RGMII_TD0 T 7 GND GND GND GND GND SW2LX U SYS_SW2FB_ RGMII_TXC VIN2 V 6 GND GND GND GND SW2LX SW2LX SW2LX W 5 GND GND GND GND SW2LX SW2LX Y 4 GND GND GND SW4LX SW4LX AA 3 GND PMIC_VIN SW4LX SYS_SW4FB_ VIN1 AB 2 SYS_POR_B GND PMIC_VIN PMIC_VIN PMIC_VIN PMIC_VIN PMIC_VIN VGEN2 AC VGEN1 AD GND AE 1 20 7.4. Package Drawings Figure 4. SCM-i.MX 6Dual/6Quad with 16Gb (1GB) LPDDR2 PoP Memory SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 27 Figure 5. SCM-i.MX 6Dual/6Quad without Memory SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 28 Freescale Semiconductor, Inc. 8. Revision History Table 8-1 SCM-i.MX 6Dual/6Quad Datasheet Revision History Revision 0 Date 02/2016 Change description Initial release SCM-i.MX 6Dual/6Quad Datasheet for Consumer Products, Data Sheet: Technical Data, Rev. 0, 02/2016 Freescale Semiconductor, Inc. 29 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. 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