NIS6201 Floating, Regulated Charge Pump The NIS6201 charge pump is designed to provide economical, low level power to circuits above ground level potential, such as the drive for ORing diodes. It is a very cost−effective replacement for a small, isolated, switching power supply. It contains an internal linear regulator, and a versatile charge pump to allow bias voltage supplies to be transferred from a ground referenced source to a higher potential. The design of the charge pump allows for any isolation voltage required, as the high voltage components are external to the pump and can be sized accordingly. MARKING DIAGRAM 8 SOIC−8 NB CASE 751 8 1 Features • • • • • http://onsemi.com Integrated Linear Regulator and Charge Pump Thermal Limit Protection Adjustable Voltage Output High Voltage Isolation This is a Pb−Free Device 1 6201 A Y WW G Applications 6201 AYWW G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package PIN CONNECTIONS • ORing Diodes • Floating Supervisory Circuits • LED Driver VCC N/C 1 8 PWRGND N/C 2 7 DRIVE SIGGND 3 6 VREG 5 VCC COMP 4 (Top View) 0.50 V Regulator 15 V ORDERING INFORMATION + - Device NIS6201DR2G + - Overcharge 150 mV DRIVE Package Shipping† SOIC−8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1.0 MHz Oscillator SIGGND COMP VREG PWRGND Figure 1. Charge Pump Block Diagram © Semiconductor Components Industries, LLC, 2011 January, 2011 − Rev. 3 1 Publication Order Number: NIS6201/D NIS6201 PIN FUNCTION DESCRIPTION Pin Symbol Description 1, 2 N/C 3 SIGGND 4 COMP 5 VCC 6 VREG This is the regulated output of the internal linear regulator. 7 DRIVE Output drive of oscillator, that drives external diode/capacitor network. 8 PWRGND No connection. Ground reference pin for control circuits. This should be connected to power ground on the PCB. The feedback and compensation network of the linear regulator are connected to this pin. Input power to chip. There is an internal clamp at 15 V to allow for a shunt regulator circuit on this pin for high voltage inputs. Ground reference pin for driver current. MAXIMUM RATINGS Rating Symbol Value Unit VCC −0.3 to 15 V Vcomp 4.5 V Drive Current, Peak IDpk 3.0 A Drive Current, Average IDavg 0.05 Thermal Resistance, Junction−to−Air Min copper area 1 in2 copper (1 oz, single sided) QJA Thermal Resistance, Junction−to−Lead (Pin 1) QJL Power Dissipation @ TA = 25°C Min copper area 1 in2 copper (1 oz, single sided) Pmax Input Voltage, Operating (Note 1) Comp pin Voltage A °C/W 175 114 41 °C/W W .57 .88 Operating Temperature Range TJ −40 to 125 °C Non−operating Temperature Range TJ −55 to 150 °C Lead Temperature, Soldering (10 Sec) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Above this voltage, a series resistor is necessary to limit current into the shunt regulator. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 15 V, Vreg = 12 V, DRIVE Pin open, TJ = 25°C.) Characteristic Symbol Min Typ Max Unit fosc 0.9 1.3 1.45 MHz On Resistance, High Side FET RDSon(hi) − 9.5 − W On Resistance, Low Side FET RDSon(low) − 9.5 12 W Vref 490 475 500 505 510 525 mV Vhead − 155 220 mV Vmin 7.0 − − V OSCILLATOR Frequency DRIVER LINEAR REGULATOR Reference Voltage, Pin 4 TJ = −40 to 125°C Headroom (VCC–Vreg) VCC = 7 V, Idrive = 10 mA TOTAL DEVICE Minimum Operational Input Voltage Bias Current (Operational) Bias Current (COMP Pin = 600 mV) VCC Zener Breakdown Voltage IBias − 3.6 4.6 mA IBias_SD − 3.0 3.6 mA VZener 14.5 15 − V http://onsemi.com 2 NIS6201 BAS16LT1 1.0 mF BAS16LT1 Load BAS16LT1 0.1 mF 5 12 V 7 NIS6201 8 NIS6111 3 6 4 22 k 0.1 mF 1.0 k Figure 2. Application Circuit with Better ORing Diode 1.0 mF VCC 48 V + PWR GND SIG GND COMP 0.1 mF Charge Pump DC−DC Converter DRIVE VREG 1.0 mF Figure 3. Application Circuit for Improved Regulation and Transient Response http://onsemi.com 3 NIS6201 0.1 mF VCC + 8.0 V PWR GND Charge Pump SIG GND COMP DRIVE 1.0 mF VREG 1.0 mF Figure 4. Current Regulated, Voltage Doubler 8.0 to 18 Vdc 220 0.1 mF COMP VREG 8 Drive 7 NIS6201 SIG GND PWR GND 5 VCC 3 4 6 0.1 mF 0.1 mF 13.7k 0.1 mF 1k 100 mA to 2 mA −12.5 V Diodes are: BAS16LT1 75V or M1MA174T1 100V 1 mF Figure 5. Regulated, Negative Doubler Circuit http://onsemi.com 4 1 mF NIS6201 OPERATING DESCRIPTION DC Input The Vcc pin is rated for a maximum dc voltage of 15 volts. An internal shunt diode is included for applications where the voltage may exceed 15 volts. For voltages greater than 15 volts an external shunt resistor must be added in series with the Vcc pin. This resistor must be sized such that at low line, the voltage drop across it will allow for an input voltage of greater than that of the output of the LDO and at high line such that the current into the chip does not exceed its power rating. Pwr GND Sig GND Comp V reg NIS6201 8 3 4 6 Vset 0.1uF LDO Vbias The internal LDO contains a P−Channel FET and error amplifier with a 0.5 volt reference. A voltage divider is required from the Vreg pin to the comp pin to set the output of the LDO. This output voltage (Vreg) is the voltage used for the charge pump oscillator. The divider can be calculated from the following formulas: Figure 6. Bias Voltage Divider Overcharge Comparator Rbias + 0.50 V Ibias The overcharge comparator provides a protection function from an overvoltage condition at turn−on. Figure 7 shows a typical configuration for this charge pump. At turn−on there is a voltage divider consisting of two capacitors and two diodes. If this device is being operated at voltages significantly above the Vreg level, it is possible to charge the Vreg cap well beyond its intended level. Ibias is generally in the range of 100 mA to 1 mA and sets the bias current in the divider. Rset + Rbias(Vreg * 0.50 V) 0.50 V VCC 1.25 V + − Regulator + Overcharge − 0.10 V 1 MHz Oscillator DRIVE VREG COMP GND Figure 7. Overcharge Circuit http://onsemi.com 5 NIS6201 The overcharge comparator detects when the voltage at Vreg is 10% greater than its set level. If this situation occurs, the overcharge circuit overrides the oscillator and turns on the bottom FET of the driver stage. This shunts the start−up current directly to ground and bypasses the capacitor on Vreg thus allowing for safe start−ups at high input voltages. Pshunt diode + VCC @ * VCC) Ǔ * 2 mA * (Iout @ nstages)ƫ ƪǒ(VinRseries LDO The power lost in the LDO pass transistor is calculated by the voltage drop across it and the current through it. As was the case with the shunt diode, when calculating the load current, the number of pump stages must be accounted for. Oscillator The oscillator in this chip operates at a nominal frequency of 1 MHz. The FETs have an on resistance of 20 W and can drive loads in excess of 20 mA. Since the charge diodes and capacitors are external, this device can drive a “floating” voltage that is referenced to the input bus such as is shown in Figure 7. The “isolation” voltage for the regulated output is limited only by the ratings of these external components. The oscillator can also drive a conventional voltage doubler circuit or an inverting output stage. PLDO + (VCC * Vreg) @ (2mA ) (Iout @ nstages)) Oscillator The power dissipated in the oscillator section can be approximated by multiplying the square of the load current by the typical on resistance. POsc + Iout2 @ 20 W Total Power Consumption Bias Current The SO−8 package used for this chip has a power rating of 570 milliwatts. The major losses in this device come from three circuits plus the bias current. These are the following: The bias current is simply the input voltage at the Vcc pin multiplied by 2 mA. The total power dissipated by the chip is the sum of these four losses. If the input voltage does not exceed 15 volts, the shunt diode losses can be ignored. The sum of these losses should not exceed the power rating for the device. Note that the power rating is specified at 25°C and must be derated at higher operating temperatures. Shunt Diode The power dissipated in this diode is due to the current through the input series resistor when the input exceeds 15 volts. The current in the diode is the current through the input resistor less the output and bias currents in the chip. The output current is equal to the load current unless multiple pump stages are used in which case it is multiplied by the number of stages in use. An additional 2 mA of bias current is required to operate the charge pump. http://onsemi.com 6 NIS6201 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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