NIS6201 Product Preview Floating, Regulated Charge Pump The NIS6201 charge pump is designed to provide economical, low level power to circuits above ground level potential, such as the drive for ORing diodes. It is a very cost−effective replacement for a small, isolated, switching power supply. It contains an internal linear regulator, and a versatile charge pump to allow bias voltage supplies to be transferred from a ground referenced source to a higher potential. The design of the charge pump allows for any isolation voltage required, as the high voltage components are external to the pump and can be sized accordingly. http://onsemi.com MARKING DIAGRAM 8 TBD ALYW SOIC−8 NB CASE 751 8 1 1 Features • • • • Integrated Linear Regulator and Charge Pump Thermal Limit Protection Adjustable Voltage Output High Voltage Isolation A L Y W = Assembly Location = Wafer Lot = Year = Work Week Applications • ORing Diodes • Floating Supervisory Circuits • LED Driver PIN CONNECTIONS VCC PWRGND 1 8 PWRGND PWRGND 2 7 DRIVE SIGGND 3 6 VREG 5 VCC COMP 4 (Top View) 0.50 V ORDERING INFORMATION + − Device Regulator 30 V TBD Package Shipping SOIC−8 TBD + − 50 mV Drive Overcharge 1.0 MHz Oscillator Comp Vreg Gnd Figure 1. Charge Pump Block Diagram This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2004 May, 2004 − Rev. P2 1 Publication Order Number: NIS6201/D NIS6201 PIN FUNCTION DESCRIPTION Pin Symbol Description 1, 2, 8 PWRGND Ground reference pin for driver current. 3 SIGGND Ground reference pin for control circuits. This should be connected to power ground on the PCB. 4 COMP 5 VCC 6 VREG This is the regulated output of the internal linear regulator. 7 DRIVE Output drive of oscillator, that drives external diode/capacitor network. The feedback and compensation network of the linear regulator are connected to this pin. Input power to chip. There is an internal clamp at 30 V to allow for a shunt regulator circuit on this pin for high voltage inputs. MAXIMUM RATINGS (Maximum ratings are those, that, if exceeded, may cause damage to the device. Electrical Characteristics are not guaranteed over this range.) Rating Symbol Value Unit Input Voltage, Operating VCC −0.3 to 18 V Drive Current, Peak IDpk 3.0 A Drive Current, Average IDavg 0.05 A Thermal Resistance, Junction−to−Air 0.1 in2 Copper 0.5 in2 Copper QJA Thermal Resistance, Junction−to−Lead (Pin 1)2 QJL − °C/W Power Dissipation @ TA = 25°C SO−8 Leadless Pmax − W Energy Rating SO−8 Leadless Emax − J Operating Temperature Range Tj −40 to 125 °C Non−operating Temperature Range Tj −55 to 150 °C Lead Temperature, Soldering (?? Sec) TL − °C °C/W − − ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 15 V, Vreg = 12 V, Tj = 25°C.) Characteristic Symbol Min Typ Max Unit fosc 0.9 1.0 1.1 MHz On Resistance, High Side FET RDSon(hi) − 20 − On Resistance, Low Side FET RDSon(low) − 20 − Vref 490 500 510 mV − − − − − Vhead − 0 − V Sink Current (Vpin? 300 mV, Low Z State) ILow − 5.0 − mA Leakage Current (Vpin? = 18 V, High Z State) ILeak − 20 − A Minimum Operational Input Voltage Vmin 7.0 − − V Bias Current (Operational) IBias − 2.0 − mA OSCILLATOR Frequency DRIVER LINEAR REGULATOR Reference Voltage Temperature Coefficient Headroom (VCC–Vreg) TOTAL DEVICE http://onsemi.com 2 NIS6201 1.0 F BAS16LT1 1.0 F BAS16LT1 Load BAS16LT1 1, 2, 8 VCC 0.1 F 5 12 V NIS6111 + 48 V 7 NIS6201 3 4 6 Pwr Gnd 0.1 F Charge Pump DC−DC Converter Drive Sig Gnd 22 k Comp 0.1 F Vreg 1.0 k 1.0 F Figure 2. Application Circuit with Better ORing Diode Figure 3. Application Circuit for Improved Regulation and Transient Response 0.1 F VCC + 8.0 V Pwr Gnd Sig Gnd Comp Charge Pump Drive 1.0 F Vreg 1.0 F Figure 4. Current Regulated, Voltage Doubler http://onsemi.com 3 NIS6201 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 Y M M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 8 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 8 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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