ESD Protection Diodes with Ultra Low Leakage

ESD9R3.3S, SZESD9R3.3S
Transient Voltage
Suppressors
ESD Protection Diodes with Ultra−Low
Leakage
The ESD9R is designed to provide ESD protection for ASSPs and
ASICs used in ultra low current applications such as human body sensors.
These devices have been designed for leakage under 1 nA from 0°C to
50°C when turned off. During an ESD event, these devices turn on to
clamp the ESD to a safe voltage level for the IC. These devices have the
added benefits of low capacitance for high speed data lines and small
package size for space constrained designs.
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Specification Features:
•
•
•
•
•
•
•
•
•
•
Ultra−Low Leakage < 1 nA
Ultra−Low Capacitance 0.5 pF
Low Clamping Voltage
Small Body Outline Dimensions:
0.039″ x 0.024″ (1.00 mm x 0.60 mm)
Low Body Height: 0.016″ (0.4 mm)
Stand−off Voltage: 3.3 V
Response Time < 1.0 ns
IEC61000−4−2 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
This is a Pb−Free and Halogen−Free Device
SOD−923
CASE 514AB
MARKING DIAGRAM
JM
J = Specific Device Code
M = Date Code
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
ORDERING INFORMATION
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Package
Shipping†
ESD9R3.3ST5G
SOD−923
(Pb−Free)
8000 / Tape &
Reel
SZESD9R3.3ST5G
SOD−923
(Pb−Free)
8000 / Tape &
Reel
Device
Symbol
Contact
Air
HBM
Value
Unit
±10
±15
±16
kV
Total Power Dissipation on FR−5 Board
(Note 1) @ TA = 25°C
°PD°
150
mW
Storage Temperature Range
Tstg
−55 to +150
°C
Junction Temperature Range
TJ
−55 to +125
°C
Lead Solder Temperature − Maximum
(10 Second Duration)
TL
260
°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
DEVICE MARKING INFORMATION
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 1
1
Publication Order Number:
ESD9R3.3S/D
ESD9R3.3S, SZESD9R3.3S
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
I
Parameter
IF
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
Working Peak Reverse Voltage
Breakdown Voltage @ IT
IT
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
C
VC VBR VRWM
Maximum Reverse Leakage Current @ VRWM
V
IR VF
IT
IPP
Uni−Directional TVS
Max. Capacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.0 V Max. @ IF = 10 mA for all types)
VRWM
(V)
IR (nA) @ 1 V
TA = 05C
to 505C
(Note 4)
VBR (V) @ IT
(Note 2)
IT
C (pF)
VC (V)
@ IPP = 1 A
(Note 5)
VC
Per IEC61000−4−2
(Note 3)
Device*
Device
Marking
Max
Max
Min
mA
Typ
Max
Max
ESD9R3.3ST5G
J**
3.3
1.0
4.8
1.0
0.5
0.9
7.8
Figures 1 and 2
See Below
*Includes SZ−prefix device where applicable.
**Rotated 270°.
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
4. Limits over temperature are guaranteed by design, not production tested.
5. VC measured using pulse waveform in Figure 5.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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2
ESD9R3.3S, SZESD9R3.3S
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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3
80
ESD9R3.3S, SZESD9R3.3S
PACKAGE DIMENSIONS
SOD−923
CASE 514AB
ISSUE C
D
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
−Y−
E
1
2X b
0.08 X Y
2
TOP VIEW
DIM
A
b
c
D
E
HE
L
L2
A
c
INCHES
MIN
NOM MAX
0.013 0.015 0.016
0.006 0.008 0.010
0.003 0.005 0.007
0.030 0.031 0.033
0.022 0.024 0.026
0.037 0.039 0.041
0.007 REF
0.002 0.004 0.006
HE
SIDE VIEW
SOLDERING FOOTPRINT*
2X
2X
MILLIMETERS
MIN
NOM MAX
0.34
0.37
0.40
0.15
0.20
0.25
0.07
0.12
0.17
0.75
0.80
0.85
0.55
0.60
0.65
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
L
1.20
2X
2X
0.36
PACKAGE
OUTLINE
L2
BOTTOM VIEW
0.25
DIMENSIONS: MILLIMETERS
See Application Note AND8455/D for more mounting details
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ESD9R3.3S/D