Integrated clean-up-PLL, TFF1xxxx and buffer amplifier

UM10484
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Rev. 3 — 10 October 2012
User manual
Document information
Info
Content
Keywords
External reference, clean-up-PLL, VCXO, LO generator, buffer amplifier,
RF output power level, phase noise
Abstract
This document describes an integrated demonstration (demo) board for
Clean-Up-PLL (CUP) local oscillator generator TFF11XXX/TFF100X. The
demo board includes an output buffer amplifier based on BFU7XX series
microwave transistors.
UM10484
NXP Semiconductors
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Revision history
Rev
Date
Description
v.3
20121010
Correct mistake in fig 4 and components in table 1.
v.2
20120202
Security status changed from company internal to company public.
v.1
20111221
Initial version.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UM10484
User manual
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Rev. 3 — 10 October 2012
© NXP B.V. 2012. All rights reserved.
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
1. Introduction
This user manual describes an integrated demonstration (demo) board for Clean-Up-PLL
(CUP) local oscillator generator TFF11XXX/TFF100X. The demo board includes an output
buffer amplifier based on the BFU7XX series of microwave transistors. Circuit schematics,
a PCB layout design and test results are provided.
The demo board converts a reference signal (typically 10 MHz) to a frequency of 30 MHz
to 50 MHz via a Xilinx CPLD and logic gate-based Voltage-Controlled eXternal Oscillator
(VCXO). The fifth harmonic is filtered via a 7th-order Cauer filter and used as the
reference for the TFF11XXX/TFF100X. Microwave transistors BFU7XX amplify the output
of the TFF11XXX/TF100X to a level of 7 dBm, 10 dBm or 13 dBm, depending on the
version of buffer used.
The NXP TFF11XXX, TFF1003, TFF1007, TFF1008 are a family of low phase-noise,
high-frequency accurate microwave band Local Oscillator (LO) generators implemented
in Silicon Germanium (SiGe) high Ft process. These devices have a combined frequency
range of 7 GHz to 15 GHz, where:
• TFF1003/TFF1007/TFF1008 cover the VSAT Ku band (12 GHz to 14 GHz)
• TFF11XXX series cover the remaining frequency band
The LO generators require a reference input signal that minimizes the added phase noise
to the LO generated signal. The Clean-Up-PLL generates an ultra-low phase noise
reference signal based on a VCXO.
In practical applications, customers often use the LO generator to drive a mixer which
could be a passive or active type. A high frequency buffer amplifier is required for
applications requiring a higher LO drive level. The demo board has a wideband buffer
amplifier designed to deliver an output power level of 7 dBm to 13 dBm.
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User manual
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Rev. 3 — 10 October 2012
© NXP B.V. 2012. All rights reserved.
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
aaa-001260
Fig 1.
PCB of integrated Clean-Up-PLL, TFF11XXX/TFF100X, and buffer amplifier
2. General description
2.1 High-level function review
The demo board accommodates additional customer-functional requirements with the
following features:
Input: typically, a system may see a reference frequency of 10 MHz, which can be internal
or external, however, a different reference frequency can be used. This demo board has a
10 MHz external reference input of 75  with F-type connector for an input power level
range of 15 dBm to +5 dBm.
Output: the demo board can provide an output power of 7 dBm, 10 dBm or 13 dBm to an
output stage such as a mixer. The on-board buffer amplifier can be used, avoiding the
need to design a separate circuit, saving engineering costs and time-to-market.
A high-level block diagram is shown in Figure 2.
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User manual
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UM10484
NXP Semiconductors
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Vbuf
Vpld
Vlpf
Vvco
PLD
Reference
dividers and
PFD
Frequency
error signal
processing/
loop filter
EXT. CLK input
5th harmonic Vbuf
filter
VCXO or VCO
REF. IN
TFF11XXX/
TFF1003/
TF1004/
TFF1008
Vbuf
Vdv
Vbuf
DC input
SUPPLY
Vpld
Vlpf
Vvco
Fig 2.
aaa-001261
Block diagram of integrated Clean-Up-PLL, TFF11XXX/TFF100X, and buffer amplifier
2.2 Description of individual function blocks
External reference input: The external reference input provides the clock for the PLL.
The amplifier converts this reference clock to a clipped sine wave that is recognized by
the CPLD logic device.
Clean-Up-PLL: The Clean-Up-PLL for generating the required reference signal (CW) for
the NXP LO generator family:
•
•
•
•
TFF1003HN: for VSAT applications in the range 12.8 GHz to13.05 GHz
TFF1007HN: VSAT applications at 14.75 GHz
TFF1008 HN: VSAT application at 14.275 GHz
TFF11XXX: frequency range 7 GHz to 15.2 GHz
The demo board has the following additional circuits to Clean-Up-PLL:
• External PLL lock detector: a simple voltage window detector logic circuit detects the
tuning voltage at the loop filter output. A voltage between 0.4 V and 2.2 V indicates a
Clean-Up-PLL locked status, and amber LED (D1) turns on.
• Phase-noise performance and tuning range can be optimized using an optional active
loop filter which allows the customer to select specific components to implement
either a passive or an active loop filter.
• Buffer amplifier: The buffer amplifier is the final stage which amplifies the TFF1XXX
RF/microwave output signal from 4 dBm (typical) to +7 dBm to +13 dBm depending
on the amplifier used.
UM10484
User manual
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UM10484
NXP Semiconductors
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
3. Application board
3.1 Application circuit
VCC_3.3 V
C22
22 nF
L1
680 nH
C24
100 nF
R29
4.7 kΩ
R30
220 Ω
C32
CON-F-TYPE-THROUGH
J3
1
L2
2.7 μH
5
4
3
2
fref-buf
C27
Q2
BFS17
10 nF
100 nF
C28
58 pF
R36
2.7 kΩ
R37
82 Ω
C29
10 nF
aaa-001262
Fig 3.
UM10484
User manual
10 MHz reference input and amplifier schematic
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© NXP B.V. 2012. All rights reserved.
6 of 20
UM10484
NXP Semiconductors
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
VCC_3.3 V
R1
22 Ω
R2
10 Ω
C4
C1
100 nF
1
C6
100 nF
2
I/O1
3
I/O2
4
I/O3
5
I/O5
6
I/O6
25
32
31
30
29
GND
I/O28
I/O29
I/O30
U2
VAUX
J2
I/O31
R7
10 Ω
TDO
R6
10 kΩ
I/O32
100 nF
R5
10 kΩ
VCC_3.3 V
28
26
VCCIO2
VCC_3.3 V
CPLD PLL
27
4
20
1
21
2
24
3
23
XC2C32A
5
22
6
19
VCC
VCC_1.8 V
C7
100 nF
GND21
PASSIVE L.F.
I/O24
I/O23
TP-UP
INPUT
18
8
17
10
13
11
33
C11
2.2 nF
I/O17 10 kΩ
C31
R41
DNP
DNP
VCC_3.3 V_VCXO
-IN
3
DNP
R40
DNP
DNP
n.c.
GND
C89
10 nF
V-TUNE
X1
C50
1
6
2
5
3
4
VCC
VCC_3.3 V_VCXO
C39
10 nF
X2
C40
1 nF
C41
220 pF
C43
10 nF
R46
220 kΩ
150 pF
C51
12 pF
40.78125
MHz
R49
150 pF
C52
12 pF
C57
C58
D4 4.7 kΩ
BB202
R53
3.3 kΩ
C53
220 pF
R54
680 Ω
L3
220 nH
REF-OUT
5.6 pF
18 pF
18 pF
L4
L5
L6
L7
39 nH
100 nH
18 nH
33 nH
Q3
BFS17
C61
36 pF
C91
1 nF
220 pF
J7
SMB-V
R58
2.7 kΩ
1
L8
6.8 nH
C63
82 pF
L10
4.7 nH
C64
100 pF
C54
6.8 pF
J4
SMB-V
C59
C60
10 nF
C45
220 pF
V-TUNE
C47
X2
D3
BB202 C56
C90
C44
1 nF
1 MΩ
C46
1
V-TUNE
Y
R43
R48
4.7 kΩ
2
TP-ACTIVE-VT
74LVC1GX04GW
220 pF
3
OUT
U9
R72
22 Ω
4
R33
DNP
1
ACTIVE L.F.
fvco
5
2
+IN V-
C30
C25
100 nF
V+
5
OPA376
R34
J6
SMB-V
DNP
DNP
R31
DNP
4
100 Ω
C23
10 Ω
U16
100 pF
C21
R27
R23
DNP
R71
R50
DNP
TP-VCO-DIV
100 nF
C92
0Ω
C15
100 nF
R17
DNP
VCC_3.3 V
JTAG
R45
27 kΩ
C12
DNP
12
C19
TP-LKDET
R44 TP-DOWN
0Ω
I/O18 R16
VCCIO1
9
DEI
16
GND11
14
I/O13
TMS
15
I/O10
I/O8
7
I/O9
fref-buf
R19
68 Ω
I/O7
TCK
fvco
TDI
C14
100 pF
TP-V-TUNE
R15
I/O19 R13
10 kΩ
6 pin
TP-PASSIVE-VT
TP-REF-DIV
L9
6.8 nH
C65
82 pF
5
4
3
R59
56 Ω
220 pF
C62
220 pF
R47
82 Ω
R51
DNP
C101 1
C37
220 pF
1 nF
2
3
4
5
R42
DNP
2
REFERENCE OUTPUT
aaa-001263
VCXO AND HARMONIC FILTER
Fig 4.
Clean-up-PLL schematic (part 1)
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User manual
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UM10484
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
3.3 V
U1
VOUT
VCC_3.3 V
C2
47 μF
35 V
R3
SENSE
VIN
2
3
LP3961EMP-3.3 V
4
10 kΩ
SD
1
5
C3
100 μF
16 V
R4
10 kΩ
GND
2
VCC_5 V
CON-2PIN
1.8 V
U3
VOUT
VCC_1.8 V
C8
47 μF
35 V
J1
1
R9
SENSE
3
VIN
2
LP3961EMP-1.8 V
4
SD
1
5
10 kΩ
D9
BZX84-B5V
C9
100 μF
16 V
R10
10 kΩ
GND
3.3 V_VCXO
U14
VOUT
VCC_3.3 V_VCXO
C85
10 μF
16 V
n.c.
1
VIN
6
LP5900SD-3.3 V
2 7
3
GND1 GND
EN
5 4
C86
10 μF
16 V
R38
10 kΩ
n.c.
POWER SUPPLY
VCC_3.3 V
C13
100 nF
R18
12.1 kΩ
LMV7239
IN-
UW: 2.2 V
R21
90.9 kΩ
C18
1 nF
IN+
4
5
3
2
VCC+
OUT
1
D1
SML-211YTT86
VCC-
U4
ON: LOCK
OFF: OUT-OF-LOCK
R24
R26
DNP
V-TUNE
U17
1 MΩ
LW: 0.4 V
LMV7239
R28
12.1 kΩ
ININ+
R32
2.2 kΩ
C20
100 nF
C26
1 nF
U7
4
5
3
2
VCC+
OUT
1
VCC-
B
A
GND
1
5
VCC
2
3
R22
220 Ω
C16
100 nF
4
Y
R25
4.7 kΩ
Q5
PBHV9050T
74AUP1G86GW
R35
DNP
Fig 5.
LOCK DETECTOR
aaa-001371
Clean-up-PLL schematic (part 2)
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User manual
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
VCC_3.3 V_TFF
U15
VOUT
C87
10 μF
16 V
1
6
VIN
VCC_5 V
LP5900SD-3.3 V
7
3
4
5
R39
EN
10 kΩ
n.c.
GND
2
GND1
n.c.
C88
10 μF
16 V
C84
120 pF
D5
SML-211YTT86
R61
560 Ω
10 nF
R62
51 Ω
R63
24 Ω
IN(REF)_N
GND2(REF)
VCC(REF)
L13
CPOUT
VTUNE
2
1
23
TFF11XXX
22
10
21
11
20
12
13
C80
100 pF
14
15
16
17
19
18
GND-TAB
GND3(BUF)
BUF2_P
BUF1_P
C69
0.5 pF
RF_OUTPUT_TO
_BUF_ AMP
BUF2_N
BUF1_N
GND2(BUF)
C71
0.5 pF
R64
51 Ω
L12
BLM15AG100SN1D
BLM15AG100SN1D
C77
4700 pF
25
9
L11
VCC_3.3 V_TFF
3
24
VCC(DIV)
C76
4700 pF
470 pF
8
BLM15AG100SN1D
TP_3.3 V_TFF
33 pF
VCC(BUF)
C74
10 nF
4
C83
GND1(BUF)
IN(REF)_P
REF-OUT
5
n.c.
C73
GND1(REF)
6
C67
7
GND(DIV)
10 kΩ
LCKDET
R67
0Ω
NSL1
U13
R69
R68
DNP
NSL2
R66
0Ω
NSL0
R70
270 Ω
Q4
PMBTA45
270 Ω
n.c.
TFF11XXX lock indicator
ON: LOCK
OFF: OUT-OF-LOCK
R60
18 nF
VREGVCO
VCC_3.3 V_TFF
C66
C78
100 pF
C79
100 pF
C75
4700 pF
aaa-001264
Fig 6.
TFF100X/TFF11XXX schematic
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User manual
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
TP_VCC_3.3 V_BUF_AMP
VCC_3.3 V
C93
10 μF
16 V
R78
12 kΩ
R76
56 Ω
C97
C98
C99
DNP
12 pF
DNP
M1
R73
39 kΩ
R75
39 Ω
R77
0Ω
R74
39 kΩ
Stub1
C100
M2
DNP
Stub1
C96
0.5 pF
C95
1
3
2
J5
GIGALANE
Q7
BFU730F
0.5 pF
RF_OUTPUT_
TO_BUF_AMP
Q6
BFU730F
RF-OUT
aaa-001265
Fig 7.
Buffer amplifier schematic (+10 dBm version)
3.2 Board layout
In general, a good PCB layout is an essential part of an RF circuit design. The demo
board of the integrated clean-up-PLL, TFF100X/TFF11XXX and buffer amplifier can serve
as a guideline or reference for laying out a board using this complete solution. Use
controlled impedance lines for all high frequency inputs and outputs. Bypass VCC with
decoupling capacitors, preferably located as close as possible to the device. For long bias
lines, decoupling capacitors may be required along the line farther away from the device.
Proper grounding of the GND pins is also essential for good RF performance, either
connecting the GND pins directly to the ground plane or through vias, or both.
Due to the nature of microwave signals, care is required to implement these circuits. Refer
to the respective documents for layout recommendations and suggestions.
The material for this integrated board depends on the TFF100X/TFF11XXX and buffer
amplifier which operate at microwave frequencies:
•
•
•
•
Substrate: low-loss Rogers 4003
Substrate critical thickness: 20 mils (0.508 mm)
Dielectric constant: 3.38
Dielectric Loss Tangent: 0.0025
The second substrate layer is solely for rigidity purposes. Figure 8 shows a detailed view
of the layer stack-up.
0.5 oz copper on all layers
20 mils rogers4003
prepreg
20 mils rogers4003
4-layer stackup
Fig 8.
UM10484
User manual
aaa-001266
PCB stack-up of integrated clean-up-PLL, TFF11XXX/TFF100X, and buffer
amplifier
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© NXP B.V. 2012. All rights reserved.
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UM10484
NXP Semiconductors
Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
aaa-001267
Fig 9.
Board layout of integrated clean-up-PLL, TFF11XXX/TFF100X, buffer amplifier
(+10 dBm version)
3.3 Bill of materials
The Bill Of Materials (BOM) is determined by the required generated frequency. Because
part of the PLL is a CPLD-based solution, it is possible to change the divider ratio (N and
R) by software programming (JTAG).
PLL filter: flexible layout options allow different parts to be populated to make either a
passive or an active loop filter.
A different crystal frequency may be required if the selected frequency is outside the
pull-range limits (typically hundreds of ppm) of the VCXO.
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User manual
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Buffer amplifier components are also both frequency and output power level dependent. If
the design requires an output power level of 7 dBm to 10 dBm at a frequency below
13 GHz, the output level is achieved by a cascaded BFU730 solution. If 10 dBm or more
is required, a balanced amplifier solution is required to combine the two cascaded buffer
amplifiers to achieve a higher output RF power to drive the mixer. Please contact NXP
Semiconductors for reference design and evaluation board.
An example of a BOM for a VSAT BUC (Block-Up-Converter) application with a
13.05 GHz LO is given in Table 1.
For other frequency applications please contact NXP Semiconductors for technical
assistance.
Table 1.
Example BOM for a VSAT BUC with a 13.05 GHz LO
Quantity
Reference
Type
Manufacturer
Value
12
C1, C4, C6, C7,
C13, C15, C16,
C19, C20, C24,
C25, C27
GRM188R71E104KA01D
Murata
100 nF
2
C2, C8
TAJE476K035RNJ
AVX
47 F, 35 V
2
C3, C9
B45197A3107K509
EPCOS
100 F, 16 V
1
C11
GRM1885C1H222JA01D
Murata
2.2 nF
8
C12, C21, C23,
C30, C31, C97,
C99, C100
<tbd>
Murata
DNP
3
C14, C64, C92
GRM1885C1H101JA01D
Murata
100 pF
6
C18, C26, C40,
C44, C91, C101
GRM1885C1H102JA01D
Murata
1 nF
1
C22
GRM188R71C223KA01D
Murata
22 nF
1
C28
GRM1885C1H560JA01D
Murata
56 pF
6
C29, C32, C39,
C43, C89, C90
GRM188R71H103KA01D
Murata
10 nF
8
C37, C41, C45,
C50, C53, C60,
C61, C62
GRM1885C1H221JA01D
Murata
220 pF
2
C46, C47
GRM1885C1H151JA01D
Murata
150 pF
2
C51, C52
GRM1885C1H120JA01D
Murata
12 pF
1
C54
GRM1885C1H6R8DZ01D
Murata
6.8 pF
1
C56
GRM1885C1H5R6DZ01D
Murata
5.6 pF
2
C57, C58
GRM1885C1H180JA01D
Murata
18 pF
1
C59
GRM1885C1H360JA01D
Murata
36 pF
2
C63, C65
GRM1885C1H820JA01D
Murata
82 pF
1
C66
GRM155R71C183KA01D
Murata
18 nF
1
C67
08051A330JAT2A
AVX
33 pF
4
C69, C71, C95,
C96
GRM1555C1HR50CZ01
Murata
0.5 pF
2
C73, C74
GRM155R71C103KA01D
Murata
10 nF
3
C75, C76, C77
GRM155R71E472KA01
Murata
4700 pF
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User manual
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Rev. 3 — 10 October 2012
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Table 1.
Example BOM for a VSAT BUC with a 13.05 GHz LO …continued
Quantity
Reference
Type
Manufacturer
Value
3
C78, C79, C80
GRM1555C1H101JZ01
Murata
100 pF
1
C83
GRM155R71H471KA01D
Murata
470 pF
1
C84
GRM1555C1H121JA01D
Murata
120 pF
5
C85, C86, C87,
C88, C93
C3216X7R1C106M
TDK
10 F, 16 V
1
C98
GRM1555C1H120JZ01D
Murata
12 pF
2
D1, D5
SML-211YTT86
ROHM Semiconductor
SML-211YTT86
2
D3, D4
BB202
NXP Semiconductors
BB202
1
D9
BZX84-A5V1
NXP Semiconductors
BZX84-B5V
1
J1
90120-0762
Molex
CON-2PIN
1
J2
90120-0766
Molex
6PIN
1
J3
531-40047-4
Amphenol
CON-F-TYPE-THROU
GH
3
J4, J6, J7
903-415J-51P
Amphenol
SMB-V
1
J5
PSF-S01-005
GigaLane
GIGALANE
1
L1
LQW21HNR68J00L
Murata
680 nH
1
L2
MLF1608A2R7K
TDK
2.7 H
1
L3
B82496C3221J
EPCOS
220 nH
1
L4
LQW18AN39NJ00D
Murata
39 nH
1
L5
LQW18ANR10J00D
Murata
100 nH
1
L6
LQW18AN18NJ00D
Murata
18 nH
1
L7
LQW18AN33NJ00D
Murata
33 nH
2
L8, L9
LQW18AN6N8D00D
Murata
6.8 nH
1
L10
LQW18AN4N7D00D
Murata
4.7 nH
3
L11, L12, L13
BLM15AG100SN1D
Murata
BLM15AG100SN1D
2
M1, M2
PCB Copper
-
stub1
2
Q2, Q3
BFS17
NXP Semiconductors
BFS17
1
Q4
PMBTA45
NXP Semiconductors
PMBTA45
1
Q5
PBHV9050T
NXP Semiconductors
PBHV9050T
2
Q6, Q7
BFU730F
NXP Semiconductors
BFU730F
2
R1, R72
ERJ-3EKF22R0V
Panasonic - ECG
22 
3
R2, R7, R23
ERJ-3EKF10R0V
Panasonic - ECG
10 
11
R3, R4, R5, R6, R9, ERJ-3EKF1002V
R10, R13, R16,
R38, R39, R69
Panasonic - ECG
10 k
1
R15
ERJ-3EKF2702V
Panasonic - ECG
27 k
13
R17, R24, R27,
R31, R33, R34,
R35, R40, R41,
R42, R50, R51,
R68
<tbd>
Panasonic- ECG
DNP
2
R18, R28
ERJ-3EKF1212V
Panasonic - ECG
12.1 k
1
R19
ERJ-3EKF68R0V
Panasonic - ECG
68 
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Table 1.
Example BOM for a VSAT BUC with a 13.05 GHz LO …continued
Quantity
Reference
Type
Manufacturer
Value
1
R21
ERJ-3EKF9092V
Panasonic - ECG
90.9 k
3
R22, R30, R46
ERJ-2RKF2200X
Panasonic - ECG
220 
4
R25, R29, R48,
R49
ERJ-3EKF4701V
Panasonic - ECG
4.7 k
2
R26, R43
ERJ-3EKF1004V
Panasonic - ECG
1 M
1
R32
ERJ-3EKF2201V
Panasonic - ECG
2.2 k
2
R36, R58
ERJ-3EKF2701V
Panasonic - ECG
2.7 k
2
R37, R47
ERJ-3EKF82R0V
Panasonic - ECG
82 
2
R44, R45
ERJ-3GEY0R00V
Panasonic - ECG
0
1
R53
ERJ-3EKF3301V
Panasonic - ECG
3.3 k
1
R54
ERJ-3EKF6800V
Panasonic - ECG
680 
1
R59
ERJ-3EKF56R0V
Panasonic - ECG
56 
2
R60, R70
ERJ-3EKF2700V
Panasonic - ECG
270 
1
R71
ERJ-3EKF1000V
Panasonic - ECG
100 
1
R61
ERJ-2GEJ561X
Panasonic - ECG
560 
2
R62, R64
ERJ-2GEJ510X
Panasonic - ECG
51 
1
R63
ERJ-2GEJ240X
Panasonic - ECG
24 
3
R66, R67, R77
CRCW04020000Z0ED
Vishay/Dale
0
2
R73, R74
ERJ-2GEJ393X
Panasonic - ECG
39 k
1
R75
ERJ-2GEJ390X
Panasonic - ECG
39 
1
R76
ERJ-2GEJ390X
Panasonic - ECG
56 
1
R78
ERJ-3EKF123X
Panasonic - ECG
12 k
1
U1
LP3961EMP-3.3
National Semiconductors
LP3961EMP-3.3
1
U2
XC2C32A-6QFG32C
Xilinx
XC2C32A
1
U3
LP3961EMP-1.8
National Semiconductors
LP3961EMP-1.8
2
U4, U7
LMV7239M5
National Semiconductors
LMV7239
1
U9
74LVC1GX04GW
NXP Semiconductors
74LVC1GX04GW
1
U13
TFF1003
NXP Semiconductors
TFF1003
2
U14, U15
LP5900SD-3.3V
National Semiconductors
LP5900SD-3.3V
1
U16
OPA376AIDBVT
Texas Instruments
OPA376
1
U17
74AUP1G86GW
NXP Semiconductors
74AUP1G86GW
1
X2
<tbd>
Tai-Saw
40.78125 MHz
Table 2.
Power
Example BOM matrix for different power and frequency applications
Frequency (examples)
13.05 GHz
UM10484
User manual
7 GHz
11.25 GHz
15 GHz
7 dBm
BOM1
BOM2
BOM3
BOM4
10 dBm
BOM5
BOM6
BOM7
BOM8
13 dBm
BOM9
BOM10
BOM11
BOM12
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3.4 Evaluation equipment
The following equipment is required for evaluation tests.
•
•
•
•
Low-noise DC power supply output to at least 500 mA at 5 V
Precision ammeter to measure the supply current
RF power meter capable of measuring up to 20 GHz or above
Spectrum analyzer or signal analyzer with phase noise measurement feature capable
of measuring up to 20 GHz or above
• 10 MHz reference input for an input power level range of 15 dBm to +5 dBm with the
following phase-noise performance for divider N = 64:
–
135 dBc/Hz at 1 kHz offset
–
140 dBc/Hz at 10 kHz offset
–
150 dBc/Hz at 100 kHz offset
• RF cables and connectors with minimum loss at 18 GHz or above
3.5 Connections and setup
The demo board has a few variants, so it is important to identify the frequency and RF
power level of the demo board to be tested. Typically, the demo board is identified by
suitable markings when it is fully assembled and tested. A step-by-step guide for
operating and testing the demo board is as follows:
1. Connect the DC power supply to the VCC and GND terminal at J1 which is a 2-pin
terminal connector that can be clipped using a clip jacket.
2. Set the power supply to 5 V and current limiting to 400 mA.
3. Connect the RF output connector J5 to spectrum analyzer or power meter.
4. Turn on the power supply; the total current drawn must not exceed 300 mA.
5. LED D3 illuminates first, indicating that the TFF100X or TFF11XXX is in locked state.
Locked state is indicated without a 10 MHz reference input due to the wide range of
the TFF’s reference input frequency. It is assumed that the free-running VCXO output
is at the correct frequency, and at first lock. If the divider ratio is 64, it locks to the
frequency of 64  ffree-running-VCXO, but the Clean-Up-PLL is not locked until D1
illuminates.
6. Apply a 10 MHz reference input using a very low phase-noise source such as the
OCXO module with F-type input connectors. LED D1 illuminates, indicating the
Clean-Up-PLL is locked, and can be considered as a secondary lock ensuring the
whole system is locked onto the 10 MHz reference input.
7. Test the phase noise and power of the Clean-Up-PLL which is the reference input of
TFF100X/TFF11XXX at input J4.
8. Test the tuning voltage of the Clean-Up-PLL at test point VTUNE-PASSIVE if the loop
filter is a passive type.
9. Test overall phase noise and power at output J5 with the spectrum analyzer and
power meter.
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
4. Demo board typical measurement result
To demonstrate the performance of the integrated board, a representative board at
13.05 GHz for Ku band BUC is demonstrated in this document.
The following test result only refers to the final output performance of the demo board. For
detailed test results of each individual building block, refer to the respective user manual,
application note or data sheet.
For accurate measurement, use a suitable 10 MHz reference source in accordance with
the requirements previously mentioned.
In the following test result, a Vectron OCXO module is used, part number 718Y-4153. Its
phase noise plot is shown in Figure 10.
aaa-001268
Fig 10. Reference input phase noise of a Vectron 10 MHz OCXO module
4.1 Demo board typical test result
fref input frequency = 10 MHz; Pref_in input power level = 0 dBm.
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
Table 3.
Typical results measured on the demo board
Test board example: 13.05 GHz for VSAT BUC; room temperature with 5 V power supply.
ID
Parameter
Conditions
1
current consumption
2
phase noise out; see
Figure 11
Min
Typ
Max
Unit
-
195
-
mA
1 kHz offset
-
96
-
dBc/Hz
10 kHz offset
-
102
-
dBc/Hz
100 kHz offset
-
101
-
dBc/Hz
1 MHz offset
-
108
-
dBc/Hz
3
spurious
reference
-
70
-
dBc
4
output power (13.05 GHz)
7 dBm version
-
7.1
-
dBm
10 dBm version
-
9.8
-
dBm
13 dBm version
-
13.2
-
dBm
aaa-001269
Fig 11. Phase noise and power output at 13.05 GHz (+10 dBm version)
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
5. Abbreviations
Table 4.
UM10484
User manual
Abbreviations
Acronym
Description
BOM
Bill Of Materials
BUC
Block-Up-Converter
CPLD
Complex Programmable Logic Device
CW
Continuous Wave
PLL
Phase-Locked Loop
OCXO
Oven-Controlled crystal Oscillator
PCB
Printed-Circuit Board
VCXO
Voltage-Controlled crystal Oscillator
VSAT
Very Small Aperture Terminal
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6. Legal information
6.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
6.2
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
UM10484
User manual
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
non-infringement, merchantability and fitness for a particular purpose. The
entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
any other theory, even if advised of the possibility of such damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
6.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
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Integrated clean-up-PLL, TFF1xxxx and buffer amplifier
7. Contents
1
2
2.1
2.2
3
3.1
3.2
3.3
3.4
3.5
4
4.1
5
6
6.1
6.2
6.3
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General description . . . . . . . . . . . . . . . . . . . . . . 4
High-level function review. . . . . . . . . . . . . . . . . 4
Description of individual function blocks . . . . . . 5
Application board . . . . . . . . . . . . . . . . . . . . . . . 6
Application circuit . . . . . . . . . . . . . . . . . . . . . . . 6
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . 11
Evaluation equipment . . . . . . . . . . . . . . . . . . . 15
Connections and setup . . . . . . . . . . . . . . . . . . 15
Demo board typical measurement result . . . 16
Demo board typical test result . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 October 2012
Document identifier: UM10484