NSC LMK3001

LMK3001
Precision Clock Conditioner with Integrated VCO
Evaluation Board Operating Instructions
11-10-2006
National Semiconductor Corporation
Interface
2900 Semiconductor Dr.
MS A2-600
Santa Clara, CA, 95052-8090
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TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................................................... 3
LOOP FILTER ................................................................................................................................................ 3
READ FIRST, BASIC OPERATION ................................................................................................................... 4
BOARD INFORMATION .................................................................................................................................. 8
OSCin ................................................................................................................................................... 8
Fin ......................................................................................................................................................... 8
Fout ....................................................................................................................................................... 8
Loop Filter ............................................................................................................................................ 8
Features of the board............................................................................................................................. 9
Other Important Notes .......................................................................................................................... 9
RECOMMENDED EQUIPMENT...................................................................................................................... 10
DELAYS...................................................................................................................................................... 11
CODELOADER SETTINGS ............................................................................................................................ 12
APPENDIX A: SCHEMATIC .......................................................................................................................... 16
APPENDIX B: BILL OF MATERIALS ............................................................................................................. 19
APPENDIX C: BUILD DIAGRAM .................................................................................................................. 22
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General Description
The LMK3001 Evaluation Board simplifies evaluation of the LMK3001 Precision Clock Conditioner with
Integrated VCO. The package consists of a characterization board, a USB <--> uWire buffer board,
and CodeLoader software. The CodeLoader software will run on a Windows 2000 or Windows XP PC.
The purpose of the CodeLoader software is to program the internal registers of the LMK3001 device
TM
through a MICROWIRE interface.
Loop Filter
3200 uA
59.1 kHz
Kφ
φ
Fcomp
Crystal Frequency
10 MHz
Output Frequency
1470 to 1570 MHz
Supply Voltage
3.3 Volts
VCO Gain
10 MHz/Volt
Phase Margin
74.4º
Loop Bandwidth
10 MHz
Charge Pump
R3
100 Ω
R4
100 Ω
VCO
C2
12 nF
C3
100 pF
C4
110 pF
R2
1.8 kΩ
Ω
C1
open
CPout
This loop filter is located on the bottom side of the PCB and is selected by
placing a 0 ohm resistor on pad R137.
This loop filter has been designed for optimal RMS jitter using a low noise
reference.
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Read first, Basic Operation
Read the document, “Installing CodeLoader 4 & USB Driver” for instructions to prepare the computer
for usage with the characterization board before continuing with the hardware setup.
For basic operation…
1. Connect a low noise 3.3 V power supply to the Vcc connector located at the top left of the
board
2. Connect a 10 MHz reference signal to the OSCin connector located on the right side of the
board.
3. Connect the CodeLoader cable to the uWire header located in the lower left.
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Read first, Basic Operation (Continued)
4. Connect the USB <--> uWire board to the PC with the USB cable.
USB Setup
The USB <--> uWire board must be connected and operating (both
LEDs solid) before CodeLoader is started.
If CodeLoader is started before the USB <--> uWire board is
connected communications with target board will not work. If this is
done, exit CodeLoader and start CodeLoader again.
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Read first, Basic Operation (Continued)
5. Start CodeLoader 4.
6. Select the USB Communication Mode on the Port Setup tab.
7. Select the default mode by clicking “Mode” “10 MHz OSC”
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Read first, Basic Operation (Continued)
8. Enable output to be measured, any of CLKout(0-7) or EN_Fout from either Clock Outputs or
Bits/Pins tab.
9. Program the part by clicking “Keyboard Controls” “Load Device” or by pressing Ctrl+L.
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Board Information
Notes on the operation of the board are included here.
OSCin
The board is configured to accept a single ended OSCin source, however it is also possible to drive
OSCin with a differential signal by changing the following components.
Differential OSCin setup
0 ohm
R35, R36, R38, R39
100 ohm
R44
0.1 uF
C24, C25 (C6 is a 0.1 uF 0402 cap which may be moved to C25)
Open
C6
The single ended setup uses the following components.
Single ended OSCin setup
0 ohm
R35, R38
51 ohm
No pad for this. Place between R44 pad on C24 side and GND
0.1 uF
C24, C6 (C25 is a 0.1 uF 0402 cap which may be moved to C6)
Open
C25
Fin
Fin is placed on the board for testing other devices in the footprint compatible family.
Fout
Fout allows direct access to the internal VCO before the clock distribution section. The EN_Fout bit
must be selected to enable Fout. A 3 dB pad is placed on R103, R104, and R105.
Loop Filter
R4 and R137 form a “resistor switch” which allows either one of two different loop filters to be
selected.
Resistor
Switch
R4 Shorted
Loop Filter
Location
Top of board
Loop Filter
Components
C1, C2, R2, C101
Default Loop
Bandwidth
77 Hz
R137 Shorted
Bottom of board
C97, C4, R139, C100
59.1 kHz
The following table services as a cross reference from traditional loop filter component
designators to the designators on the characterization board. Also, on the board below each loop
filter is an offset diagram illustrating the positions of each loop filter component using traditional
C1, C2, C2p, R2 designators.
Traditional
Textbook
designators
C1
C2
C2p
R2
Top
Loop Filter
designators
C1
C2
C101
R2
Bottom
Loop Filter
designators
C97
C4
C100
R139
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Features of the board
•
•
•
•
•
•
•
•
Either one of two loop filters can be selected by shorting either R137 or R4. More info
about each loop filter can be found in the General Description and Appendix A.
Test points for each of the uWire lines are scattered in the lower left corner of the board
and include: GOE_TP, DATAuWire, CLKuWire, LEuWire, SYNC_TP, LD_TP, Pin10_TP,
Pin7_TP, Pin5_TP.
Ground is located on each pin GND_J1, the 10 pin header on the left side of the board.
Ground is located on the GND_tp2 in the upper left corner of the board and GND_tp1
located to the right of the Vcc SMA connector.
Ground is located on the bottom side of the board on each pad of the unstuffed 10 pin
header GND_J2.
Vcc is located on each pin of VCC_J1, the 10 pin header on the upper left side of the
board.
Vcc is located on VccPlane test point located to the right of the Vcc SMA.
Vcc is located on the bottom side of the board on each pad of the unstuffed 10 pin
header VCC_J2
Other Important Notes
•
•
•
•
For both loop filters on the top and bottom side of the board, a helper silkscreen is offset
from the loop filters to help identify the components by National Semiconductor’s
traditional reference designators associated with loop filters.
When changing the OSCin frequency, the OSCin frequency register needs to be changed
to match.
Toggle the SYNC* pin to synchronize the clock outputs
Errata: SYNC* is labeled on the PCB as SYNC, however the logic of SYNC* is still active
low!
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Recommended Equipment
Power Supply
The Power Supply should be a low noise power supply. An Agilent 6623A Triple power supply with LC
filters on the output to reduce noise was used in creating these evaluation board instructions.
Phase Noise / Spectrum Analyzer
For measuring phase noise an Agilent E5052A is recommended. An Agilent E4445A PSA Spectrum
Analyzer with the Phase Noise option is also usable although the architecture of the E5052A is superior
for phase noise measurements.
Oscilloscope
For measuring delay an Agilent Infiniium DSO81204A was used.
Reference Oscillator
Either a 10 MHz crystal or the reference output of any RF test equipment will serve as a 10 MHz
output.
Note: The default loop filter has a loop bandwidth of ~60 kHz. Inside the loop bandwidth of a PLL the
noise is greatly affected by any noise on the reference oscillator (OSCin). Therefore any noise on the
oscillator less than 60 kHz will be passed through and seen on the outputs. For this reason the main
output of a Signal Generator is not recommended for driving OSCin in this setup. Instead use the 10
MHz reference output of the signal generator.
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Delays
These delay measurements illustrate how skew errors due to different length traces may be tuned out.
The delay may be adjusted in steps of 150 ps.
Delays 150, 300, 450, 600, 750
CLKout0_DLY = 0 ps
CLKout1_DLY = all delays
programmed: 0, 150, 300, 450,
600, 750, 900, 1050, 1200,
1350, 1500, 1650, 1800, 1950,
2100, and 2250 ps
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CodeLoader Settings
The USB <--> uWire board must be connected and operating (both
LEDs solid) before CodeLoader is started.
If CodeLoader is started before the USB <--> uWire board is
connected communications with target board will not work. If this is
done, exit CodeLoader and start CodeLoader again.
The Port Setup tab tells CodeLoader what signals are assigned to which pins. If this is wrong,
the part will not program.
Part setup can be restored to the default state by clicking Mode “10 MHz OSC.” The default
reference oscillator used for these instructions is 10 MHz and the restored mode expects a 10
MHz OSCin signal. For the loaded mode to take affect the device must be loaded by
pressing Ctrl+L.
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The Bits/Pins tab shows some of the internal registers which are not accessible from any of the
other visual tabs like “PLL” and “Clock Outputs.”
Program Bits
POWERDOWN
EN_Fout
OSCin_FREQ
INPUT_DIV
PLL_MUX
VCO_R3_LF
VCO_R4_LF
VCO_C3_C4_LF
EN_CLKout0..7
EN_CLKout_Global
Program Pins
GOE
SYNC*
TRIGGER
Powers the part down.
Turns on the Fout pin for measuring the internal VCO.
Must be set to the OSCin frequency in MHz.
This control also exists on the Clock Outputs page, it sets the value of the
input divider.
Programmable to many different values to support Lock Detect or aid
troubleshooting.
Internal loop filter values, also accessible from Clock Outputs tab.
Enable CLKout bits from CLKout0 to CLKout7. Also accessible from Clock
Outputs tab.
Enable all clock outs. If unselected then the EN_CLKouts are overridden
and the outputs are all disabled.
Set Global Output Enable to high or low logic level
Set SYNC* pin to high or low logic level
Set auxiliary trigger pin to high or low logic level.
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The Registers tab shows the raw bits which will be programmed when device is loaded by
clicking Keyboard Controls Load Device or Ctrl+L.
The Clock Outputs tab allows the user to visualize the clock distribution portions of the device.
From this tab the device’s dividers, delays, clock output muxes, and output drivers can be
programmed along with internal loop filter values. The PLL block shows the R and N divider
values however to change these values either click on the PLL tab or the blue PLL box to access
the PLL tab to make changes to the PLL.
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The PLL tab shows a conventional PLL diagram along with the Input Divider. It is important to
realize that the total effective N value is PLL N Counter * Input Divider. This means that the
“channel spacing” is the Phase Detector Frequency * Input Divider. Depending on the
situation, this may require the R Counter multiplied up by the value of the Input Divider to achieve
desired VCO output frequencies.
Example: If the desired VCO output frequency was 1501 MHz, R would need to be increased to
20 before 1501 MHz could be programmed because of the Input Divider of 2 would only allow
programming of 1500, 1502, 1504, etc. with a 1 MHz phase detector frequency.
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Appendix A: Schematic
1
2
3
4
6
5
D
D
Timex - Main Board
Timex - Main Board.sch
Timex - Outputs
Timex - Outputs.sch
F1
SMA_CONN
C
C
Vcc
Vcc
GND_J1
1
3
5
7
9
VCC_J1
2
4
6
8
10
1
3
5
7
9
HEADER_2X5
B
2
4
6
8
10
HEADER_2X5
B
Vcc
Vcc
GND_J2
1
3
5
7
9
VCC_J2
2
4
6
8
10
HEADER_2X5
1
3
5
7
9
2
4
6
8
10
HEADER_2X5
A
A
Title
Size
Number
Revision
B
Date:
File:
1
2
3
4
16
5
1-Sep-2006
C:\worksvn\Timex-EvalBoard\Timex.ddb
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1
U2
LM317
R145
VinLDO
1
Vin
Open
Vout
VinLDO
R99
Open
3
U3
R146
4
Open
2
LM317_out
C15
Open
2
C5
Open
LM317_out
3
8
3
R144
Open
Open
C14
Open
R98
Open
C104
Open
4
LP2989_out
Input
Output
NC
Sense
/Shutdown
/Error
GND
Bypass
R100
Open
C75
Open
7
R37
Open
1
C53
Open
LP2989
C13
Open
0 ohm
6
4
R36
Open
R1
0
R33
Open
R34
Open
GND_tp2
0.1 uF
R44
Open
TCXO
C56
Open
D
DUT_OSCin*
Open
1
Open
Open
Open
R45
Open
C25
R39
R9
C35
Open
C105
C6
Open
0.1 uF
C94
Open
2
Vcont
Vcc
GND
Out
Y1 4
TCXO
3
TCXO_RF
VccPlane
Vcc3
R7
0
C9
10 uF
C10
10 uF
0
Fout
0
VCO
Open
R149
C59
100 pF
DIG
C108
Open
DIG_vcc_tp
C110
Open
0
C60
100 pF
Vcc9
R15
0
OSCin
R52 0
C61
100 pF
PDCP
C109
0.1 uF
PDCP_vcc_tp
0
R152
51 ohm
R154
51 ohm
0.1 uF
C106
C7
Open
Open
R141
Open
U4
R56
1
Open
Vtune
2
C95
Open
5
RF*
GND
R148
Open
6
Vs
NC
3
R101
Open
C99
Open
C107
Open
VCXO_RF*
4
RF
VCXO_RF
VCXO - C5310
C
R147
Open
R41
Open
VCXO_RF
R102
Open
CLK6
VtuneVCO
Vcc14
0
VCO
U5
R57
1
Open
CLK7
C68
100 pF
Vt
2
C96
Open
G
3
Vcc
Synth
7
NC
6
G
5
Fout
VCO_RF
4
C62
100 pF
VtuneVCXO
DUT_Fin*
Open
CLK5
C67
100 pF
R18
Vcc10
R12
VCXO
C69
Open
C49
R50
SMA
Open
C50
Open
0.1 uF
TC1-1-13M+
Vcc13
0
Open
PDCP_vcc
C111
Open
P
R55
Open
1
2
3
Sd
NC
S
VCXO_RF*
C66
100 pF
R20
Open
R150
DUT_Fin
Pd
R21
8
0
R135
0 ohm
Vcc12
R17
Vcc8
R11
4
R47
Open
CLK4
Vcc
C48
B2
Fin*
C65
100 pF
R54
Open
R49
6
CLK3
C64
100 pF
0
Open
DIG_vcc
Fin
R153
Open
Open
Vcc11
R19
Vcc7 Open
R51
0
R151
Open
R46
0 ohm
SMA
0
C58
100 pF
R14
Vcc6
VCXO_pwr
Open
Vcc
Fin
VCO_RF
CLK2
C63
100 pF
R16
Vcc2
R10
CLK1
R48
Open
0
C57
100 pF
C55
100 pF
Vcc5
R8
Vcc1
CLK0
Vcc
0
R13
C54
100 pF
Vcc4
R6
C3
10 uF
C
1
2
3
Sd
NC
S
P
SMA
Vcc
C11
10 uF
R134
Open
Pd
OSCin*
GND_tp1
Vcc
Vcc
DUT_OSCin
B1
SMA
LM317_out LP2989_out
R53
Open
R44_opt
51 ohm
C24
R38
R35
0 ohm
OSCin
D
Vin
6
TCXO_pwr
Open
OSCin
TCXO_RF
6
5
LP2989_out
5
G
VccLDO
C12
Open
VinLDO
I N S T R U C T I O N S
G
0
SMA
O P E R A T I N G
2
Vin
R5
Vadj
Vcc
B O A R D
VCO_pwr
Open
Vcc
C17
1 uF
C36
0.1 uF
C26
1 uF
C37
0.1 uF
C18
1 uF
C38
0.1 uF
C27
1 uF
C39
0.1 uF
C19
1 uF
C40
0.1 uF
C28
1 uF
C41
0.1 uF
C22
1 uF
C46
0.1 uF
C16
1 uF
C33
0.1 uF
C23
1 uF
C34
0.1 uF
C20
1 uF
C42
0.1 uF
C29
1 uF
C43
0.1 uF
C21
1 uF
C44
0.1 uF
C30
1 uF
C45
0.1 uF
C31
1 uF
C47
0.1 uF
R136
Vcc
R142
Open
Open
C103
Open
C102
Open
Vcc
CLKout6
CLKout6*
Vcc
B
10
R31
Open
GOE
R32
1
R69
Open
LDObyp2
Vcc
C77
10 uF
Pin5_TP
R65
Open
C51
Open
R29
15 k
R43
12
39
37
38
42
40
41
45
43
44
LEuWire
Vcc11
CLKout4
CLKout4*
Vcc12
Vcc13
CLKout5
CLKout5*
Vcc8
Vcc2
OSCin*
LDObyp1
OSCin
LDObyp2
SYNC
GOE
Vcc7
LD
GND
C52
0.1 uF
Vcc3
C74
R68
100 pF 27 k
Vcc9
DS8SF18I
NC
GOE_TP LD_TP
SYNC
Open
11
LD
CPout
Vcc3
1
3
5
7
9
R30
1
LDObyp1
Vcc10
DATAuWire
Vcc4
Vcc5
35
DUT_Fin
29
Open
C2
Open
0
R137
C1
820 nF
DUT_OSCin*
28
R40
Open
R3
0
R4
32
Vcc9
31
Vcc8
30
R143
C101
10 uF
Open
R138
R2
820
DUT_OSCin
27
Vcc7
26
25
SYNC
SYNC_TP
R140
C4
Open
C97
Open
C100
12 nF
Open
A
C98
Open
R139
1.8 k
CLKout3*
CLKout3
Title
CLKout2*
CLKout2
Size
Number
Revision
C
Date:
File:
1
2
3
4
17
Vtune
Open
Open
Vcc6
CLKout0
CLKout0*
CLKout1
CLKout1*
VtuneVCXO VtuneVCO
DUT_Fin*
34
Vcc10
33
CLKout3*
9
CLKuWire
CLKout3
8
Fin
Vcc6
7
Vcc2
R28
15 k
Pin7_TP
SYNC
Open
B
R64
Open
36
24
R66
27 k
6
Fin*
Vcc1
23
C73
1 uF
5
Fout
22
LEuWire
4
CLKout2*
CLKuWire
DATAuWire
uWire
HEADER_2X5
R42
Open
3
21
R104
270
Open
2
4
6
8
10
R67
Open
GOE
47 pF
R103
270
Fout*
Pin10_TP
GOE
Open
Vcc1
18 ohms
4
C32
1 uF
Bias
CLKout2
P
Open
GND
Vcc5
Pd
2
CLKout1*
Sd
NC
S
C76
R105
6
20
SMA
1
TC1-1-13M+
19
0
CLKout6
R26
B3
1
2
3
CLKout6*
LD
Open
CLKout1
0
Fout
Vcc
46
48
R25
C8
Open
R63
Open
Vcc4
R62
15 k
18
R24
15 k
17
R60
27 k
16
C72
Open
Vcc14
R23
15 k
CLKout7
R59
27 k
CLKout7*
C71
Open
GND
R22
15 k
R27
0
Vcc11
0
R58
27 k
CLKout0*
CLKuWire
C70
Open
Vcc12
U1
CLKout0
LD
15
LEuWire
47
R61
Open
14
DATAuWire
Vcc13
LEuWire
13
DATAuWire
Vcc
CLKout4*
CLKout4
Vcc14
CLKuWire
A
CLKout5*
CLKout5
CLKout7
CLKout7*
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2
Vcc
3
Vcc
Vcc
CLKout0
4
Vcc
R78
Open
C78
CLKout0
R84
Open
C80
CLKout1
PC0
PC0b
C79
PC1
PC1b
CLKout0*
C81
Vcc
R75
Open
R76
Open
C83
Vcc
R81
Open
R120
Open
C86
CLKout4
Vcc
C87
R94
Open
CLKout5
C89
CLKout6
R113
125
CLKout5*
CLKout7
0.1 uF
C91
R129
Open
R125
Open
C92
R96
Open
PC7
PC7b
CLKout6*
C93
R97
Open
CLKout7*
CLKout7*
0.1 uF
R128
Open
Vcc
CLKout7
CLKout6*
R112
125
R93
Open
C
R124
Open
PC6b
0.1 uF
R127
Open
Vcc
R123
Open
PC6
CLKout5*
0.1 uF
R91
Open
Vcc
C90
R95
Open
CLKout3*
R89
Open
0.1 uF
PC5b
CLKout4*
R126
Open
R88
Open
CLKout6
PC5
CLKout4*
R87
Open
CLKout7
R122
Open
0.1 uF
PC4b
PC3b
C85
0.1 uF
R85
Open
R121
Open
CLKout5
0.1 uF
PC4
R111
125
R83
Open
Vcc
C88
CLKout4
PC3
CLKout2*
CLKout6
R119
Open
D
CLKout3
R109
Open
CLKout3*
R82
Open
CLKout5
R118
Open
R110
125
PC2b
R108
Open
0.1 uF
R79
Open
Vcc
CLKout4
C
R77
Open
R92
Open
C84
0.1 uF
PC2
CLKout1*
0.1 uF
R73
Open
Vcc
CLKout3
CLKout2*
0.1 uF
R71
Open
CLKout2
0.1 uF
R107
Open
CLKout1*
R70
Open
R90
Open
C82
0.1 uF
CLKout0*
R86
Open
CLKout2
0.1 uF
R106
Open
Vcc
CLKout3
R80
Open
CLKout1
6
Vcc
CLKout2
R74
Open
CLKout0
5
Vcc
CLKout1
R72
Open
D
I N S T R U C T I O N S
R114
125
R115
125
0.1 uF
R130
Open
R131
Open
R116
125
R117
125
R132
Open
R133
Open
B
B
A
A
Title
Size
Number
Revision
C
Date:
File:
1
2
3
4
18
5
1-Sep-2006
C:\worksvn\Timex-EvalBoard\Timex.ddb
Sheet of
Drawn By:
6
L M K 3 0 0 1
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix B: Bill of Materials
Part
Capacitors
47 pF
Manufacturer
Part Number
Quant
Identifier
Kemet
C0603C470J5GAC
1
100 pF
100 pF
Kemet
Kemet
C0402C101J5GAC
C0603C101J5GAC
14
1
0.1 uF
Kemet
C0402C104J4RAC
20
0.1 uF
0.1 uF
12 nF
820 nF
Kemet
Kemet
Kemet
Kemet
C0603C104J3RAC
C0603C104J3RAC
C0805C123K4RAC
C0603C824K4RAC
15
1
1
1
1 uF
1 uF
10 uF
10 uF
Kemet
Kemet
Kemet
Kemet
C0603C105K8VAC
C0603C105K8VAC
C0805C106K9PAC
C0805C106K9PAC
15
1
2
4
C76
C54, C55, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67,
C68
C74
C6, C24, C48, C49, C78, C79, C80, C81, C82, C83, C84, C85, C86,
C87, C88, C89, C90, C91, C92, C93
C33, C34, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46,
C47, C52
C109
C100
C1
C16, C17, C18, C19, C20, C21, C22, C23, C26, C27, C28, C29, C30,
C31, C73
C32
C77, C101
C3, C9, C10, C11
ERJ-2GE0R00X
CRCW0603000ZRT1
CRCW0603000ZRT1
CRCW0603000ZRT1
CRCW0603010JRT1
CRCW0603180JRT1
ERJ-2GEJ510X
CRCW0603510JRT1
ERJ-2GEJ121X
CRCW0603271JRT1
CRCW0603821JRT1
15
9
1
1
2
1
2
1
8
2
1
R6, R7, R8, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
R52
R1, R3, R5, R25, R35, R38, R46, R135, R137
R27
R26
R30, R32
R105
R152, R154
R44_opt (connected from one pad of R44 to GND)
R110, R111, R112, R113, R114, R115, R116, R117
R103, R104
R2
Resistors
0 ohm
0 ohm
0 ohm
0 ohm
1 ohm
18 ohms
51 ohms
51 ohms
120 ohms
270 ohms
820 ohms
Panasonic
Vishay
Vishay
Vishay
Vishay
Vishay
Panasonic
Vishay
Panasonic
Vishay
Vishay
19
L M K 3 0 0 1
1.8 k
15 k
27 k
E V A L U A T I O N
B O A R D
Vishay
Vishay
Vishay
O P E R A T I N G
I N S T R U C T I O N S
CRCW0603182JRT1
CRCW0603153JRT1
CRCW0603273JRT1
1
6
5
R139
R22, R23, R24, R28, R29, R62
R58, R59, R60, R66, R68
SMA Connectors
SMA_EDGE
Johnson Components
142-0701-851
1
SMA_EDGE
SMA_EDGE
Johnson Components
Johnson Components
142-0701-851
142-0701-851
8
5
Vcc
CLKout0, CLKout0*, CLKout3, CLKout3*, CLKout4, CLKout4*, CLKout7,
CLKout7*
Fin, Fin*, OSCin, OSCin*, Fout
52601-S10-8
HTSM3203-10G2
TC1-1-13M+
LMK30xxEB_PCB
SPCS-8
LMK3001
1
2
1
1
4
1
uWire
GND_J1, VCC_J1
B2
Standoffs in the four corners (insert from bottom)
U1
Other
HEADER_2X5
HEADER_2X5
BALUN - TC1-1-13M+
PCB
SPCS-8
LMK3001 Device
FCI Electronics
Comm Con Connectors
Minicircuits
Printed Circuits Corp.
SPC Technology
National
Open
Open
Capacitors
Open
Open
Resistors
Comm Con Connectors
Open
Johnson Components
35
HTSM3203-10G2
90
2
142-0701-851
19
20
C2, C4, C5, C7, C8, C12, C13, C14, C15, C25, C35, C50, C51, C53,
C56, C69, C70, C71, C72, C75, C94, C95, C96, C97, C98, C99, C102,
C103, C104, C105, C106, C107, C108, C110, C111
R4, R9, R21, R31, R33, R34, R36, R37, R39, R40, R41, R42, R43, R44,
R45, R47, R48, R49, R50, R51, R53, R54, R55, R56, R57, R61, R63,
R64, R65, R67, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78,
R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91,
R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R106,
R107, R108, R109, R118, R119, R120, R121, R122, R123, R124, R125,
R126, R127, R128, R129, R130, R131, R132, R133, R134, R136, R138,
R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150,
R151, R153
GND_J2, VCC_J2
CLKout1, CLKout1*, CLKout2, CLKout2*, CLKout5, CLKout5*, CLKout6,
CLKout6*, Vtune, Fout*, LD, GOE, SYNC, VccLDO, DIG_vcc,
L M K 3 0 0 1
Open
E V A L U A T I O N
Minicircuits
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
TC1-1-13M+
2
21
PDCP_vcc, TCXO_pwr, VCO_pwr, VCXO_pwr
B1, B3
L M K 3 0 0 1
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Appendix C: Build Diagram
22
L M K 3 0 0 1
E V A L U A T I O N
B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Bottom Build Diagram
23