View detail for Hibernate Mode in the AT73C238/AT73C239

Hibernate Mode in the AT73C238/AT73C239
1. Scope
This application note decribes the hibernate mode for the AT73C238/AT73C239.
1.1
Power
Management
Reference Documents
Table 1-1 gives the references of the documents and their denominations in this
document.
Table 1-1.
Reference Documents
Owner - Reference
Title
Atmel - 6201.pdf
AT73C239 Technical Datasheet
Application
Note
6240A–PMAAC–19-May-06
2. Operating Conditions
Table 2-1.
AT73C238/AT73C239 Operating Conditions
Parameter/Function
Pads
Operating Temperature
Conditions
Min
Max
Unit
--
-40
85
°C
Main Input Voltage
VDD1, VDD2, VDD3
3.0
3.6
V
Backup Input Voltage
VBAT
2.5
3.6
V
LDO1 Trimming
vo1
Trimmed @ 2.75V
2.7
2.8
V
LDO2 Trimming
vo2
Trimmed @ 1.8V
1.75
1.85
V
LDO3 Trimming
vo3
Trimmed @ 1.5V
1.45
1.55
V
LDO4 Trimming
vo4
Trimmed @ 1.5V
1.4
1.6
V
3. Glossary
Hibernate Mode -- When this mode is activated, the baseband enters very low consumption
mode. In this mode, only the RTC block of the baseband is running, thus the main LDOs are
switched off.
Trimming -- Action on internal fuse to adjust the output voltage value to the targeted value.
2
Application Note
6240A–PMAAC–19-May-06
Application Note
4. Block Diagram With Hibernate Mode
Figure 4-1.
Standard Application Diagram with Hibernate Mode
LDO1
VBG
VBG
HPBG
VDD1
VIN
GPS
Antenna
VDD
3.0V-3.6V
VOUT
1.8V/2.7V
GNDA/AVSS
VO1
Internal Oscillator
VIN
3.0V
I/O
NC
100 k
Baseband
COUT1
XRESIN
TWD
LDO2
VDD2
VIN
LNA
Reset Generator
TWCK
GPIO
TCXO
ILOAD 25 mA
TWI
RF
VDD
3.0V-3.6V
XRESO
rstin
GNDD
SM
VOUT
1.5V/1.8V
VO2
ILOAD 30 mA
Fuse1
3.0V I/O
Supply
Fuse2
COUT2
VZAP
VMON
POR1
3.0V I/O
Backup Supply
VBAT
VBAT
POR2
LDO4
LDO3
VBAT
2.5V-3.6V
VDD
3.0V-3.6V
VOUT
1.2V/1.5V/1.8V
VOUT
1.2V/1.5V/1.8V
ILOAD 2 mA
ILOAD 60 mA
VIN 3.3V
VO3
VO4
1.5V
Backup Core
COUT4
VDD3
Main Supply
LPBG
1.5V Core
5. Hibernate Mode
5.1
Scope
Hibernate mode puts the application in very low consumption mode. During this phase, the consumption is less than 2mA. In order to achieve this, all the main LDOs are switched off (LDO1,
LDO2 and LDO3) by activating the “twck” pin to low level. Only LDO4 remains active so that the
baseband RTC block may continue working.
To wake up the device (equivalent to quitting Hibernate Mode), a high level should be applied on
the “twck” pin. This switches on the main LDOs.
3
6240A–PMAAC–19-May-06
5.2
Timing Diagram
Figure 5-1 shows the timing diagram of the behavior of each LDO output voltage for Hibernate
Mode.
Figure 5-1.
Hibernate Mode Timing Diagram
Vin
3.0V - 3.6V
Time
Vbat
2.5V - 3.6V
Time
TWD
Time
TWCK
LDO1
Time
2.75V
LDO2
Time
1.8V
Time
LDO3
1.5V
Time
LDO4
1.5V
Time
300 µs
4
Application Note
6240A–PMAAC–19-May-06
Application Note
5.3
Output Voltage Values and Behavior on Silicon
Table 5-1.
AT73C238/AT73C239 Product Output Voltages
Parameter/Function
Pads
LDO1 Output Voltage
vo1
Conditions
VBAT = VIN = 3.3V, in Normal Mode
2.75
V
0
V
1.8
V
0
V
1.5
V
0
V
VBAT = VIN = 3.3V, in Normal Mode
1.5
V
VBAT = VIN = 3.3V, in Hibernate Mode
1.5
V
VBAT = VIN = 3.3V, in Hibernate Mode
VBAT = VIN = 3.3V, in Normal Mode
LDO2 Output Voltage
vo2
VBAT = VIN = 3.3V, in Hibernate Mode
VBAT = VIN = 3.3V, in Normal Mode
LDO3 Output Voltage
vo3
VBAT = VIN = 3.3V, in Hibernate Mode
LDO4 Output Voltage
Figure 5-2.
Note:
Unit
vo4
Hibernate Mode Timing Diagram on Silicon
These measurements were done without any output loads.
5
6240A–PMAAC–19-May-06
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